1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 STMMAC Common Header File 4 5 Copyright (C) 2007-2009 STMicroelectronics Ltd 6 7 8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 9 *******************************************************************************/ 10 11 #ifndef __COMMON_H__ 12 #define __COMMON_H__ 13 14 #include <linux/etherdevice.h> 15 #include <linux/netdevice.h> 16 #include <linux/stmmac.h> 17 #include <linux/phy.h> 18 #include <linux/mdio-xpcs.h> 19 #include <linux/module.h> 20 #if IS_ENABLED(CONFIG_VLAN_8021Q) 21 #define STMMAC_VLAN_TAG_USED 22 #include <linux/if_vlan.h> 23 #endif 24 25 #include "descs.h" 26 #include "hwif.h" 27 #include "mmc.h" 28 29 /* Synopsys Core versions */ 30 #define DWMAC_CORE_3_40 0x34 31 #define DWMAC_CORE_3_50 0x35 32 #define DWMAC_CORE_4_00 0x40 33 #define DWMAC_CORE_4_10 0x41 34 #define DWMAC_CORE_5_00 0x50 35 #define DWMAC_CORE_5_10 0x51 36 #define DWXGMAC_CORE_2_10 0x21 37 #define DWXLGMAC_CORE_2_00 0x20 38 39 /* Device ID */ 40 #define DWXGMAC_ID 0x76 41 #define DWXLGMAC_ID 0x27 42 43 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */ 44 45 /* These need to be power of two, and >= 4 */ 46 #define DMA_TX_SIZE 512 47 #define DMA_RX_SIZE 512 48 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1)) 49 50 #undef FRAME_FILTER_DEBUG 51 /* #define FRAME_FILTER_DEBUG */ 52 53 /* Extra statistic and debug information exposed by ethtool */ 54 struct stmmac_extra_stats { 55 /* Transmit errors */ 56 unsigned long tx_underflow ____cacheline_aligned; 57 unsigned long tx_carrier; 58 unsigned long tx_losscarrier; 59 unsigned long vlan_tag; 60 unsigned long tx_deferred; 61 unsigned long tx_vlan; 62 unsigned long tx_jabber; 63 unsigned long tx_frame_flushed; 64 unsigned long tx_payload_error; 65 unsigned long tx_ip_header_error; 66 /* Receive errors */ 67 unsigned long rx_desc; 68 unsigned long sa_filter_fail; 69 unsigned long overflow_error; 70 unsigned long ipc_csum_error; 71 unsigned long rx_collision; 72 unsigned long rx_crc_errors; 73 unsigned long dribbling_bit; 74 unsigned long rx_length; 75 unsigned long rx_mii; 76 unsigned long rx_multicast; 77 unsigned long rx_gmac_overflow; 78 unsigned long rx_watchdog; 79 unsigned long da_rx_filter_fail; 80 unsigned long sa_rx_filter_fail; 81 unsigned long rx_missed_cntr; 82 unsigned long rx_overflow_cntr; 83 unsigned long rx_vlan; 84 unsigned long rx_split_hdr_pkt_n; 85 /* Tx/Rx IRQ error info */ 86 unsigned long tx_undeflow_irq; 87 unsigned long tx_process_stopped_irq; 88 unsigned long tx_jabber_irq; 89 unsigned long rx_overflow_irq; 90 unsigned long rx_buf_unav_irq; 91 unsigned long rx_process_stopped_irq; 92 unsigned long rx_watchdog_irq; 93 unsigned long tx_early_irq; 94 unsigned long fatal_bus_error_irq; 95 /* Tx/Rx IRQ Events */ 96 unsigned long rx_early_irq; 97 unsigned long threshold; 98 unsigned long tx_pkt_n; 99 unsigned long rx_pkt_n; 100 unsigned long normal_irq_n; 101 unsigned long rx_normal_irq_n; 102 unsigned long napi_poll; 103 unsigned long tx_normal_irq_n; 104 unsigned long tx_clean; 105 unsigned long tx_set_ic_bit; 106 unsigned long irq_receive_pmt_irq_n; 107 /* MMC info */ 108 unsigned long mmc_tx_irq_n; 109 unsigned long mmc_rx_irq_n; 110 unsigned long mmc_rx_csum_offload_irq_n; 111 /* EEE */ 112 unsigned long irq_tx_path_in_lpi_mode_n; 113 unsigned long irq_tx_path_exit_lpi_mode_n; 114 unsigned long irq_rx_path_in_lpi_mode_n; 115 unsigned long irq_rx_path_exit_lpi_mode_n; 116 unsigned long phy_eee_wakeup_error_n; 117 /* Extended RDES status */ 118 unsigned long ip_hdr_err; 119 unsigned long ip_payload_err; 120 unsigned long ip_csum_bypassed; 121 unsigned long ipv4_pkt_rcvd; 122 unsigned long ipv6_pkt_rcvd; 123 unsigned long no_ptp_rx_msg_type_ext; 124 unsigned long ptp_rx_msg_type_sync; 125 unsigned long ptp_rx_msg_type_follow_up; 126 unsigned long ptp_rx_msg_type_delay_req; 127 unsigned long ptp_rx_msg_type_delay_resp; 128 unsigned long ptp_rx_msg_type_pdelay_req; 129 unsigned long ptp_rx_msg_type_pdelay_resp; 130 unsigned long ptp_rx_msg_type_pdelay_follow_up; 131 unsigned long ptp_rx_msg_type_announce; 132 unsigned long ptp_rx_msg_type_management; 133 unsigned long ptp_rx_msg_pkt_reserved_type; 134 unsigned long ptp_frame_type; 135 unsigned long ptp_ver; 136 unsigned long timestamp_dropped; 137 unsigned long av_pkt_rcvd; 138 unsigned long av_tagged_pkt_rcvd; 139 unsigned long vlan_tag_priority_val; 140 unsigned long l3_filter_match; 141 unsigned long l4_filter_match; 142 unsigned long l3_l4_filter_no_match; 143 /* PCS */ 144 unsigned long irq_pcs_ane_n; 145 unsigned long irq_pcs_link_n; 146 unsigned long irq_rgmii_n; 147 unsigned long pcs_link; 148 unsigned long pcs_duplex; 149 unsigned long pcs_speed; 150 /* debug register */ 151 unsigned long mtl_tx_status_fifo_full; 152 unsigned long mtl_tx_fifo_not_empty; 153 unsigned long mmtl_fifo_ctrl; 154 unsigned long mtl_tx_fifo_read_ctrl_write; 155 unsigned long mtl_tx_fifo_read_ctrl_wait; 156 unsigned long mtl_tx_fifo_read_ctrl_read; 157 unsigned long mtl_tx_fifo_read_ctrl_idle; 158 unsigned long mac_tx_in_pause; 159 unsigned long mac_tx_frame_ctrl_xfer; 160 unsigned long mac_tx_frame_ctrl_idle; 161 unsigned long mac_tx_frame_ctrl_wait; 162 unsigned long mac_tx_frame_ctrl_pause; 163 unsigned long mac_gmii_tx_proto_engine; 164 unsigned long mtl_rx_fifo_fill_level_full; 165 unsigned long mtl_rx_fifo_fill_above_thresh; 166 unsigned long mtl_rx_fifo_fill_below_thresh; 167 unsigned long mtl_rx_fifo_fill_level_empty; 168 unsigned long mtl_rx_fifo_read_ctrl_flush; 169 unsigned long mtl_rx_fifo_read_ctrl_read_data; 170 unsigned long mtl_rx_fifo_read_ctrl_status; 171 unsigned long mtl_rx_fifo_read_ctrl_idle; 172 unsigned long mtl_rx_fifo_ctrl_active; 173 unsigned long mac_rx_frame_ctrl_fifo; 174 unsigned long mac_gmii_rx_proto_engine; 175 /* TSO */ 176 unsigned long tx_tso_frames; 177 unsigned long tx_tso_nfrags; 178 }; 179 180 /* Safety Feature statistics exposed by ethtool */ 181 struct stmmac_safety_stats { 182 unsigned long mac_errors[32]; 183 unsigned long mtl_errors[32]; 184 unsigned long dma_errors[32]; 185 }; 186 187 /* Number of fields in Safety Stats */ 188 #define STMMAC_SAFETY_FEAT_SIZE \ 189 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long)) 190 191 /* CSR Frequency Access Defines*/ 192 #define CSR_F_35M 35000000 193 #define CSR_F_60M 60000000 194 #define CSR_F_100M 100000000 195 #define CSR_F_150M 150000000 196 #define CSR_F_250M 250000000 197 #define CSR_F_300M 300000000 198 199 #define MAC_CSR_H_FRQ_MASK 0x20 200 201 #define HASH_TABLE_SIZE 64 202 #define PAUSE_TIME 0xffff 203 204 /* Flow Control defines */ 205 #define FLOW_OFF 0 206 #define FLOW_RX 1 207 #define FLOW_TX 2 208 #define FLOW_AUTO (FLOW_TX | FLOW_RX) 209 210 /* PCS defines */ 211 #define STMMAC_PCS_RGMII (1 << 0) 212 #define STMMAC_PCS_SGMII (1 << 1) 213 #define STMMAC_PCS_TBI (1 << 2) 214 #define STMMAC_PCS_RTBI (1 << 3) 215 216 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */ 217 218 /* DAM HW feature register fields */ 219 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */ 220 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */ 221 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */ 222 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */ 223 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */ 224 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */ 225 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */ 226 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */ 227 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */ 228 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */ 229 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */ 230 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */ 231 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */ 232 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */ 233 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */ 234 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */ 235 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */ 236 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */ 237 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */ 238 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */ 239 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */ 240 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */ 241 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */ 242 /* Timestamping with Internal System Time */ 243 #define DMA_HW_FEAT_INTTSEN 0x02000000 244 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */ 245 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */ 246 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */ 247 #define DEFAULT_DMA_PBL 8 248 249 /* PCS status and mask defines */ 250 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */ 251 #define PCS_LINK_IRQ BIT(1) /* PCS Link */ 252 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */ 253 254 /* Max/Min RI Watchdog Timer count value */ 255 #define MAX_DMA_RIWT 0xff 256 #define MIN_DMA_RIWT 0x10 257 #define DEF_DMA_RIWT 0xa0 258 /* Tx coalesce parameters */ 259 #define STMMAC_COAL_TX_TIMER 1000 260 #define STMMAC_MAX_COAL_TX_TICK 100000 261 #define STMMAC_TX_MAX_FRAMES 256 262 #define STMMAC_TX_FRAMES 25 263 #define STMMAC_RX_FRAMES 0 264 265 /* Packets types */ 266 enum packets_types { 267 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */ 268 PACKET_PTPQ = 0x2, /* PTP Packets */ 269 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */ 270 PACKET_UPQ = 0x4, /* Untagged Packets */ 271 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */ 272 }; 273 274 /* Rx IPC status */ 275 enum rx_frame_status { 276 good_frame = 0x0, 277 discard_frame = 0x1, 278 csum_none = 0x2, 279 llc_snap = 0x4, 280 dma_own = 0x8, 281 rx_not_ls = 0x10, 282 }; 283 284 /* Tx status */ 285 enum tx_frame_status { 286 tx_done = 0x0, 287 tx_not_ls = 0x1, 288 tx_err = 0x2, 289 tx_dma_own = 0x4, 290 }; 291 292 enum dma_irq_status { 293 tx_hard_error = 0x1, 294 tx_hard_error_bump_tc = 0x2, 295 handle_rx = 0x4, 296 handle_tx = 0x8, 297 }; 298 299 /* EEE and LPI defines */ 300 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0) 301 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1) 302 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2) 303 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3) 304 305 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8) 306 307 /* Physical Coding Sublayer */ 308 struct rgmii_adv { 309 unsigned int pause; 310 unsigned int duplex; 311 unsigned int lp_pause; 312 unsigned int lp_duplex; 313 }; 314 315 #define STMMAC_PCS_PAUSE 1 316 #define STMMAC_PCS_ASYM_PAUSE 2 317 318 /* DMA HW capabilities */ 319 struct dma_features { 320 unsigned int mbps_10_100; 321 unsigned int mbps_1000; 322 unsigned int half_duplex; 323 unsigned int hash_filter; 324 unsigned int multi_addr; 325 unsigned int pcs; 326 unsigned int sma_mdio; 327 unsigned int pmt_remote_wake_up; 328 unsigned int pmt_magic_frame; 329 unsigned int rmon; 330 /* IEEE 1588-2002 */ 331 unsigned int time_stamp; 332 /* IEEE 1588-2008 */ 333 unsigned int atime_stamp; 334 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 335 unsigned int eee; 336 unsigned int av; 337 unsigned int hash_tb_sz; 338 unsigned int tsoen; 339 /* TX and RX csum */ 340 unsigned int tx_coe; 341 unsigned int rx_coe; 342 unsigned int rx_coe_type1; 343 unsigned int rx_coe_type2; 344 unsigned int rxfifo_over_2048; 345 /* TX and RX number of channels */ 346 unsigned int number_rx_channel; 347 unsigned int number_tx_channel; 348 /* TX and RX number of queues */ 349 unsigned int number_rx_queues; 350 unsigned int number_tx_queues; 351 /* PPS output */ 352 unsigned int pps_out_num; 353 /* Alternate (enhanced) DESC mode */ 354 unsigned int enh_desc; 355 /* TX and RX FIFO sizes */ 356 unsigned int tx_fifo_size; 357 unsigned int rx_fifo_size; 358 /* Automotive Safety Package */ 359 unsigned int asp; 360 /* RX Parser */ 361 unsigned int frpsel; 362 unsigned int frpbs; 363 unsigned int frpes; 364 unsigned int addr64; 365 unsigned int rssen; 366 unsigned int vlhash; 367 unsigned int sphen; 368 unsigned int vlins; 369 unsigned int dvlan; 370 unsigned int l3l4fnum; 371 unsigned int arpoffsel; 372 /* TSN Features */ 373 unsigned int estwid; 374 unsigned int estdep; 375 unsigned int estsel; 376 unsigned int fpesel; 377 unsigned int tbssel; 378 }; 379 380 /* RX Buffer size must be multiple of 4/8/16 bytes */ 381 #define BUF_SIZE_16KiB 16368 382 #define BUF_SIZE_8KiB 8188 383 #define BUF_SIZE_4KiB 4096 384 #define BUF_SIZE_2KiB 2048 385 386 /* Power Down and WOL */ 387 #define PMT_NOT_SUPPORTED 0 388 #define PMT_SUPPORTED 1 389 390 /* Common MAC defines */ 391 #define MAC_CTRL_REG 0x00000000 /* MAC Control */ 392 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 393 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 394 395 /* Default LPI timers */ 396 #define STMMAC_DEFAULT_LIT_LS 0x3E8 397 #define STMMAC_DEFAULT_TWT_LS 0x1E 398 399 #define STMMAC_CHAIN_MODE 0x1 400 #define STMMAC_RING_MODE 0x2 401 402 #define JUMBO_LEN 9000 403 404 /* Receive Side Scaling */ 405 #define STMMAC_RSS_HASH_KEY_SIZE 40 406 #define STMMAC_RSS_MAX_TABLE_SIZE 256 407 408 /* VLAN */ 409 #define STMMAC_VLAN_NONE 0x0 410 #define STMMAC_VLAN_REMOVE 0x1 411 #define STMMAC_VLAN_INSERT 0x2 412 #define STMMAC_VLAN_REPLACE 0x3 413 414 extern const struct stmmac_desc_ops enh_desc_ops; 415 extern const struct stmmac_desc_ops ndesc_ops; 416 417 struct mac_device_info; 418 419 extern const struct stmmac_hwtimestamp stmmac_ptp; 420 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops; 421 422 struct mac_link { 423 u32 speed_mask; 424 u32 speed10; 425 u32 speed100; 426 u32 speed1000; 427 u32 speed2500; 428 u32 duplex; 429 struct { 430 u32 speed2500; 431 u32 speed5000; 432 u32 speed10000; 433 } xgmii; 434 struct { 435 u32 speed25000; 436 u32 speed40000; 437 u32 speed50000; 438 u32 speed100000; 439 } xlgmii; 440 }; 441 442 struct mii_regs { 443 unsigned int addr; /* MII Address */ 444 unsigned int data; /* MII Data */ 445 unsigned int addr_shift; /* MII address shift */ 446 unsigned int reg_shift; /* MII reg shift */ 447 unsigned int addr_mask; /* MII address mask */ 448 unsigned int reg_mask; /* MII reg mask */ 449 unsigned int clk_csr_shift; 450 unsigned int clk_csr_mask; 451 }; 452 453 struct mac_device_info { 454 const struct stmmac_ops *mac; 455 const struct stmmac_desc_ops *desc; 456 const struct stmmac_dma_ops *dma; 457 const struct stmmac_mode_ops *mode; 458 const struct stmmac_hwtimestamp *ptp; 459 const struct stmmac_tc_ops *tc; 460 const struct stmmac_mmc_ops *mmc; 461 const struct mdio_xpcs_ops *xpcs; 462 struct mdio_xpcs_args xpcs_args; 463 struct mii_regs mii; /* MII register Addresses */ 464 struct mac_link link; 465 void __iomem *pcsr; /* vpointer to device CSRs */ 466 unsigned int multicast_filter_bins; 467 unsigned int unicast_filter_entries; 468 unsigned int mcast_bits_log2; 469 unsigned int rx_csum; 470 unsigned int pcs; 471 unsigned int pmt; 472 unsigned int ps; 473 unsigned int xlgmac; 474 unsigned int num_vlan; 475 u32 vlan_filter[32]; 476 unsigned int promisc; 477 }; 478 479 struct stmmac_rx_routing { 480 u32 reg_mask; 481 u32 reg_shift; 482 }; 483 484 int dwmac100_setup(struct stmmac_priv *priv); 485 int dwmac1000_setup(struct stmmac_priv *priv); 486 int dwmac4_setup(struct stmmac_priv *priv); 487 int dwxgmac2_setup(struct stmmac_priv *priv); 488 int dwxlgmac2_setup(struct stmmac_priv *priv); 489 490 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 491 unsigned int high, unsigned int low); 492 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 493 unsigned int high, unsigned int low); 494 void stmmac_set_mac(void __iomem *ioaddr, bool enable); 495 496 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 497 unsigned int high, unsigned int low); 498 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 499 unsigned int high, unsigned int low); 500 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable); 501 502 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); 503 504 extern const struct stmmac_mode_ops ring_mode_ops; 505 extern const struct stmmac_mode_ops chain_mode_ops; 506 extern const struct stmmac_desc_ops dwmac4_desc_ops; 507 508 #endif /* __COMMON_H__ */ 509