1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/pci.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_gem.h> 34 #include <drm/drm_gem_vram_helper.h> 35 36 #include "ast_drv.h" 37 38 void ast_set_index_reg_mask(struct ast_private *ast, 39 uint32_t base, uint8_t index, 40 uint8_t mask, uint8_t val) 41 { 42 u8 tmp; 43 ast_io_write8(ast, base, index); 44 tmp = (ast_io_read8(ast, base + 1) & mask) | val; 45 ast_set_index_reg(ast, base, index, tmp); 46 } 47 48 uint8_t ast_get_index_reg(struct ast_private *ast, 49 uint32_t base, uint8_t index) 50 { 51 uint8_t ret; 52 ast_io_write8(ast, base, index); 53 ret = ast_io_read8(ast, base + 1); 54 return ret; 55 } 56 57 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 58 uint32_t base, uint8_t index, uint8_t mask) 59 { 60 uint8_t ret; 61 ast_io_write8(ast, base, index); 62 ret = ast_io_read8(ast, base + 1) & mask; 63 return ret; 64 } 65 66 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) 67 { 68 struct device_node *np = dev->pdev->dev.of_node; 69 struct ast_private *ast = to_ast_private(dev); 70 uint32_t data, jregd0, jregd1; 71 72 /* Defaults */ 73 ast->config_mode = ast_use_defaults; 74 *scu_rev = 0xffffffff; 75 76 /* Check if we have device-tree properties */ 77 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", 78 scu_rev)) { 79 /* We do, disable P2A access */ 80 ast->config_mode = ast_use_dt; 81 drm_info(dev, "Using device-tree for configuration\n"); 82 return; 83 } 84 85 /* Not all families have a P2A bridge */ 86 if (dev->pdev->device != PCI_CHIP_AST2000) 87 return; 88 89 /* 90 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 91 * is disabled. We force using P2A if VGA only mode bit 92 * is set D[7] 93 */ 94 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 95 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 96 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { 97 /* Double check it's actually working */ 98 data = ast_read32(ast, 0xf004); 99 if (data != 0xFFFFFFFF) { 100 /* P2A works, grab silicon revision */ 101 ast->config_mode = ast_use_p2a; 102 103 drm_info(dev, "Using P2A bridge for configuration\n"); 104 105 /* Read SCU7c (silicon revision register) */ 106 ast_write32(ast, 0xf004, 0x1e6e0000); 107 ast_write32(ast, 0xf000, 0x1); 108 *scu_rev = ast_read32(ast, 0x1207c); 109 return; 110 } 111 } 112 113 /* We have a P2A bridge but it's disabled */ 114 drm_info(dev, "P2A bridge disabled, using default configuration\n"); 115 } 116 117 static int ast_detect_chip(struct drm_device *dev, bool *need_post) 118 { 119 struct ast_private *ast = to_ast_private(dev); 120 uint32_t jreg, scu_rev; 121 122 /* 123 * If VGA isn't enabled, we need to enable now or subsequent 124 * access to the scratch registers will fail. We also inform 125 * our caller that it needs to POST the chip 126 * (Assumption: VGA not enabled -> need to POST) 127 */ 128 if (!ast_is_vga_enabled(dev)) { 129 ast_enable_vga(dev); 130 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n"); 131 *need_post = true; 132 } else 133 *need_post = false; 134 135 136 /* Enable extended register access */ 137 ast_open_key(ast); 138 ast_enable_mmio(dev); 139 140 /* Find out whether P2A works or whether to use device-tree */ 141 ast_detect_config_mode(dev, &scu_rev); 142 143 /* Identify chipset */ 144 if (dev->pdev->revision >= 0x40) { 145 ast->chip = AST2500; 146 drm_info(dev, "AST 2500 detected\n"); 147 } else if (dev->pdev->revision >= 0x30) { 148 ast->chip = AST2400; 149 drm_info(dev, "AST 2400 detected\n"); 150 } else if (dev->pdev->revision >= 0x20) { 151 ast->chip = AST2300; 152 drm_info(dev, "AST 2300 detected\n"); 153 } else if (dev->pdev->revision >= 0x10) { 154 switch (scu_rev & 0x0300) { 155 case 0x0200: 156 ast->chip = AST1100; 157 drm_info(dev, "AST 1100 detected\n"); 158 break; 159 case 0x0100: 160 ast->chip = AST2200; 161 drm_info(dev, "AST 2200 detected\n"); 162 break; 163 case 0x0000: 164 ast->chip = AST2150; 165 drm_info(dev, "AST 2150 detected\n"); 166 break; 167 default: 168 ast->chip = AST2100; 169 drm_info(dev, "AST 2100 detected\n"); 170 break; 171 } 172 ast->vga2_clone = false; 173 } else { 174 ast->chip = AST2000; 175 drm_info(dev, "AST 2000 detected\n"); 176 } 177 178 /* Check if we support wide screen */ 179 switch (ast->chip) { 180 case AST2000: 181 ast->support_wide_screen = false; 182 break; 183 default: 184 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 185 if (!(jreg & 0x80)) 186 ast->support_wide_screen = true; 187 else if (jreg & 0x01) 188 ast->support_wide_screen = true; 189 else { 190 ast->support_wide_screen = false; 191 if (ast->chip == AST2300 && 192 (scu_rev & 0x300) == 0x0) /* ast1300 */ 193 ast->support_wide_screen = true; 194 if (ast->chip == AST2400 && 195 (scu_rev & 0x300) == 0x100) /* ast1400 */ 196 ast->support_wide_screen = true; 197 if (ast->chip == AST2500 && 198 scu_rev == 0x100) /* ast2510 */ 199 ast->support_wide_screen = true; 200 } 201 break; 202 } 203 204 /* Check 3rd Tx option (digital output afaik) */ 205 ast->tx_chip_type = AST_TX_NONE; 206 207 /* 208 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 209 * enabled, in that case, assume we have a SIL164 TMDS transmitter 210 * 211 * Don't make that assumption if we the chip wasn't enabled and 212 * is at power-on reset, otherwise we'll incorrectly "detect" a 213 * SIL164 when there is none. 214 */ 215 if (!*need_post) { 216 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); 217 if (jreg & 0x80) 218 ast->tx_chip_type = AST_TX_SIL164; 219 } 220 221 if ((ast->chip == AST2300) || (ast->chip == AST2400)) { 222 /* 223 * On AST2300 and 2400, look the configuration set by the SoC in 224 * the SOC scratch register #1 bits 11:8 (interestingly marked 225 * as "reserved" in the spec) 226 */ 227 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 228 switch (jreg) { 229 case 0x04: 230 ast->tx_chip_type = AST_TX_SIL164; 231 break; 232 case 0x08: 233 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL); 234 if (ast->dp501_fw_addr) { 235 /* backup firmware */ 236 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { 237 kfree(ast->dp501_fw_addr); 238 ast->dp501_fw_addr = NULL; 239 } 240 } 241 /* fallthrough */ 242 case 0x0c: 243 ast->tx_chip_type = AST_TX_DP501; 244 } 245 } 246 247 /* Print stuff for diagnostic purposes */ 248 switch(ast->tx_chip_type) { 249 case AST_TX_SIL164: 250 drm_info(dev, "Using Sil164 TMDS transmitter\n"); 251 break; 252 case AST_TX_DP501: 253 drm_info(dev, "Using DP501 DisplayPort transmitter\n"); 254 break; 255 default: 256 drm_info(dev, "Analog VGA only\n"); 257 } 258 return 0; 259 } 260 261 static int ast_get_dram_info(struct drm_device *dev) 262 { 263 struct device_node *np = dev->pdev->dev.of_node; 264 struct ast_private *ast = to_ast_private(dev); 265 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; 266 uint32_t denum, num, div, ref_pll, dsel; 267 268 switch (ast->config_mode) { 269 case ast_use_dt: 270 /* 271 * If some properties are missing, use reasonable 272 * defaults for AST2400 273 */ 274 if (of_property_read_u32(np, "aspeed,mcr-configuration", 275 &mcr_cfg)) 276 mcr_cfg = 0x00000577; 277 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", 278 &mcr_scu_mpll)) 279 mcr_scu_mpll = 0x000050C0; 280 if (of_property_read_u32(np, "aspeed,mcr-scu-strap", 281 &mcr_scu_strap)) 282 mcr_scu_strap = 0; 283 break; 284 case ast_use_p2a: 285 ast_write32(ast, 0xf004, 0x1e6e0000); 286 ast_write32(ast, 0xf000, 0x1); 287 mcr_cfg = ast_read32(ast, 0x10004); 288 mcr_scu_mpll = ast_read32(ast, 0x10120); 289 mcr_scu_strap = ast_read32(ast, 0x10170); 290 break; 291 case ast_use_defaults: 292 default: 293 ast->dram_bus_width = 16; 294 ast->dram_type = AST_DRAM_1Gx16; 295 if (ast->chip == AST2500) 296 ast->mclk = 800; 297 else 298 ast->mclk = 396; 299 return 0; 300 } 301 302 if (mcr_cfg & 0x40) 303 ast->dram_bus_width = 16; 304 else 305 ast->dram_bus_width = 32; 306 307 if (ast->chip == AST2500) { 308 switch (mcr_cfg & 0x03) { 309 case 0: 310 ast->dram_type = AST_DRAM_1Gx16; 311 break; 312 default: 313 case 1: 314 ast->dram_type = AST_DRAM_2Gx16; 315 break; 316 case 2: 317 ast->dram_type = AST_DRAM_4Gx16; 318 break; 319 case 3: 320 ast->dram_type = AST_DRAM_8Gx16; 321 break; 322 } 323 } else if (ast->chip == AST2300 || ast->chip == AST2400) { 324 switch (mcr_cfg & 0x03) { 325 case 0: 326 ast->dram_type = AST_DRAM_512Mx16; 327 break; 328 default: 329 case 1: 330 ast->dram_type = AST_DRAM_1Gx16; 331 break; 332 case 2: 333 ast->dram_type = AST_DRAM_2Gx16; 334 break; 335 case 3: 336 ast->dram_type = AST_DRAM_4Gx16; 337 break; 338 } 339 } else { 340 switch (mcr_cfg & 0x0c) { 341 case 0: 342 case 4: 343 ast->dram_type = AST_DRAM_512Mx16; 344 break; 345 case 8: 346 if (mcr_cfg & 0x40) 347 ast->dram_type = AST_DRAM_1Gx16; 348 else 349 ast->dram_type = AST_DRAM_512Mx32; 350 break; 351 case 0xc: 352 ast->dram_type = AST_DRAM_1Gx32; 353 break; 354 } 355 } 356 357 if (mcr_scu_strap & 0x2000) 358 ref_pll = 14318; 359 else 360 ref_pll = 12000; 361 362 denum = mcr_scu_mpll & 0x1f; 363 num = (mcr_scu_mpll & 0x3fe0) >> 5; 364 dsel = (mcr_scu_mpll & 0xc000) >> 14; 365 switch (dsel) { 366 case 3: 367 div = 0x4; 368 break; 369 case 2: 370 case 1: 371 div = 0x2; 372 break; 373 default: 374 div = 0x1; 375 break; 376 } 377 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); 378 return 0; 379 } 380 381 int ast_driver_load(struct drm_device *dev, unsigned long flags) 382 { 383 struct ast_private *ast; 384 bool need_post; 385 int ret = 0; 386 387 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL); 388 if (!ast) 389 return -ENOMEM; 390 391 dev->dev_private = ast; 392 ast->dev = dev; 393 394 ast->regs = pci_iomap(dev->pdev, 1, 0); 395 if (!ast->regs) { 396 ret = -EIO; 397 goto out_free; 398 } 399 400 /* 401 * If we don't have IO space at all, use MMIO now and 402 * assume the chip has MMIO enabled by default (rev 0x20 403 * and higher). 404 */ 405 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) { 406 drm_info(dev, "platform has no IO space, trying MMIO\n"); 407 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 408 } 409 410 /* "map" IO regs if the above hasn't done so already */ 411 if (!ast->ioregs) { 412 ast->ioregs = pci_iomap(dev->pdev, 2, 0); 413 if (!ast->ioregs) { 414 ret = -EIO; 415 goto out_free; 416 } 417 } 418 419 ast_detect_chip(dev, &need_post); 420 421 ret = ast_get_dram_info(dev); 422 if (ret) 423 goto out_free; 424 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n", 425 ast->mclk, ast->dram_type, ast->dram_bus_width); 426 427 if (need_post) 428 ast_post_gpu(dev); 429 430 ret = ast_mm_init(ast); 431 if (ret) 432 goto out_free; 433 434 ret = ast_mode_config_init(ast); 435 if (ret) 436 goto out_free; 437 438 return 0; 439 out_free: 440 kfree(ast); 441 dev->dev_private = NULL; 442 return ret; 443 } 444 445 void ast_driver_unload(struct drm_device *dev) 446 { 447 struct ast_private *ast = to_ast_private(dev); 448 449 /* enable standard VGA decode */ 450 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); 451 452 ast_release_firmware(dev); 453 kfree(ast->dp501_fw_addr); 454 455 kfree(ast); 456 } 457