1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD20 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "socionext,uniphier-ld20"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 32 cluster1 { 33 core0 { 34 cpu = <&cpu2>; 35 }; 36 core1 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 }; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a72"; 45 reg = <0 0x000>; 46 clocks = <&sys_clk 32>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 #cooling-cells = <2>; 50 }; 51 52 cpu1: cpu@1 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a72"; 55 reg = <0 0x001>; 56 clocks = <&sys_clk 32>; 57 enable-method = "psci"; 58 operating-points-v2 = <&cluster0_opp>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu2: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0 0x100>; 66 clocks = <&sys_clk 33>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cluster1_opp>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu3: cpu@101 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0 0x101>; 76 clocks = <&sys_clk 33>; 77 enable-method = "psci"; 78 operating-points-v2 = <&cluster1_opp>; 79 #cooling-cells = <2>; 80 }; 81 }; 82 83 cluster0_opp: opp-table0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-250000000 { 88 opp-hz = /bits/ 64 <250000000>; 89 clock-latency-ns = <300>; 90 }; 91 opp-275000000 { 92 opp-hz = /bits/ 64 <275000000>; 93 clock-latency-ns = <300>; 94 }; 95 opp-500000000 { 96 opp-hz = /bits/ 64 <500000000>; 97 clock-latency-ns = <300>; 98 }; 99 opp-550000000 { 100 opp-hz = /bits/ 64 <550000000>; 101 clock-latency-ns = <300>; 102 }; 103 opp-666667000 { 104 opp-hz = /bits/ 64 <666667000>; 105 clock-latency-ns = <300>; 106 }; 107 opp-733334000 { 108 opp-hz = /bits/ 64 <733334000>; 109 clock-latency-ns = <300>; 110 }; 111 opp-1000000000 { 112 opp-hz = /bits/ 64 <1000000000>; 113 clock-latency-ns = <300>; 114 }; 115 opp-1100000000 { 116 opp-hz = /bits/ 64 <1100000000>; 117 clock-latency-ns = <300>; 118 }; 119 }; 120 121 cluster1_opp: opp-table1 { 122 compatible = "operating-points-v2"; 123 opp-shared; 124 125 opp-250000000 { 126 opp-hz = /bits/ 64 <250000000>; 127 clock-latency-ns = <300>; 128 }; 129 opp-275000000 { 130 opp-hz = /bits/ 64 <275000000>; 131 clock-latency-ns = <300>; 132 }; 133 opp-500000000 { 134 opp-hz = /bits/ 64 <500000000>; 135 clock-latency-ns = <300>; 136 }; 137 opp-550000000 { 138 opp-hz = /bits/ 64 <550000000>; 139 clock-latency-ns = <300>; 140 }; 141 opp-666667000 { 142 opp-hz = /bits/ 64 <666667000>; 143 clock-latency-ns = <300>; 144 }; 145 opp-733334000 { 146 opp-hz = /bits/ 64 <733334000>; 147 clock-latency-ns = <300>; 148 }; 149 opp-1000000000 { 150 opp-hz = /bits/ 64 <1000000000>; 151 clock-latency-ns = <300>; 152 }; 153 opp-1100000000 { 154 opp-hz = /bits/ 64 <1100000000>; 155 clock-latency-ns = <300>; 156 }; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0"; 161 method = "smc"; 162 }; 163 164 clocks { 165 refclk: ref { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <25000000>; 169 }; 170 }; 171 172 emmc_pwrseq: emmc-pwrseq { 173 compatible = "mmc-pwrseq-emmc"; 174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 175 }; 176 177 timer { 178 compatible = "arm,armv8-timer"; 179 interrupts = <1 13 4>, 180 <1 14 4>, 181 <1 11 4>, 182 <1 10 4>; 183 }; 184 185 thermal-zones { 186 cpu-thermal { 187 polling-delay-passive = <250>; /* 250ms */ 188 polling-delay = <1000>; /* 1000ms */ 189 thermal-sensors = <&pvtctl>; 190 191 trips { 192 cpu_crit: cpu-crit { 193 temperature = <110000>; /* 110C */ 194 hysteresis = <2000>; 195 type = "critical"; 196 }; 197 cpu_alert: cpu-alert { 198 temperature = <100000>; /* 100C */ 199 hysteresis = <2000>; 200 type = "passive"; 201 }; 202 }; 203 204 cooling-maps { 205 map0 { 206 trip = <&cpu_alert>; 207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 }; 212 }; 213 }; 214 }; 215 216 reserved-memory { 217 #address-cells = <2>; 218 #size-cells = <2>; 219 ranges; 220 221 secure-memory@81000000 { 222 reg = <0x0 0x81000000 0x0 0x01000000>; 223 no-map; 224 }; 225 }; 226 227 soc@0 { 228 compatible = "simple-bus"; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 ranges = <0 0 0 0xffffffff>; 232 233 spi0: spi@54006000 { 234 compatible = "socionext,uniphier-scssi"; 235 status = "disabled"; 236 reg = <0x54006000 0x100>; 237 interrupts = <0 39 4>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_spi0>; 240 clocks = <&peri_clk 11>; 241 resets = <&peri_rst 11>; 242 }; 243 244 spi1: spi@54006100 { 245 compatible = "socionext,uniphier-scssi"; 246 status = "disabled"; 247 reg = <0x54006100 0x100>; 248 interrupts = <0 216 4>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_spi1>; 251 clocks = <&peri_clk 11>; 252 resets = <&peri_rst 11>; 253 }; 254 255 spi2: spi@54006200 { 256 compatible = "socionext,uniphier-scssi"; 257 status = "disabled"; 258 reg = <0x54006200 0x100>; 259 interrupts = <0 229 4>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_spi2>; 262 clocks = <&peri_clk 11>; 263 resets = <&peri_rst 11>; 264 }; 265 266 spi3: spi@54006300 { 267 compatible = "socionext,uniphier-scssi"; 268 status = "disabled"; 269 reg = <0x54006300 0x100>; 270 interrupts = <0 230 4>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_spi3>; 273 clocks = <&peri_clk 11>; 274 resets = <&peri_rst 11>; 275 }; 276 277 serial0: serial@54006800 { 278 compatible = "socionext,uniphier-uart"; 279 status = "disabled"; 280 reg = <0x54006800 0x40>; 281 interrupts = <0 33 4>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_uart0>; 284 clocks = <&peri_clk 0>; 285 resets = <&peri_rst 0>; 286 }; 287 288 serial1: serial@54006900 { 289 compatible = "socionext,uniphier-uart"; 290 status = "disabled"; 291 reg = <0x54006900 0x40>; 292 interrupts = <0 35 4>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_uart1>; 295 clocks = <&peri_clk 1>; 296 resets = <&peri_rst 1>; 297 }; 298 299 serial2: serial@54006a00 { 300 compatible = "socionext,uniphier-uart"; 301 status = "disabled"; 302 reg = <0x54006a00 0x40>; 303 interrupts = <0 37 4>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_uart2>; 306 clocks = <&peri_clk 2>; 307 resets = <&peri_rst 2>; 308 }; 309 310 serial3: serial@54006b00 { 311 compatible = "socionext,uniphier-uart"; 312 status = "disabled"; 313 reg = <0x54006b00 0x40>; 314 interrupts = <0 177 4>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_uart3>; 317 clocks = <&peri_clk 3>; 318 resets = <&peri_rst 3>; 319 }; 320 321 gpio: gpio@55000000 { 322 compatible = "socionext,uniphier-gpio"; 323 reg = <0x55000000 0x200>; 324 interrupt-parent = <&aidet>; 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 gpio-controller; 328 #gpio-cells = <2>; 329 gpio-ranges = <&pinctrl 0 0 0>, 330 <&pinctrl 96 0 0>, 331 <&pinctrl 160 0 0>; 332 gpio-ranges-group-names = "gpio_range0", 333 "gpio_range1", 334 "gpio_range2"; 335 ngpios = <205>; 336 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 337 <21 217 3>; 338 }; 339 340 audio@56000000 { 341 compatible = "socionext,uniphier-ld20-aio"; 342 reg = <0x56000000 0x80000>; 343 interrupts = <0 144 4>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_aout1>, 346 <&pinctrl_aoutiec1>; 347 clock-names = "aio"; 348 clocks = <&sys_clk 40>; 349 reset-names = "aio"; 350 resets = <&sys_rst 40>; 351 #sound-dai-cells = <1>; 352 socionext,syscon = <&soc_glue>; 353 354 i2s_port0: port@0 { 355 i2s_hdmi: endpoint { 356 }; 357 }; 358 359 i2s_port1: port@1 { 360 i2s_pcmin2: endpoint { 361 }; 362 }; 363 364 i2s_port2: port@2 { 365 i2s_line: endpoint { 366 dai-format = "i2s"; 367 remote-endpoint = <&evea_line>; 368 }; 369 }; 370 371 i2s_port3: port@3 { 372 i2s_hpcmout1: endpoint { 373 }; 374 }; 375 376 i2s_port4: port@4 { 377 i2s_hp: endpoint { 378 dai-format = "i2s"; 379 remote-endpoint = <&evea_hp>; 380 }; 381 }; 382 383 spdif_port0: port@5 { 384 spdif_hiecout1: endpoint { 385 }; 386 }; 387 388 src_port0: port@6 { 389 i2s_epcmout2: endpoint { 390 }; 391 }; 392 393 src_port1: port@7 { 394 i2s_epcmout3: endpoint { 395 }; 396 }; 397 398 comp_spdif_port0: port@8 { 399 comp_spdif_hiecout1: endpoint { 400 }; 401 }; 402 }; 403 404 codec@57900000 { 405 compatible = "socionext,uniphier-evea"; 406 reg = <0x57900000 0x1000>; 407 clock-names = "evea", "exiv"; 408 clocks = <&sys_clk 41>, <&sys_clk 42>; 409 reset-names = "evea", "exiv", "adamv"; 410 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 411 #sound-dai-cells = <1>; 412 413 port@0 { 414 evea_line: endpoint { 415 remote-endpoint = <&i2s_line>; 416 }; 417 }; 418 419 port@1 { 420 evea_hp: endpoint { 421 remote-endpoint = <&i2s_hp>; 422 }; 423 }; 424 }; 425 426 adamv@57920000 { 427 compatible = "socionext,uniphier-ld20-adamv", 428 "simple-mfd", "syscon"; 429 reg = <0x57920000 0x1000>; 430 431 adamv_rst: reset { 432 compatible = "socionext,uniphier-ld20-adamv-reset"; 433 #reset-cells = <1>; 434 }; 435 }; 436 437 i2c0: i2c@58780000 { 438 compatible = "socionext,uniphier-fi2c"; 439 status = "disabled"; 440 reg = <0x58780000 0x80>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 interrupts = <0 41 4>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_i2c0>; 446 clocks = <&peri_clk 4>; 447 resets = <&peri_rst 4>; 448 clock-frequency = <100000>; 449 }; 450 451 i2c1: i2c@58781000 { 452 compatible = "socionext,uniphier-fi2c"; 453 status = "disabled"; 454 reg = <0x58781000 0x80>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 interrupts = <0 42 4>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pinctrl_i2c1>; 460 clocks = <&peri_clk 5>; 461 resets = <&peri_rst 5>; 462 clock-frequency = <100000>; 463 }; 464 465 i2c2: i2c@58782000 { 466 compatible = "socionext,uniphier-fi2c"; 467 reg = <0x58782000 0x80>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 interrupts = <0 43 4>; 471 clocks = <&peri_clk 6>; 472 resets = <&peri_rst 6>; 473 clock-frequency = <400000>; 474 }; 475 476 i2c3: i2c@58783000 { 477 compatible = "socionext,uniphier-fi2c"; 478 status = "disabled"; 479 reg = <0x58783000 0x80>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 interrupts = <0 44 4>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&pinctrl_i2c3>; 485 clocks = <&peri_clk 7>; 486 resets = <&peri_rst 7>; 487 clock-frequency = <100000>; 488 }; 489 490 i2c4: i2c@58784000 { 491 compatible = "socionext,uniphier-fi2c"; 492 status = "disabled"; 493 reg = <0x58784000 0x80>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 interrupts = <0 45 4>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&pinctrl_i2c4>; 499 clocks = <&peri_clk 8>; 500 resets = <&peri_rst 8>; 501 clock-frequency = <100000>; 502 }; 503 504 i2c5: i2c@58785000 { 505 compatible = "socionext,uniphier-fi2c"; 506 reg = <0x58785000 0x80>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 interrupts = <0 25 4>; 510 clocks = <&peri_clk 9>; 511 resets = <&peri_rst 9>; 512 clock-frequency = <400000>; 513 }; 514 515 system_bus: system-bus@58c00000 { 516 compatible = "socionext,uniphier-system-bus"; 517 status = "disabled"; 518 reg = <0x58c00000 0x400>; 519 #address-cells = <2>; 520 #size-cells = <1>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pinctrl_system_bus>; 523 }; 524 525 smpctrl@59801000 { 526 compatible = "socionext,uniphier-smpctrl"; 527 reg = <0x59801000 0x400>; 528 }; 529 530 sdctrl@59810000 { 531 compatible = "socionext,uniphier-ld20-sdctrl", 532 "simple-mfd", "syscon"; 533 reg = <0x59810000 0x400>; 534 535 sd_clk: clock { 536 compatible = "socionext,uniphier-ld20-sd-clock"; 537 #clock-cells = <1>; 538 }; 539 540 sd_rst: reset { 541 compatible = "socionext,uniphier-ld20-sd-reset"; 542 #reset-cells = <1>; 543 }; 544 }; 545 546 perictrl@59820000 { 547 compatible = "socionext,uniphier-ld20-perictrl", 548 "simple-mfd", "syscon"; 549 reg = <0x59820000 0x200>; 550 551 peri_clk: clock { 552 compatible = "socionext,uniphier-ld20-peri-clock"; 553 #clock-cells = <1>; 554 }; 555 556 peri_rst: reset { 557 compatible = "socionext,uniphier-ld20-peri-reset"; 558 #reset-cells = <1>; 559 }; 560 }; 561 562 emmc: sdhc@5a000000 { 563 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 564 reg = <0x5a000000 0x400>; 565 interrupts = <0 78 4>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_emmc>; 568 clocks = <&sys_clk 4>; 569 resets = <&sys_rst 4>; 570 bus-width = <8>; 571 mmc-ddr-1_8v; 572 mmc-hs200-1_8v; 573 mmc-pwrseq = <&emmc_pwrseq>; 574 cdns,phy-input-delay-legacy = <9>; 575 cdns,phy-input-delay-mmc-highspeed = <2>; 576 cdns,phy-input-delay-mmc-ddr = <3>; 577 cdns,phy-dll-delay-sdclk = <21>; 578 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 579 }; 580 581 sd: sdhc@5a400000 { 582 compatible = "socionext,uniphier-sd-v3.1.1"; 583 status = "disabled"; 584 reg = <0x5a400000 0x800>; 585 interrupts = <0 76 4>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_sd>; 588 clocks = <&sd_clk 0>; 589 reset-names = "host"; 590 resets = <&sd_rst 0>; 591 bus-width = <4>; 592 cap-sd-highspeed; 593 }; 594 595 soc_glue: soc-glue@5f800000 { 596 compatible = "socionext,uniphier-ld20-soc-glue", 597 "simple-mfd", "syscon"; 598 reg = <0x5f800000 0x2000>; 599 600 pinctrl: pinctrl { 601 compatible = "socionext,uniphier-ld20-pinctrl"; 602 }; 603 }; 604 605 soc-glue@5f900000 { 606 compatible = "socionext,uniphier-ld20-soc-glue-debug", 607 "simple-mfd"; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0 0x5f900000 0x2000>; 611 612 efuse@100 { 613 compatible = "socionext,uniphier-efuse"; 614 reg = <0x100 0x28>; 615 }; 616 617 efuse@200 { 618 compatible = "socionext,uniphier-efuse"; 619 reg = <0x200 0x68>; 620 #address-cells = <1>; 621 #size-cells = <1>; 622 623 /* USB cells */ 624 usb_rterm0: trim@54,4 { 625 reg = <0x54 1>; 626 bits = <4 2>; 627 }; 628 usb_rterm1: trim@55,4 { 629 reg = <0x55 1>; 630 bits = <4 2>; 631 }; 632 usb_rterm2: trim@58,4 { 633 reg = <0x58 1>; 634 bits = <4 2>; 635 }; 636 usb_rterm3: trim@59,4 { 637 reg = <0x59 1>; 638 bits = <4 2>; 639 }; 640 usb_sel_t0: trim@54,0 { 641 reg = <0x54 1>; 642 bits = <0 4>; 643 }; 644 usb_sel_t1: trim@55,0 { 645 reg = <0x55 1>; 646 bits = <0 4>; 647 }; 648 usb_sel_t2: trim@58,0 { 649 reg = <0x58 1>; 650 bits = <0 4>; 651 }; 652 usb_sel_t3: trim@59,0 { 653 reg = <0x59 1>; 654 bits = <0 4>; 655 }; 656 usb_hs_i0: trim@56,0 { 657 reg = <0x56 1>; 658 bits = <0 4>; 659 }; 660 usb_hs_i2: trim@5a,0 { 661 reg = <0x5a 1>; 662 bits = <0 4>; 663 }; 664 }; 665 }; 666 667 aidet: aidet@5fc20000 { 668 compatible = "socionext,uniphier-ld20-aidet"; 669 reg = <0x5fc20000 0x200>; 670 interrupt-controller; 671 #interrupt-cells = <2>; 672 }; 673 674 gic: interrupt-controller@5fe00000 { 675 compatible = "arm,gic-v3"; 676 reg = <0x5fe00000 0x10000>, /* GICD */ 677 <0x5fe80000 0x80000>; /* GICR */ 678 interrupt-controller; 679 #interrupt-cells = <3>; 680 interrupts = <1 9 4>; 681 }; 682 683 sysctrl@61840000 { 684 compatible = "socionext,uniphier-ld20-sysctrl", 685 "simple-mfd", "syscon"; 686 reg = <0x61840000 0x10000>; 687 688 sys_clk: clock { 689 compatible = "socionext,uniphier-ld20-clock"; 690 #clock-cells = <1>; 691 }; 692 693 sys_rst: reset { 694 compatible = "socionext,uniphier-ld20-reset"; 695 #reset-cells = <1>; 696 }; 697 698 watchdog { 699 compatible = "socionext,uniphier-wdt"; 700 }; 701 702 pvtctl: pvtctl { 703 compatible = "socionext,uniphier-ld20-thermal"; 704 interrupts = <0 3 4>; 705 #thermal-sensor-cells = <0>; 706 socionext,tmod-calibration = <0x0f22 0x68ee>; 707 }; 708 }; 709 710 eth: ethernet@65000000 { 711 compatible = "socionext,uniphier-ld20-ave4"; 712 status = "disabled"; 713 reg = <0x65000000 0x8500>; 714 interrupts = <0 66 4>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_ether_rgmii>; 717 clock-names = "ether"; 718 clocks = <&sys_clk 6>; 719 reset-names = "ether"; 720 resets = <&sys_rst 6>; 721 phy-mode = "rgmii"; 722 local-mac-address = [00 00 00 00 00 00]; 723 socionext,syscon-phy-mode = <&soc_glue 0>; 724 725 mdio: mdio { 726 #address-cells = <1>; 727 #size-cells = <0>; 728 }; 729 }; 730 731 usb: usb@65a00000 { 732 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 733 status = "disabled"; 734 reg = <0x65a00000 0xcd00>; 735 interrupt-names = "host"; 736 interrupts = <0 134 4>; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 739 <&pinctrl_usb2>, <&pinctrl_usb3>; 740 clock-names = "ref", "bus_early", "suspend"; 741 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; 742 resets = <&usb_rst 15>; 743 phys = <&usb_hsphy0>, <&usb_hsphy1>, 744 <&usb_hsphy2>, <&usb_hsphy3>, 745 <&usb_ssphy0>, <&usb_ssphy1>; 746 dr_mode = "host"; 747 }; 748 749 usb-glue@65b00000 { 750 compatible = "socionext,uniphier-ld20-dwc3-glue", 751 "simple-mfd"; 752 #address-cells = <1>; 753 #size-cells = <1>; 754 ranges = <0 0x65b00000 0x400>; 755 756 usb_rst: reset@0 { 757 compatible = "socionext,uniphier-ld20-usb3-reset"; 758 reg = <0x0 0x4>; 759 #reset-cells = <1>; 760 clock-names = "link"; 761 clocks = <&sys_clk 14>; 762 reset-names = "link"; 763 resets = <&sys_rst 14>; 764 }; 765 766 usb_vbus0: regulator@100 { 767 compatible = "socionext,uniphier-ld20-usb3-regulator"; 768 reg = <0x100 0x10>; 769 clock-names = "link"; 770 clocks = <&sys_clk 14>; 771 reset-names = "link"; 772 resets = <&sys_rst 14>; 773 }; 774 775 usb_vbus1: regulator@110 { 776 compatible = "socionext,uniphier-ld20-usb3-regulator"; 777 reg = <0x110 0x10>; 778 clock-names = "link"; 779 clocks = <&sys_clk 14>; 780 reset-names = "link"; 781 resets = <&sys_rst 14>; 782 }; 783 784 usb_vbus2: regulator@120 { 785 compatible = "socionext,uniphier-ld20-usb3-regulator"; 786 reg = <0x120 0x10>; 787 clock-names = "link"; 788 clocks = <&sys_clk 14>; 789 reset-names = "link"; 790 resets = <&sys_rst 14>; 791 }; 792 793 usb_vbus3: regulator@130 { 794 compatible = "socionext,uniphier-ld20-usb3-regulator"; 795 reg = <0x130 0x10>; 796 clock-names = "link"; 797 clocks = <&sys_clk 14>; 798 reset-names = "link"; 799 resets = <&sys_rst 14>; 800 }; 801 802 usb_hsphy0: hs-phy@200 { 803 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 804 reg = <0x200 0x10>; 805 #phy-cells = <0>; 806 clock-names = "link", "phy"; 807 clocks = <&sys_clk 14>, <&sys_clk 16>; 808 reset-names = "link", "phy"; 809 resets = <&sys_rst 14>, <&sys_rst 16>; 810 vbus-supply = <&usb_vbus0>; 811 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 812 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 813 <&usb_hs_i0>; 814 }; 815 816 usb_hsphy1: hs-phy@210 { 817 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 818 reg = <0x210 0x10>; 819 #phy-cells = <0>; 820 clock-names = "link", "phy"; 821 clocks = <&sys_clk 14>, <&sys_clk 16>; 822 reset-names = "link", "phy"; 823 resets = <&sys_rst 14>, <&sys_rst 16>; 824 vbus-supply = <&usb_vbus1>; 825 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 826 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 827 <&usb_hs_i0>; 828 }; 829 830 usb_hsphy2: hs-phy@220 { 831 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 832 reg = <0x220 0x10>; 833 #phy-cells = <0>; 834 clock-names = "link", "phy"; 835 clocks = <&sys_clk 14>, <&sys_clk 17>; 836 reset-names = "link", "phy"; 837 resets = <&sys_rst 14>, <&sys_rst 17>; 838 vbus-supply = <&usb_vbus2>; 839 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 840 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 841 <&usb_hs_i2>; 842 }; 843 844 usb_hsphy3: hs-phy@230 { 845 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 846 reg = <0x230 0x10>; 847 #phy-cells = <0>; 848 clock-names = "link", "phy"; 849 clocks = <&sys_clk 14>, <&sys_clk 17>; 850 reset-names = "link", "phy"; 851 resets = <&sys_rst 14>, <&sys_rst 17>; 852 vbus-supply = <&usb_vbus3>; 853 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 854 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 855 <&usb_hs_i2>; 856 }; 857 858 usb_ssphy0: ss-phy@300 { 859 compatible = "socionext,uniphier-ld20-usb3-ssphy"; 860 reg = <0x300 0x10>; 861 #phy-cells = <0>; 862 clock-names = "link", "phy"; 863 clocks = <&sys_clk 14>, <&sys_clk 18>; 864 reset-names = "link", "phy"; 865 resets = <&sys_rst 14>, <&sys_rst 18>; 866 vbus-supply = <&usb_vbus0>; 867 }; 868 869 usb_ssphy1: ss-phy@310 { 870 compatible = "socionext,uniphier-ld20-usb3-ssphy"; 871 reg = <0x310 0x10>; 872 #phy-cells = <0>; 873 clock-names = "link", "phy"; 874 clocks = <&sys_clk 14>, <&sys_clk 19>; 875 reset-names = "link", "phy"; 876 resets = <&sys_rst 14>, <&sys_rst 19>; 877 vbus-supply = <&usb_vbus1>; 878 }; 879 }; 880 881 pcie: pcie@66000000 { 882 compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; 883 status = "disabled"; 884 reg-names = "dbi", "link", "config"; 885 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 886 <0x2fff0000 0x10000>; 887 #address-cells = <3>; 888 #size-cells = <2>; 889 clocks = <&sys_clk 24>; 890 resets = <&sys_rst 24>; 891 num-lanes = <1>; 892 num-viewport = <1>; 893 bus-range = <0x0 0xff>; 894 device_type = "pci"; 895 ranges = 896 /* downstream I/O */ 897 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 898 /* non-prefetchable memory */ 899 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 900 #interrupt-cells = <1>; 901 interrupt-names = "dma", "msi"; 902 interrupts = <0 224 4>, <0 225 4>; 903 interrupt-map-mask = <0 0 0 7>; 904 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 905 <0 0 0 2 &pcie_intc 1>, /* INTB */ 906 <0 0 0 3 &pcie_intc 2>, /* INTC */ 907 <0 0 0 4 &pcie_intc 3>; /* INTD */ 908 phy-names = "pcie-phy"; 909 phys = <&pcie_phy>; 910 911 pcie_intc: legacy-interrupt-controller { 912 interrupt-controller; 913 #interrupt-cells = <1>; 914 interrupt-parent = <&gic>; 915 interrupts = <0 226 4>; 916 }; 917 }; 918 919 pcie_phy: phy@66038000 { 920 compatible = "socionext,uniphier-ld20-pcie-phy"; 921 reg = <0x66038000 0x4000>; 922 #phy-cells = <0>; 923 clocks = <&sys_clk 24>; 924 resets = <&sys_rst 24>; 925 socionext,syscon = <&soc_glue>; 926 }; 927 928 nand: nand@68000000 { 929 compatible = "socionext,uniphier-denali-nand-v5b"; 930 status = "disabled"; 931 reg-names = "nand_data", "denali_reg"; 932 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interrupts = <0 65 4>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&pinctrl_nand>; 938 clock-names = "nand", "nand_x", "ecc"; 939 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 940 reset-names = "nand", "reg"; 941 resets = <&sys_rst 2>, <&sys_rst 2>; 942 }; 943 }; 944}; 945 946#include "uniphier-pinctrl.dtsi" 947 948&pinctrl_aout1 { 949 drive-strength = <4>; /* default: 3.5mA */ 950 951 ao1dacck { 952 pins = "AO1DACCK"; 953 drive-strength = <5>; /* 5mA */ 954 }; 955}; 956 957&pinctrl_aoutiec1 { 958 drive-strength = <4>; /* default: 3.5mA */ 959 960 ao1arc { 961 pins = "AO1ARC"; 962 drive-strength = <11>; /* 11mA */ 963 }; 964}; 965