1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers. 4 * 5 * (C) Copyright 2014, 2015 Linaro Ltd. 6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org> 7 * 8 * CPPC describes a few methods for controlling CPU performance using 9 * information from a per CPU table called CPC. This table is described in 10 * the ACPI v5.0+ specification. The table consists of a list of 11 * registers which may be memory mapped or hardware registers and also may 12 * include some static integer values. 13 * 14 * CPU performance is on an abstract continuous scale as against a discretized 15 * P-state scale which is tied to CPU frequency only. In brief, the basic 16 * operation involves: 17 * 18 * - OS makes a CPU performance request. (Can provide min and max bounds) 19 * 20 * - Platform (such as BMC) is free to optimize request within requested bounds 21 * depending on power/thermal budgets etc. 22 * 23 * - Platform conveys its decision back to OS 24 * 25 * The communication between OS and platform occurs through another medium 26 * called (PCC) Platform Communication Channel. This is a generic mailbox like 27 * mechanism which includes doorbell semantics to indicate register updates. 28 * See drivers/mailbox/pcc.c for details on PCC. 29 * 30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and 31 * above specifications. 32 */ 33 34 #define pr_fmt(fmt) "ACPI CPPC: " fmt 35 36 #include <linux/cpufreq.h> 37 #include <linux/delay.h> 38 #include <linux/iopoll.h> 39 #include <linux/ktime.h> 40 #include <linux/rwsem.h> 41 #include <linux/wait.h> 42 43 #include <acpi/cppc_acpi.h> 44 45 struct cppc_pcc_data { 46 struct mbox_chan *pcc_channel; 47 void __iomem *pcc_comm_addr; 48 bool pcc_channel_acquired; 49 unsigned int deadline_us; 50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal; 51 52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */ 53 bool platform_owns_pcc; /* Ownership of PCC subspace */ 54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */ 55 56 /* 57 * Lock to provide controlled access to the PCC channel. 58 * 59 * For performance critical usecases(currently cppc_set_perf) 60 * We need to take read_lock and check if channel belongs to OSPM 61 * before reading or writing to PCC subspace 62 * We need to take write_lock before transferring the channel 63 * ownership to the platform via a Doorbell 64 * This allows us to batch a number of CPPC requests if they happen 65 * to originate in about the same time 66 * 67 * For non-performance critical usecases(init) 68 * Take write_lock for all purposes which gives exclusive access 69 */ 70 struct rw_semaphore pcc_lock; 71 72 /* Wait queue for CPUs whose requests were batched */ 73 wait_queue_head_t pcc_write_wait_q; 74 ktime_t last_cmd_cmpl_time; 75 ktime_t last_mpar_reset; 76 int mpar_count; 77 int refcount; 78 }; 79 80 /* Array to represent the PCC channel per subspace ID */ 81 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES]; 82 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */ 83 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx); 84 85 /* 86 * The cpc_desc structure contains the ACPI register details 87 * as described in the per CPU _CPC tables. The details 88 * include the type of register (e.g. PCC, System IO, FFH etc.) 89 * and destination addresses which lets us READ/WRITE CPU performance 90 * information using the appropriate I/O methods. 91 */ 92 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr); 93 94 /* pcc mapped address + header size + offset within PCC subspace */ 95 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \ 96 0x8 + (offs)) 97 98 /* Check if a CPC register is in PCC */ 99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \ 100 (cpc)->cpc_entry.reg.space_id == \ 101 ACPI_ADR_SPACE_PLATFORM_COMM) 102 103 /* Evalutes to True if reg is a NULL register descriptor */ 104 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ 105 (reg)->address == 0 && \ 106 (reg)->bit_width == 0 && \ 107 (reg)->bit_offset == 0 && \ 108 (reg)->access_width == 0) 109 110 /* Evalutes to True if an optional cpc field is supported */ 111 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \ 112 !!(cpc)->cpc_entry.int_value : \ 113 !IS_NULL_REG(&(cpc)->cpc_entry.reg)) 114 /* 115 * Arbitrary Retries in case the remote processor is slow to respond 116 * to PCC commands. Keeping it high enough to cover emulators where 117 * the processors run painfully slow. 118 */ 119 #define NUM_RETRIES 500ULL 120 121 struct cppc_attr { 122 struct attribute attr; 123 ssize_t (*show)(struct kobject *kobj, 124 struct attribute *attr, char *buf); 125 ssize_t (*store)(struct kobject *kobj, 126 struct attribute *attr, const char *c, ssize_t count); 127 }; 128 129 #define define_one_cppc_ro(_name) \ 130 static struct cppc_attr _name = \ 131 __ATTR(_name, 0444, show_##_name, NULL) 132 133 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) 134 135 #define show_cppc_data(access_fn, struct_name, member_name) \ 136 static ssize_t show_##member_name(struct kobject *kobj, \ 137 struct attribute *attr, char *buf) \ 138 { \ 139 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ 140 struct struct_name st_name = {0}; \ 141 int ret; \ 142 \ 143 ret = access_fn(cpc_ptr->cpu_id, &st_name); \ 144 if (ret) \ 145 return ret; \ 146 \ 147 return scnprintf(buf, PAGE_SIZE, "%llu\n", \ 148 (u64)st_name.member_name); \ 149 } \ 150 define_one_cppc_ro(member_name) 151 152 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); 153 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); 154 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); 155 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); 156 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); 157 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); 158 159 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); 160 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); 161 162 static ssize_t show_feedback_ctrs(struct kobject *kobj, 163 struct attribute *attr, char *buf) 164 { 165 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); 166 struct cppc_perf_fb_ctrs fb_ctrs = {0}; 167 int ret; 168 169 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); 170 if (ret) 171 return ret; 172 173 return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n", 174 fb_ctrs.reference, fb_ctrs.delivered); 175 } 176 define_one_cppc_ro(feedback_ctrs); 177 178 static struct attribute *cppc_attrs[] = { 179 &feedback_ctrs.attr, 180 &reference_perf.attr, 181 &wraparound_time.attr, 182 &highest_perf.attr, 183 &lowest_perf.attr, 184 &lowest_nonlinear_perf.attr, 185 &nominal_perf.attr, 186 &nominal_freq.attr, 187 &lowest_freq.attr, 188 NULL 189 }; 190 191 static struct kobj_type cppc_ktype = { 192 .sysfs_ops = &kobj_sysfs_ops, 193 .default_attrs = cppc_attrs, 194 }; 195 196 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) 197 { 198 int ret, status; 199 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 200 struct acpi_pcct_shared_memory __iomem *generic_comm_base = 201 pcc_ss_data->pcc_comm_addr; 202 203 if (!pcc_ss_data->platform_owns_pcc) 204 return 0; 205 206 /* 207 * Poll PCC status register every 3us(delay_us) for maximum of 208 * deadline_us(timeout_us) until PCC command complete bit is set(cond) 209 */ 210 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status, 211 status & PCC_CMD_COMPLETE_MASK, 3, 212 pcc_ss_data->deadline_us); 213 214 if (likely(!ret)) { 215 pcc_ss_data->platform_owns_pcc = false; 216 if (chk_err_bit && (status & PCC_ERROR_MASK)) 217 ret = -EIO; 218 } 219 220 if (unlikely(ret)) 221 pr_err("PCC check channel failed for ss: %d. ret=%d\n", 222 pcc_ss_id, ret); 223 224 return ret; 225 } 226 227 /* 228 * This function transfers the ownership of the PCC to the platform 229 * So it must be called while holding write_lock(pcc_lock) 230 */ 231 static int send_pcc_cmd(int pcc_ss_id, u16 cmd) 232 { 233 int ret = -EIO, i; 234 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id]; 235 struct acpi_pcct_shared_memory *generic_comm_base = 236 (struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr; 237 unsigned int time_delta; 238 239 /* 240 * For CMD_WRITE we know for a fact the caller should have checked 241 * the channel before writing to PCC space 242 */ 243 if (cmd == CMD_READ) { 244 /* 245 * If there are pending cpc_writes, then we stole the channel 246 * before write completion, so first send a WRITE command to 247 * platform 248 */ 249 if (pcc_ss_data->pending_pcc_write_cmd) 250 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 251 252 ret = check_pcc_chan(pcc_ss_id, false); 253 if (ret) 254 goto end; 255 } else /* CMD_WRITE */ 256 pcc_ss_data->pending_pcc_write_cmd = FALSE; 257 258 /* 259 * Handle the Minimum Request Turnaround Time(MRTT) 260 * "The minimum amount of time that OSPM must wait after the completion 261 * of a command before issuing the next command, in microseconds" 262 */ 263 if (pcc_ss_data->pcc_mrtt) { 264 time_delta = ktime_us_delta(ktime_get(), 265 pcc_ss_data->last_cmd_cmpl_time); 266 if (pcc_ss_data->pcc_mrtt > time_delta) 267 udelay(pcc_ss_data->pcc_mrtt - time_delta); 268 } 269 270 /* 271 * Handle the non-zero Maximum Periodic Access Rate(MPAR) 272 * "The maximum number of periodic requests that the subspace channel can 273 * support, reported in commands per minute. 0 indicates no limitation." 274 * 275 * This parameter should be ideally zero or large enough so that it can 276 * handle maximum number of requests that all the cores in the system can 277 * collectively generate. If it is not, we will follow the spec and just 278 * not send the request to the platform after hitting the MPAR limit in 279 * any 60s window 280 */ 281 if (pcc_ss_data->pcc_mpar) { 282 if (pcc_ss_data->mpar_count == 0) { 283 time_delta = ktime_ms_delta(ktime_get(), 284 pcc_ss_data->last_mpar_reset); 285 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) { 286 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit", 287 pcc_ss_id); 288 ret = -EIO; 289 goto end; 290 } 291 pcc_ss_data->last_mpar_reset = ktime_get(); 292 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar; 293 } 294 pcc_ss_data->mpar_count--; 295 } 296 297 /* Write to the shared comm region. */ 298 writew_relaxed(cmd, &generic_comm_base->command); 299 300 /* Flip CMD COMPLETE bit */ 301 writew_relaxed(0, &generic_comm_base->status); 302 303 pcc_ss_data->platform_owns_pcc = true; 304 305 /* Ring doorbell */ 306 ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd); 307 if (ret < 0) { 308 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n", 309 pcc_ss_id, cmd, ret); 310 goto end; 311 } 312 313 /* wait for completion and check for PCC errro bit */ 314 ret = check_pcc_chan(pcc_ss_id, true); 315 316 if (pcc_ss_data->pcc_mrtt) 317 pcc_ss_data->last_cmd_cmpl_time = ktime_get(); 318 319 if (pcc_ss_data->pcc_channel->mbox->txdone_irq) 320 mbox_chan_txdone(pcc_ss_data->pcc_channel, ret); 321 else 322 mbox_client_txdone(pcc_ss_data->pcc_channel, ret); 323 324 end: 325 if (cmd == CMD_WRITE) { 326 if (unlikely(ret)) { 327 for_each_possible_cpu(i) { 328 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); 329 if (!desc) 330 continue; 331 332 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt) 333 desc->write_cmd_status = ret; 334 } 335 } 336 pcc_ss_data->pcc_write_cnt++; 337 wake_up_all(&pcc_ss_data->pcc_write_wait_q); 338 } 339 340 return ret; 341 } 342 343 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret) 344 { 345 if (ret < 0) 346 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n", 347 *(u16 *)msg, ret); 348 else 349 pr_debug("TX completed. CMD sent:%x, ret:%d\n", 350 *(u16 *)msg, ret); 351 } 352 353 struct mbox_client cppc_mbox_cl = { 354 .tx_done = cppc_chan_tx_done, 355 .knows_txdone = true, 356 }; 357 358 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle) 359 { 360 int result = -EFAULT; 361 acpi_status status = AE_OK; 362 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL}; 363 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"}; 364 struct acpi_buffer state = {0, NULL}; 365 union acpi_object *psd = NULL; 366 struct acpi_psd_package *pdomain; 367 368 status = acpi_evaluate_object_typed(handle, "_PSD", NULL, 369 &buffer, ACPI_TYPE_PACKAGE); 370 if (status == AE_NOT_FOUND) /* _PSD is optional */ 371 return 0; 372 if (ACPI_FAILURE(status)) 373 return -ENODEV; 374 375 psd = buffer.pointer; 376 if (!psd || psd->package.count != 1) { 377 pr_debug("Invalid _PSD data\n"); 378 goto end; 379 } 380 381 pdomain = &(cpc_ptr->domain_info); 382 383 state.length = sizeof(struct acpi_psd_package); 384 state.pointer = pdomain; 385 386 status = acpi_extract_package(&(psd->package.elements[0]), 387 &format, &state); 388 if (ACPI_FAILURE(status)) { 389 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id); 390 goto end; 391 } 392 393 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) { 394 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id); 395 goto end; 396 } 397 398 if (pdomain->revision != ACPI_PSD_REV0_REVISION) { 399 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id); 400 goto end; 401 } 402 403 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL && 404 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY && 405 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) { 406 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id); 407 goto end; 408 } 409 410 result = 0; 411 end: 412 kfree(buffer.pointer); 413 return result; 414 } 415 416 /** 417 * acpi_get_psd_map - Map the CPUs in a common freq domain. 418 * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info. 419 * 420 * Return: 0 for success or negative value for err. 421 */ 422 int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data) 423 { 424 int count_target; 425 int retval = 0; 426 unsigned int i, j; 427 cpumask_var_t covered_cpus; 428 struct cppc_cpudata *pr, *match_pr; 429 struct acpi_psd_package *pdomain; 430 struct acpi_psd_package *match_pdomain; 431 struct cpc_desc *cpc_ptr, *match_cpc_ptr; 432 433 if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)) 434 return -ENOMEM; 435 436 /* 437 * Now that we have _PSD data from all CPUs, let's setup P-state 438 * domain info. 439 */ 440 for_each_possible_cpu(i) { 441 if (cpumask_test_cpu(i, covered_cpus)) 442 continue; 443 444 pr = all_cpu_data[i]; 445 cpc_ptr = per_cpu(cpc_desc_ptr, i); 446 if (!cpc_ptr) { 447 retval = -EFAULT; 448 goto err_ret; 449 } 450 451 pdomain = &(cpc_ptr->domain_info); 452 cpumask_set_cpu(i, pr->shared_cpu_map); 453 cpumask_set_cpu(i, covered_cpus); 454 if (pdomain->num_processors <= 1) 455 continue; 456 457 /* Validate the Domain info */ 458 count_target = pdomain->num_processors; 459 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL) 460 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; 461 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL) 462 pr->shared_type = CPUFREQ_SHARED_TYPE_HW; 463 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY) 464 pr->shared_type = CPUFREQ_SHARED_TYPE_ANY; 465 466 for_each_possible_cpu(j) { 467 if (i == j) 468 continue; 469 470 match_cpc_ptr = per_cpu(cpc_desc_ptr, j); 471 if (!match_cpc_ptr) { 472 retval = -EFAULT; 473 goto err_ret; 474 } 475 476 match_pdomain = &(match_cpc_ptr->domain_info); 477 if (match_pdomain->domain != pdomain->domain) 478 continue; 479 480 /* Here i and j are in the same domain */ 481 if (match_pdomain->num_processors != count_target) { 482 retval = -EFAULT; 483 goto err_ret; 484 } 485 486 if (pdomain->coord_type != match_pdomain->coord_type) { 487 retval = -EFAULT; 488 goto err_ret; 489 } 490 491 cpumask_set_cpu(j, covered_cpus); 492 cpumask_set_cpu(j, pr->shared_cpu_map); 493 } 494 495 for_each_cpu(j, pr->shared_cpu_map) { 496 if (i == j) 497 continue; 498 499 match_pr = all_cpu_data[j]; 500 match_pr->shared_type = pr->shared_type; 501 cpumask_copy(match_pr->shared_cpu_map, 502 pr->shared_cpu_map); 503 } 504 } 505 goto out; 506 507 err_ret: 508 for_each_possible_cpu(i) { 509 pr = all_cpu_data[i]; 510 511 /* Assume no coordination on any error parsing domain info */ 512 cpumask_clear(pr->shared_cpu_map); 513 cpumask_set_cpu(i, pr->shared_cpu_map); 514 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL; 515 } 516 out: 517 free_cpumask_var(covered_cpus); 518 return retval; 519 } 520 EXPORT_SYMBOL_GPL(acpi_get_psd_map); 521 522 static int register_pcc_channel(int pcc_ss_idx) 523 { 524 struct acpi_pcct_hw_reduced *cppc_ss; 525 u64 usecs_lat; 526 527 if (pcc_ss_idx >= 0) { 528 pcc_data[pcc_ss_idx]->pcc_channel = 529 pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx); 530 531 if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) { 532 pr_err("Failed to find PCC channel for subspace %d\n", 533 pcc_ss_idx); 534 return -ENODEV; 535 } 536 537 /* 538 * The PCC mailbox controller driver should 539 * have parsed the PCCT (global table of all 540 * PCC channels) and stored pointers to the 541 * subspace communication region in con_priv. 542 */ 543 cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv; 544 545 if (!cppc_ss) { 546 pr_err("No PCC subspace found for %d CPPC\n", 547 pcc_ss_idx); 548 return -ENODEV; 549 } 550 551 /* 552 * cppc_ss->latency is just a Nominal value. In reality 553 * the remote processor could be much slower to reply. 554 * So add an arbitrary amount of wait on top of Nominal. 555 */ 556 usecs_lat = NUM_RETRIES * cppc_ss->latency; 557 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat; 558 pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time; 559 pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate; 560 pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency; 561 562 pcc_data[pcc_ss_idx]->pcc_comm_addr = 563 acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length); 564 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) { 565 pr_err("Failed to ioremap PCC comm region mem for %d\n", 566 pcc_ss_idx); 567 return -ENOMEM; 568 } 569 570 /* Set flag so that we don't come here for each CPU. */ 571 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true; 572 } 573 574 return 0; 575 } 576 577 /** 578 * cpc_ffh_supported() - check if FFH reading supported 579 * 580 * Check if the architecture has support for functional fixed hardware 581 * read/write capability. 582 * 583 * Return: true for supported, false for not supported 584 */ 585 bool __weak cpc_ffh_supported(void) 586 { 587 return false; 588 } 589 590 /** 591 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace 592 * 593 * Check and allocate the cppc_pcc_data memory. 594 * In some processor configurations it is possible that same subspace 595 * is shared between multiple CPUs. This is seen especially in CPUs 596 * with hardware multi-threading support. 597 * 598 * Return: 0 for success, errno for failure 599 */ 600 int pcc_data_alloc(int pcc_ss_id) 601 { 602 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES) 603 return -EINVAL; 604 605 if (pcc_data[pcc_ss_id]) { 606 pcc_data[pcc_ss_id]->refcount++; 607 } else { 608 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data), 609 GFP_KERNEL); 610 if (!pcc_data[pcc_ss_id]) 611 return -ENOMEM; 612 pcc_data[pcc_ss_id]->refcount++; 613 } 614 615 return 0; 616 } 617 618 /* Check if CPPC revision + num_ent combination is supported */ 619 static bool is_cppc_supported(int revision, int num_ent) 620 { 621 int expected_num_ent; 622 623 switch (revision) { 624 case CPPC_V2_REV: 625 expected_num_ent = CPPC_V2_NUM_ENT; 626 break; 627 case CPPC_V3_REV: 628 expected_num_ent = CPPC_V3_NUM_ENT; 629 break; 630 default: 631 pr_debug("Firmware exports unsupported CPPC revision: %d\n", 632 revision); 633 return false; 634 } 635 636 if (expected_num_ent != num_ent) { 637 pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n", 638 num_ent, expected_num_ent, revision); 639 return false; 640 } 641 642 return true; 643 } 644 645 /* 646 * An example CPC table looks like the following. 647 * 648 * Name(_CPC, Package() 649 * { 650 * 17, 651 * NumEntries 652 * 1, 653 * // Revision 654 * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)}, 655 * // Highest Performance 656 * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)}, 657 * // Nominal Performance 658 * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)}, 659 * // Lowest Nonlinear Performance 660 * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)}, 661 * // Lowest Performance 662 * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)}, 663 * // Guaranteed Performance Register 664 * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)}, 665 * // Desired Performance Register 666 * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)}, 667 * .. 668 * .. 669 * .. 670 * 671 * } 672 * Each Register() encodes how to access that specific register. 673 * e.g. a sample PCC entry has the following encoding: 674 * 675 * Register ( 676 * PCC, 677 * AddressSpaceKeyword 678 * 8, 679 * //RegisterBitWidth 680 * 8, 681 * //RegisterBitOffset 682 * 0x30, 683 * //RegisterAddress 684 * 9 685 * //AccessSize (subspace ID) 686 * 0 687 * ) 688 * } 689 */ 690 691 /** 692 * acpi_cppc_processor_probe - Search for per CPU _CPC objects. 693 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 694 * 695 * Return: 0 for success or negative value for err. 696 */ 697 int acpi_cppc_processor_probe(struct acpi_processor *pr) 698 { 699 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL}; 700 union acpi_object *out_obj, *cpc_obj; 701 struct cpc_desc *cpc_ptr; 702 struct cpc_reg *gas_t; 703 struct device *cpu_dev; 704 acpi_handle handle = pr->handle; 705 unsigned int num_ent, i, cpc_rev; 706 int pcc_subspace_id = -1; 707 acpi_status status; 708 int ret = -EFAULT; 709 710 /* Parse the ACPI _CPC table for this CPU. */ 711 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output, 712 ACPI_TYPE_PACKAGE); 713 if (ACPI_FAILURE(status)) { 714 ret = -ENODEV; 715 goto out_buf_free; 716 } 717 718 out_obj = (union acpi_object *) output.pointer; 719 720 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL); 721 if (!cpc_ptr) { 722 ret = -ENOMEM; 723 goto out_buf_free; 724 } 725 726 /* First entry is NumEntries. */ 727 cpc_obj = &out_obj->package.elements[0]; 728 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 729 num_ent = cpc_obj->integer.value; 730 } else { 731 pr_debug("Unexpected entry type(%d) for NumEntries\n", 732 cpc_obj->type); 733 goto out_free; 734 } 735 cpc_ptr->num_entries = num_ent; 736 737 /* Second entry should be revision. */ 738 cpc_obj = &out_obj->package.elements[1]; 739 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 740 cpc_rev = cpc_obj->integer.value; 741 } else { 742 pr_debug("Unexpected entry type(%d) for Revision\n", 743 cpc_obj->type); 744 goto out_free; 745 } 746 cpc_ptr->version = cpc_rev; 747 748 if (!is_cppc_supported(cpc_rev, num_ent)) 749 goto out_free; 750 751 /* Iterate through remaining entries in _CPC */ 752 for (i = 2; i < num_ent; i++) { 753 cpc_obj = &out_obj->package.elements[i]; 754 755 if (cpc_obj->type == ACPI_TYPE_INTEGER) { 756 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER; 757 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value; 758 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) { 759 gas_t = (struct cpc_reg *) 760 cpc_obj->buffer.pointer; 761 762 /* 763 * The PCC Subspace index is encoded inside 764 * the CPC table entries. The same PCC index 765 * will be used for all the PCC entries, 766 * so extract it only once. 767 */ 768 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { 769 if (pcc_subspace_id < 0) { 770 pcc_subspace_id = gas_t->access_width; 771 if (pcc_data_alloc(pcc_subspace_id)) 772 goto out_free; 773 } else if (pcc_subspace_id != gas_t->access_width) { 774 pr_debug("Mismatched PCC ids.\n"); 775 goto out_free; 776 } 777 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { 778 if (gas_t->address) { 779 void __iomem *addr; 780 781 addr = ioremap(gas_t->address, gas_t->bit_width/8); 782 if (!addr) 783 goto out_free; 784 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; 785 } 786 } else { 787 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) { 788 /* Support only PCC ,SYS MEM and FFH type regs */ 789 pr_debug("Unsupported register type: %d\n", gas_t->space_id); 790 goto out_free; 791 } 792 } 793 794 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER; 795 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); 796 } else { 797 pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id); 798 goto out_free; 799 } 800 } 801 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id; 802 803 /* 804 * Initialize the remaining cpc_regs as unsupported. 805 * Example: In case FW exposes CPPC v2, the below loop will initialize 806 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported 807 */ 808 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) { 809 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER; 810 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0; 811 } 812 813 814 /* Store CPU Logical ID */ 815 cpc_ptr->cpu_id = pr->id; 816 817 /* Parse PSD data for this CPU */ 818 ret = acpi_get_psd(cpc_ptr, handle); 819 if (ret) 820 goto out_free; 821 822 /* Register PCC channel once for all PCC subspace ID. */ 823 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) { 824 ret = register_pcc_channel(pcc_subspace_id); 825 if (ret) 826 goto out_free; 827 828 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock); 829 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q); 830 } 831 832 /* Everything looks okay */ 833 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id); 834 835 /* Add per logical CPU nodes for reading its feedback counters. */ 836 cpu_dev = get_cpu_device(pr->id); 837 if (!cpu_dev) { 838 ret = -EINVAL; 839 goto out_free; 840 } 841 842 /* Plug PSD data into this CPU's CPC descriptor. */ 843 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; 844 845 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, 846 "acpi_cppc"); 847 if (ret) { 848 per_cpu(cpc_desc_ptr, pr->id) = NULL; 849 goto out_free; 850 } 851 852 kfree(output.pointer); 853 return 0; 854 855 out_free: 856 /* Free all the mapped sys mem areas for this CPU */ 857 for (i = 2; i < cpc_ptr->num_entries; i++) { 858 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 859 860 if (addr) 861 iounmap(addr); 862 } 863 kfree(cpc_ptr); 864 865 out_buf_free: 866 kfree(output.pointer); 867 return ret; 868 } 869 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe); 870 871 /** 872 * acpi_cppc_processor_exit - Cleanup CPC structs. 873 * @pr: Ptr to acpi_processor containing this CPU's logical ID. 874 * 875 * Return: Void 876 */ 877 void acpi_cppc_processor_exit(struct acpi_processor *pr) 878 { 879 struct cpc_desc *cpc_ptr; 880 unsigned int i; 881 void __iomem *addr; 882 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); 883 884 if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) { 885 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) { 886 pcc_data[pcc_ss_id]->refcount--; 887 if (!pcc_data[pcc_ss_id]->refcount) { 888 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel); 889 kfree(pcc_data[pcc_ss_id]); 890 pcc_data[pcc_ss_id] = NULL; 891 } 892 } 893 } 894 895 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id); 896 if (!cpc_ptr) 897 return; 898 899 /* Free all the mapped sys mem areas for this CPU */ 900 for (i = 2; i < cpc_ptr->num_entries; i++) { 901 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr; 902 if (addr) 903 iounmap(addr); 904 } 905 906 kobject_put(&cpc_ptr->kobj); 907 kfree(cpc_ptr); 908 } 909 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit); 910 911 /** 912 * cpc_read_ffh() - Read FFH register 913 * @cpunum: CPU number to read 914 * @reg: cppc register information 915 * @val: place holder for return value 916 * 917 * Read bit_width bits from a specified address and bit_offset 918 * 919 * Return: 0 for success and error code 920 */ 921 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) 922 { 923 return -ENOTSUPP; 924 } 925 926 /** 927 * cpc_write_ffh() - Write FFH register 928 * @cpunum: CPU number to write 929 * @reg: cppc register information 930 * @val: value to write 931 * 932 * Write value of bit_width bits to a specified address and bit_offset 933 * 934 * Return: 0 for success and error code 935 */ 936 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) 937 { 938 return -ENOTSUPP; 939 } 940 941 /* 942 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be 943 * as fast as possible. We have already mapped the PCC subspace during init, so 944 * we can directly write to it. 945 */ 946 947 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) 948 { 949 int ret_val = 0; 950 void __iomem *vaddr = 0; 951 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 952 struct cpc_reg *reg = ®_res->cpc_entry.reg; 953 954 if (reg_res->type == ACPI_TYPE_INTEGER) { 955 *val = reg_res->cpc_entry.int_value; 956 return ret_val; 957 } 958 959 *val = 0; 960 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) 961 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 962 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 963 vaddr = reg_res->sys_mem_vaddr; 964 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 965 return cpc_read_ffh(cpu, reg, val); 966 else 967 return acpi_os_read_memory((acpi_physical_address)reg->address, 968 val, reg->bit_width); 969 970 switch (reg->bit_width) { 971 case 8: 972 *val = readb_relaxed(vaddr); 973 break; 974 case 16: 975 *val = readw_relaxed(vaddr); 976 break; 977 case 32: 978 *val = readl_relaxed(vaddr); 979 break; 980 case 64: 981 *val = readq_relaxed(vaddr); 982 break; 983 default: 984 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", 985 reg->bit_width, pcc_ss_id); 986 ret_val = -EFAULT; 987 } 988 989 return ret_val; 990 } 991 992 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) 993 { 994 int ret_val = 0; 995 void __iomem *vaddr = 0; 996 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 997 struct cpc_reg *reg = ®_res->cpc_entry.reg; 998 999 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) 1000 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); 1001 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) 1002 vaddr = reg_res->sys_mem_vaddr; 1003 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) 1004 return cpc_write_ffh(cpu, reg, val); 1005 else 1006 return acpi_os_write_memory((acpi_physical_address)reg->address, 1007 val, reg->bit_width); 1008 1009 switch (reg->bit_width) { 1010 case 8: 1011 writeb_relaxed(val, vaddr); 1012 break; 1013 case 16: 1014 writew_relaxed(val, vaddr); 1015 break; 1016 case 32: 1017 writel_relaxed(val, vaddr); 1018 break; 1019 case 64: 1020 writeq_relaxed(val, vaddr); 1021 break; 1022 default: 1023 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", 1024 reg->bit_width, pcc_ss_id); 1025 ret_val = -EFAULT; 1026 break; 1027 } 1028 1029 return ret_val; 1030 } 1031 1032 /** 1033 * cppc_get_desired_perf - Get the value of desired performance register. 1034 * @cpunum: CPU from which to get desired performance. 1035 * @desired_perf: address of a variable to store the returned desired performance 1036 * 1037 * Return: 0 for success, -EIO otherwise. 1038 */ 1039 int cppc_get_desired_perf(int cpunum, u64 *desired_perf) 1040 { 1041 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1042 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1043 struct cpc_register_resource *desired_reg; 1044 struct cppc_pcc_data *pcc_ss_data = NULL; 1045 1046 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1047 1048 if (CPC_IN_PCC(desired_reg)) { 1049 int ret = 0; 1050 1051 if (pcc_ss_id < 0) 1052 return -EIO; 1053 1054 pcc_ss_data = pcc_data[pcc_ss_id]; 1055 1056 down_write(&pcc_ss_data->pcc_lock); 1057 1058 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) 1059 cpc_read(cpunum, desired_reg, desired_perf); 1060 else 1061 ret = -EIO; 1062 1063 up_write(&pcc_ss_data->pcc_lock); 1064 1065 return ret; 1066 } 1067 1068 cpc_read(cpunum, desired_reg, desired_perf); 1069 1070 return 0; 1071 } 1072 EXPORT_SYMBOL_GPL(cppc_get_desired_perf); 1073 1074 /** 1075 * cppc_get_perf_caps - Get a CPU's performance capabilities. 1076 * @cpunum: CPU from which to get capabilities info. 1077 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h 1078 * 1079 * Return: 0 for success with perf_caps populated else -ERRNO. 1080 */ 1081 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps) 1082 { 1083 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1084 struct cpc_register_resource *highest_reg, *lowest_reg, 1085 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, 1086 *low_freq_reg = NULL, *nom_freq_reg = NULL; 1087 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0; 1088 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1089 struct cppc_pcc_data *pcc_ss_data = NULL; 1090 int ret = 0, regs_in_pcc = 0; 1091 1092 if (!cpc_desc) { 1093 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1094 return -ENODEV; 1095 } 1096 1097 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF]; 1098 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF]; 1099 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF]; 1100 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1101 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ]; 1102 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ]; 1103 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF]; 1104 1105 /* Are any of the regs PCC ?*/ 1106 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || 1107 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || 1108 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { 1109 if (pcc_ss_id < 0) { 1110 pr_debug("Invalid pcc_ss_id\n"); 1111 return -ENODEV; 1112 } 1113 pcc_ss_data = pcc_data[pcc_ss_id]; 1114 regs_in_pcc = 1; 1115 down_write(&pcc_ss_data->pcc_lock); 1116 /* Ring doorbell once to update PCC subspace */ 1117 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1118 ret = -EIO; 1119 goto out_err; 1120 } 1121 } 1122 1123 cpc_read(cpunum, highest_reg, &high); 1124 perf_caps->highest_perf = high; 1125 1126 cpc_read(cpunum, lowest_reg, &low); 1127 perf_caps->lowest_perf = low; 1128 1129 cpc_read(cpunum, nominal_reg, &nom); 1130 perf_caps->nominal_perf = nom; 1131 1132 if (guaranteed_reg->type != ACPI_TYPE_BUFFER || 1133 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { 1134 perf_caps->guaranteed_perf = 0; 1135 } else { 1136 cpc_read(cpunum, guaranteed_reg, &guaranteed); 1137 perf_caps->guaranteed_perf = guaranteed; 1138 } 1139 1140 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear); 1141 perf_caps->lowest_nonlinear_perf = min_nonlinear; 1142 1143 if (!high || !low || !nom || !min_nonlinear) 1144 ret = -EFAULT; 1145 1146 /* Read optional lowest and nominal frequencies if present */ 1147 if (CPC_SUPPORTED(low_freq_reg)) 1148 cpc_read(cpunum, low_freq_reg, &low_f); 1149 1150 if (CPC_SUPPORTED(nom_freq_reg)) 1151 cpc_read(cpunum, nom_freq_reg, &nom_f); 1152 1153 perf_caps->lowest_freq = low_f; 1154 perf_caps->nominal_freq = nom_f; 1155 1156 1157 out_err: 1158 if (regs_in_pcc) 1159 up_write(&pcc_ss_data->pcc_lock); 1160 return ret; 1161 } 1162 EXPORT_SYMBOL_GPL(cppc_get_perf_caps); 1163 1164 /** 1165 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. 1166 * @cpunum: CPU from which to read counters. 1167 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h 1168 * 1169 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. 1170 */ 1171 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) 1172 { 1173 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); 1174 struct cpc_register_resource *delivered_reg, *reference_reg, 1175 *ref_perf_reg, *ctr_wrap_reg; 1176 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); 1177 struct cppc_pcc_data *pcc_ss_data = NULL; 1178 u64 delivered, reference, ref_perf, ctr_wrap_time; 1179 int ret = 0, regs_in_pcc = 0; 1180 1181 if (!cpc_desc) { 1182 pr_debug("No CPC descriptor for CPU:%d\n", cpunum); 1183 return -ENODEV; 1184 } 1185 1186 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR]; 1187 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR]; 1188 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF]; 1189 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME]; 1190 1191 /* 1192 * If reference perf register is not supported then we should 1193 * use the nominal perf value 1194 */ 1195 if (!CPC_SUPPORTED(ref_perf_reg)) 1196 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF]; 1197 1198 /* Are any of the regs PCC ?*/ 1199 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) || 1200 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) { 1201 if (pcc_ss_id < 0) { 1202 pr_debug("Invalid pcc_ss_id\n"); 1203 return -ENODEV; 1204 } 1205 pcc_ss_data = pcc_data[pcc_ss_id]; 1206 down_write(&pcc_ss_data->pcc_lock); 1207 regs_in_pcc = 1; 1208 /* Ring doorbell once to update PCC subspace */ 1209 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { 1210 ret = -EIO; 1211 goto out_err; 1212 } 1213 } 1214 1215 cpc_read(cpunum, delivered_reg, &delivered); 1216 cpc_read(cpunum, reference_reg, &reference); 1217 cpc_read(cpunum, ref_perf_reg, &ref_perf); 1218 1219 /* 1220 * Per spec, if ctr_wrap_time optional register is unsupported, then the 1221 * performance counters are assumed to never wrap during the lifetime of 1222 * platform 1223 */ 1224 ctr_wrap_time = (u64)(~((u64)0)); 1225 if (CPC_SUPPORTED(ctr_wrap_reg)) 1226 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time); 1227 1228 if (!delivered || !reference || !ref_perf) { 1229 ret = -EFAULT; 1230 goto out_err; 1231 } 1232 1233 perf_fb_ctrs->delivered = delivered; 1234 perf_fb_ctrs->reference = reference; 1235 perf_fb_ctrs->reference_perf = ref_perf; 1236 perf_fb_ctrs->wraparound_time = ctr_wrap_time; 1237 out_err: 1238 if (regs_in_pcc) 1239 up_write(&pcc_ss_data->pcc_lock); 1240 return ret; 1241 } 1242 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); 1243 1244 /** 1245 * cppc_set_perf - Set a CPU's performance controls. 1246 * @cpu: CPU for which to set performance controls. 1247 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h 1248 * 1249 * Return: 0 for success, -ERRNO otherwise. 1250 */ 1251 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) 1252 { 1253 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); 1254 struct cpc_register_resource *desired_reg; 1255 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); 1256 struct cppc_pcc_data *pcc_ss_data = NULL; 1257 int ret = 0; 1258 1259 if (!cpc_desc) { 1260 pr_debug("No CPC descriptor for CPU:%d\n", cpu); 1261 return -ENODEV; 1262 } 1263 1264 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1265 1266 /* 1267 * This is Phase-I where we want to write to CPC registers 1268 * -> We want all CPUs to be able to execute this phase in parallel 1269 * 1270 * Since read_lock can be acquired by multiple CPUs simultaneously we 1271 * achieve that goal here 1272 */ 1273 if (CPC_IN_PCC(desired_reg)) { 1274 if (pcc_ss_id < 0) { 1275 pr_debug("Invalid pcc_ss_id\n"); 1276 return -ENODEV; 1277 } 1278 pcc_ss_data = pcc_data[pcc_ss_id]; 1279 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */ 1280 if (pcc_ss_data->platform_owns_pcc) { 1281 ret = check_pcc_chan(pcc_ss_id, false); 1282 if (ret) { 1283 up_read(&pcc_ss_data->pcc_lock); 1284 return ret; 1285 } 1286 } 1287 /* 1288 * Update the pending_write to make sure a PCC CMD_READ will not 1289 * arrive and steal the channel during the switch to write lock 1290 */ 1291 pcc_ss_data->pending_pcc_write_cmd = true; 1292 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt; 1293 cpc_desc->write_cmd_status = 0; 1294 } 1295 1296 /* 1297 * Skip writing MIN/MAX until Linux knows how to come up with 1298 * useful values. 1299 */ 1300 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); 1301 1302 if (CPC_IN_PCC(desired_reg)) 1303 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ 1304 /* 1305 * This is Phase-II where we transfer the ownership of PCC to Platform 1306 * 1307 * Short Summary: Basically if we think of a group of cppc_set_perf 1308 * requests that happened in short overlapping interval. The last CPU to 1309 * come out of Phase-I will enter Phase-II and ring the doorbell. 1310 * 1311 * We have the following requirements for Phase-II: 1312 * 1. We want to execute Phase-II only when there are no CPUs 1313 * currently executing in Phase-I 1314 * 2. Once we start Phase-II we want to avoid all other CPUs from 1315 * entering Phase-I. 1316 * 3. We want only one CPU among all those who went through Phase-I 1317 * to run phase-II 1318 * 1319 * If write_trylock fails to get the lock and doesn't transfer the 1320 * PCC ownership to the platform, then one of the following will be TRUE 1321 * 1. There is at-least one CPU in Phase-I which will later execute 1322 * write_trylock, so the CPUs in Phase-I will be responsible for 1323 * executing the Phase-II. 1324 * 2. Some other CPU has beaten this CPU to successfully execute the 1325 * write_trylock and has already acquired the write_lock. We know for a 1326 * fact it (other CPU acquiring the write_lock) couldn't have happened 1327 * before this CPU's Phase-I as we held the read_lock. 1328 * 3. Some other CPU executing pcc CMD_READ has stolen the 1329 * down_write, in which case, send_pcc_cmd will check for pending 1330 * CMD_WRITE commands by checking the pending_pcc_write_cmd. 1331 * So this CPU can be certain that its request will be delivered 1332 * So in all cases, this CPU knows that its request will be delivered 1333 * by another CPU and can return 1334 * 1335 * After getting the down_write we still need to check for 1336 * pending_pcc_write_cmd to take care of the following scenario 1337 * The thread running this code could be scheduled out between 1338 * Phase-I and Phase-II. Before it is scheduled back on, another CPU 1339 * could have delivered the request to Platform by triggering the 1340 * doorbell and transferred the ownership of PCC to platform. So this 1341 * avoids triggering an unnecessary doorbell and more importantly before 1342 * triggering the doorbell it makes sure that the PCC channel ownership 1343 * is still with OSPM. 1344 * pending_pcc_write_cmd can also be cleared by a different CPU, if 1345 * there was a pcc CMD_READ waiting on down_write and it steals the lock 1346 * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this 1347 * case during a CMD_READ and if there are pending writes it delivers 1348 * the write command before servicing the read command 1349 */ 1350 if (CPC_IN_PCC(desired_reg)) { 1351 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ 1352 /* Update only if there are pending write commands */ 1353 if (pcc_ss_data->pending_pcc_write_cmd) 1354 send_pcc_cmd(pcc_ss_id, CMD_WRITE); 1355 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */ 1356 } else 1357 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */ 1358 wait_event(pcc_ss_data->pcc_write_wait_q, 1359 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt); 1360 1361 /* send_pcc_cmd updates the status in case of failure */ 1362 ret = cpc_desc->write_cmd_status; 1363 } 1364 return ret; 1365 } 1366 EXPORT_SYMBOL_GPL(cppc_set_perf); 1367 1368 /** 1369 * cppc_get_transition_latency - returns frequency transition latency in ns 1370 * 1371 * ACPI CPPC does not explicitly specifiy how a platform can specify the 1372 * transition latency for perfromance change requests. The closest we have 1373 * is the timing information from the PCCT tables which provides the info 1374 * on the number and frequency of PCC commands the platform can handle. 1375 */ 1376 unsigned int cppc_get_transition_latency(int cpu_num) 1377 { 1378 /* 1379 * Expected transition latency is based on the PCCT timing values 1380 * Below are definition from ACPI spec: 1381 * pcc_nominal- Expected latency to process a command, in microseconds 1382 * pcc_mpar - The maximum number of periodic requests that the subspace 1383 * channel can support, reported in commands per minute. 0 1384 * indicates no limitation. 1385 * pcc_mrtt - The minimum amount of time that OSPM must wait after the 1386 * completion of a command before issuing the next command, 1387 * in microseconds. 1388 */ 1389 unsigned int latency_ns = 0; 1390 struct cpc_desc *cpc_desc; 1391 struct cpc_register_resource *desired_reg; 1392 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num); 1393 struct cppc_pcc_data *pcc_ss_data; 1394 1395 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num); 1396 if (!cpc_desc) 1397 return CPUFREQ_ETERNAL; 1398 1399 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; 1400 if (!CPC_IN_PCC(desired_reg)) 1401 return CPUFREQ_ETERNAL; 1402 1403 if (pcc_ss_id < 0) 1404 return CPUFREQ_ETERNAL; 1405 1406 pcc_ss_data = pcc_data[pcc_ss_id]; 1407 if (pcc_ss_data->pcc_mpar) 1408 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar); 1409 1410 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000); 1411 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000); 1412 1413 return latency_ns; 1414 } 1415 EXPORT_SYMBOL_GPL(cppc_get_transition_latency); 1416