1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This program is used to generate definitions needed by 4 * assembly language modules. 5 * 6 * We use the technique used in the OSF Mach kernel code: 7 * generate asm statements containing #defines, 8 * compile this file to assembler, and then extract the 9 * #defines from the assembly-language output. 10 */ 11 12 #define GENERATING_ASM_OFFSETS /* asm/smp.h */ 13 14 #include <linux/compat.h> 15 #include <linux/signal.h> 16 #include <linux/sched.h> 17 #include <linux/kernel.h> 18 #include <linux/errno.h> 19 #include <linux/string.h> 20 #include <linux/types.h> 21 #include <linux/mman.h> 22 #include <linux/mm.h> 23 #include <linux/suspend.h> 24 #include <linux/hrtimer.h> 25 #ifdef CONFIG_PPC64 26 #include <linux/time.h> 27 #include <linux/hardirq.h> 28 #endif 29 #include <linux/kbuild.h> 30 31 #include <asm/io.h> 32 #include <asm/page.h> 33 #include <asm/pgtable.h> 34 #include <asm/processor.h> 35 #include <asm/cputable.h> 36 #include <asm/thread_info.h> 37 #include <asm/rtas.h> 38 #include <asm/vdso_datapage.h> 39 #include <asm/dbell.h> 40 #ifdef CONFIG_PPC64 41 #include <asm/paca.h> 42 #include <asm/lppaca.h> 43 #include <asm/cache.h> 44 #include <asm/mmu.h> 45 #include <asm/hvcall.h> 46 #include <asm/xics.h> 47 #endif 48 #ifdef CONFIG_PPC_POWERNV 49 #include <asm/opal.h> 50 #endif 51 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST) 52 #include <linux/kvm_host.h> 53 #endif 54 #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S) 55 #include <asm/kvm_book3s.h> 56 #include <asm/kvm_ppc.h> 57 #endif 58 59 #ifdef CONFIG_PPC32 60 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 61 #include "head_booke.h" 62 #endif 63 #endif 64 65 #if defined(CONFIG_PPC_FSL_BOOK3E) 66 #include "../mm/mmu_decl.h" 67 #endif 68 69 #ifdef CONFIG_PPC_8xx 70 #include <asm/fixmap.h> 71 #endif 72 73 #define STACK_PT_REGS_OFFSET(sym, val) \ 74 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val)) 75 76 int main(void) 77 { 78 OFFSET(THREAD, task_struct, thread); 79 OFFSET(MM, task_struct, mm); 80 #ifdef CONFIG_STACKPROTECTOR 81 OFFSET(TASK_CANARY, task_struct, stack_canary); 82 #ifdef CONFIG_PPC64 83 OFFSET(PACA_CANARY, paca_struct, canary); 84 #endif 85 #endif 86 OFFSET(MMCONTEXTID, mm_struct, context.id); 87 #ifdef CONFIG_PPC64 88 DEFINE(SIGSEGV, SIGSEGV); 89 DEFINE(NMI_MASK, NMI_MASK); 90 #else 91 OFFSET(KSP_LIMIT, thread_struct, ksp_limit); 92 #ifdef CONFIG_PPC_RTAS 93 OFFSET(RTAS_SP, thread_struct, rtas_sp); 94 #endif 95 #endif /* CONFIG_PPC64 */ 96 OFFSET(TASK_STACK, task_struct, stack); 97 #ifdef CONFIG_SMP 98 OFFSET(TASK_CPU, task_struct, cpu); 99 #endif 100 101 #ifdef CONFIG_LIVEPATCH 102 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp); 103 #endif 104 105 OFFSET(KSP, thread_struct, ksp); 106 OFFSET(PT_REGS, thread_struct, regs); 107 #ifdef CONFIG_BOOKE 108 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]); 109 #endif 110 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode); 111 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr); 112 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area); 113 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr); 114 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp); 115 #ifdef CONFIG_ALTIVEC 116 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr); 117 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area); 118 OFFSET(THREAD_VRSAVE, thread_struct, vrsave); 119 OFFSET(THREAD_USED_VR, thread_struct, used_vr); 120 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr); 121 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec); 122 #endif /* CONFIG_ALTIVEC */ 123 #ifdef CONFIG_VSX 124 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr); 125 #endif /* CONFIG_VSX */ 126 #ifdef CONFIG_PPC64 127 OFFSET(KSP_VSID, thread_struct, ksp_vsid); 128 #else /* CONFIG_PPC64 */ 129 OFFSET(PGDIR, thread_struct, pgdir); 130 #ifdef CONFIG_VMAP_STACK 131 OFFSET(SRR0, thread_struct, srr0); 132 OFFSET(SRR1, thread_struct, srr1); 133 OFFSET(DAR, thread_struct, dar); 134 OFFSET(DSISR, thread_struct, dsisr); 135 #ifdef CONFIG_PPC_BOOK3S_32 136 OFFSET(THR0, thread_struct, r0); 137 OFFSET(THR3, thread_struct, r3); 138 OFFSET(THR4, thread_struct, r4); 139 OFFSET(THR5, thread_struct, r5); 140 OFFSET(THR6, thread_struct, r6); 141 OFFSET(THR8, thread_struct, r8); 142 OFFSET(THR9, thread_struct, r9); 143 OFFSET(THR11, thread_struct, r11); 144 OFFSET(THLR, thread_struct, lr); 145 OFFSET(THCTR, thread_struct, ctr); 146 #endif 147 #endif 148 #ifdef CONFIG_SPE 149 OFFSET(THREAD_EVR0, thread_struct, evr[0]); 150 OFFSET(THREAD_ACC, thread_struct, acc); 151 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr); 152 OFFSET(THREAD_USED_SPE, thread_struct, used_spe); 153 #endif /* CONFIG_SPE */ 154 #endif /* CONFIG_PPC64 */ 155 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 156 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0); 157 #endif 158 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER 159 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu); 160 #endif 161 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 162 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu); 163 #endif 164 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) 165 OFFSET(KUAP, thread_struct, kuap); 166 #endif 167 168 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 169 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch); 170 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar); 171 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr); 172 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar); 173 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar); 174 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr); 175 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr); 176 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs); 177 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr); 178 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave); 179 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr); 180 /* Local pt_regs on stack for Transactional Memory funcs. */ 181 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD + 182 sizeof(struct pt_regs) + 16); 183 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 184 185 OFFSET(TI_FLAGS, thread_info, flags); 186 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags); 187 OFFSET(TI_PREEMPT, thread_info, preempt_count); 188 189 #ifdef CONFIG_PPC64 190 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size); 191 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size); 192 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page); 193 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size); 194 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size); 195 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page); 196 /* paca */ 197 DEFINE(PACA_SIZE, sizeof(struct paca_struct)); 198 OFFSET(PACAPACAINDEX, paca_struct, paca_index); 199 OFFSET(PACAPROCSTART, paca_struct, cpu_start); 200 OFFSET(PACAKSAVE, paca_struct, kstack); 201 OFFSET(PACACURRENT, paca_struct, __current); 202 DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) + 203 offsetof(struct task_struct, thread_info)); 204 OFFSET(PACASAVEDMSR, paca_struct, saved_msr); 205 OFFSET(PACAR1, paca_struct, saved_r1); 206 OFFSET(PACATOC, paca_struct, kernel_toc); 207 OFFSET(PACAKBASE, paca_struct, kernelbase); 208 OFFSET(PACAKMSR, paca_struct, kernel_msr); 209 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask); 210 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened); 211 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled); 212 #ifdef CONFIG_PPC_BOOK3S 213 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id); 214 #ifdef CONFIG_PPC_MM_SLICES 215 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize); 216 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize); 217 OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit); 218 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); 219 #endif /* CONFIG_PPC_MM_SLICES */ 220 #endif 221 222 #ifdef CONFIG_PPC_BOOK3E 223 OFFSET(PACAPGD, paca_struct, pgd); 224 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd); 225 OFFSET(PACA_EXGEN, paca_struct, exgen); 226 OFFSET(PACA_EXTLB, paca_struct, extlb); 227 OFFSET(PACA_EXMC, paca_struct, exmc); 228 OFFSET(PACA_EXCRIT, paca_struct, excrit); 229 OFFSET(PACA_EXDBG, paca_struct, exdbg); 230 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack); 231 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack); 232 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack); 233 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr); 234 235 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next); 236 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max); 237 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first); 238 #endif /* CONFIG_PPC_BOOK3E */ 239 240 #ifdef CONFIG_PPC_BOOK3S_64 241 OFFSET(PACASLBCACHE, paca_struct, slb_cache); 242 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr); 243 OFFSET(PACASTABRR, paca_struct, stab_rr); 244 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp); 245 #ifdef CONFIG_PPC_MM_SLICES 246 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp); 247 #else 248 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp); 249 #endif /* CONFIG_PPC_MM_SLICES */ 250 OFFSET(PACA_EXGEN, paca_struct, exgen); 251 OFFSET(PACA_EXMC, paca_struct, exmc); 252 OFFSET(PACA_EXSLB, paca_struct, exslb); 253 OFFSET(PACA_EXNMI, paca_struct, exnmi); 254 #ifdef CONFIG_PPC_PSERIES 255 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr); 256 #endif 257 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr); 258 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid); 259 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid); 260 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area); 261 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use); 262 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 263 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use); 264 #endif 265 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx); 266 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count); 267 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx); 268 #endif /* CONFIG_PPC_BOOK3S_64 */ 269 OFFSET(PACAEMERGSP, paca_struct, emergency_sp); 270 #ifdef CONFIG_PPC_BOOK3S_64 271 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp); 272 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp); 273 OFFSET(PACA_IN_MCE, paca_struct, in_mce); 274 OFFSET(PACA_IN_NMI, paca_struct, in_nmi); 275 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area); 276 OFFSET(PACA_EXRFI, paca_struct, exrfi); 277 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size); 278 279 #endif 280 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id); 281 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state); 282 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default); 283 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime); 284 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user); 285 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime); 286 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime); 287 #ifdef CONFIG_PPC_BOOK3E 288 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save); 289 #endif 290 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso); 291 #else /* CONFIG_PPC64 */ 292 #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 293 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime); 294 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user); 295 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime); 296 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime); 297 #endif 298 #endif /* CONFIG_PPC64 */ 299 300 /* RTAS */ 301 OFFSET(RTASBASE, rtas_t, base); 302 OFFSET(RTASENTRY, rtas_t, entry); 303 304 /* Interrupt register frame */ 305 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); 306 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); 307 STACK_PT_REGS_OFFSET(GPR0, gpr[0]); 308 STACK_PT_REGS_OFFSET(GPR1, gpr[1]); 309 STACK_PT_REGS_OFFSET(GPR2, gpr[2]); 310 STACK_PT_REGS_OFFSET(GPR3, gpr[3]); 311 STACK_PT_REGS_OFFSET(GPR4, gpr[4]); 312 STACK_PT_REGS_OFFSET(GPR5, gpr[5]); 313 STACK_PT_REGS_OFFSET(GPR6, gpr[6]); 314 STACK_PT_REGS_OFFSET(GPR7, gpr[7]); 315 STACK_PT_REGS_OFFSET(GPR8, gpr[8]); 316 STACK_PT_REGS_OFFSET(GPR9, gpr[9]); 317 STACK_PT_REGS_OFFSET(GPR10, gpr[10]); 318 STACK_PT_REGS_OFFSET(GPR11, gpr[11]); 319 STACK_PT_REGS_OFFSET(GPR12, gpr[12]); 320 STACK_PT_REGS_OFFSET(GPR13, gpr[13]); 321 #ifndef CONFIG_PPC64 322 STACK_PT_REGS_OFFSET(GPR14, gpr[14]); 323 #endif /* CONFIG_PPC64 */ 324 /* 325 * Note: these symbols include _ because they overlap with special 326 * register names 327 */ 328 STACK_PT_REGS_OFFSET(_NIP, nip); 329 STACK_PT_REGS_OFFSET(_MSR, msr); 330 STACK_PT_REGS_OFFSET(_CTR, ctr); 331 STACK_PT_REGS_OFFSET(_LINK, link); 332 STACK_PT_REGS_OFFSET(_CCR, ccr); 333 STACK_PT_REGS_OFFSET(_XER, xer); 334 STACK_PT_REGS_OFFSET(_DAR, dar); 335 STACK_PT_REGS_OFFSET(_DSISR, dsisr); 336 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3); 337 STACK_PT_REGS_OFFSET(RESULT, result); 338 STACK_PT_REGS_OFFSET(_TRAP, trap); 339 #ifndef CONFIG_PPC64 340 /* 341 * The PowerPC 400-class & Book-E processors have neither the DAR 342 * nor the DSISR SPRs. Hence, we overload them to hold the similar 343 * DEAR and ESR SPRs for such processors. For critical interrupts 344 * we use them to hold SRR0 and SRR1. 345 */ 346 STACK_PT_REGS_OFFSET(_DEAR, dar); 347 STACK_PT_REGS_OFFSET(_ESR, dsisr); 348 #else /* CONFIG_PPC64 */ 349 STACK_PT_REGS_OFFSET(SOFTE, softe); 350 STACK_PT_REGS_OFFSET(_PPR, ppr); 351 #endif /* CONFIG_PPC64 */ 352 353 #ifdef CONFIG_PPC_KUAP 354 STACK_PT_REGS_OFFSET(STACK_REGS_KUAP, kuap); 355 #endif 356 357 #if defined(CONFIG_PPC32) 358 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 359 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE); 360 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); 361 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */ 362 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); 363 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1)); 364 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2)); 365 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3)); 366 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6)); 367 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7)); 368 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0)); 369 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1)); 370 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0)); 371 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1)); 372 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0)); 373 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1)); 374 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit)); 375 #endif 376 #endif 377 378 #ifndef CONFIG_PPC64 379 OFFSET(MM_PGD, mm_struct, pgd); 380 #endif /* ! CONFIG_PPC64 */ 381 382 /* About the CPU features table */ 383 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); 384 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); 385 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore); 386 387 OFFSET(pbe_address, pbe, address); 388 OFFSET(pbe_orig_address, pbe, orig_address); 389 OFFSET(pbe_next, pbe, next); 390 391 #ifndef CONFIG_PPC64 392 DEFINE(TASK_SIZE, TASK_SIZE); 393 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); 394 #endif /* ! CONFIG_PPC64 */ 395 396 /* datapage offsets for use by vdso */ 397 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp); 398 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec); 399 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs); 400 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count); 401 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest); 402 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime); 403 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32); 404 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec); 405 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec); 406 OFFSET(STAMP_XTIME_SEC, vdso_data, stamp_xtime_sec); 407 OFFSET(STAMP_XTIME_NSEC, vdso_data, stamp_xtime_nsec); 408 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction); 409 OFFSET(CLOCK_HRTIMER_RES, vdso_data, hrtimer_res); 410 #ifdef CONFIG_PPC64 411 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size); 412 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size); 413 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size); 414 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size); 415 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64); 416 OFFSET(TVAL64_TV_SEC, __kernel_old_timeval, tv_sec); 417 OFFSET(TVAL64_TV_USEC, __kernel_old_timeval, tv_usec); 418 #endif 419 OFFSET(TSPC64_TV_SEC, __kernel_timespec, tv_sec); 420 OFFSET(TSPC64_TV_NSEC, __kernel_timespec, tv_nsec); 421 OFFSET(TVAL32_TV_SEC, old_timeval32, tv_sec); 422 OFFSET(TVAL32_TV_USEC, old_timeval32, tv_usec); 423 OFFSET(TSPC32_TV_SEC, old_timespec32, tv_sec); 424 OFFSET(TSPC32_TV_NSEC, old_timespec32, tv_nsec); 425 /* timeval/timezone offsets for use by vdso */ 426 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest); 427 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime); 428 429 /* Other bits used by the vdso */ 430 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); 431 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); 432 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE); 433 DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE); 434 DEFINE(CLOCK_MAX, CLOCK_TAI); 435 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); 436 DEFINE(EINVAL, EINVAL); 437 DEFINE(KTIME_LOW_RES, KTIME_LOW_RES); 438 439 #ifdef CONFIG_BUG 440 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry)); 441 #endif 442 443 #ifdef CONFIG_PPC_BOOK3S_64 444 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE))); 445 #else 446 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE); 447 #endif 448 DEFINE(PTE_SIZE, sizeof(pte_t)); 449 450 #ifdef CONFIG_KVM 451 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack); 452 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid); 453 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid); 454 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr); 455 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave); 456 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr); 457 #ifdef CONFIG_ALTIVEC 458 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr); 459 #endif 460 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); 461 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); 462 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); 463 #ifdef CONFIG_PPC_BOOK3S 464 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar); 465 #endif 466 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); 467 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); 468 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 469 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr); 470 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0); 471 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1); 472 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0); 473 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1); 474 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2); 475 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3); 476 #endif 477 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING 478 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry); 479 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr); 480 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit); 481 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time); 482 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time); 483 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity); 484 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start); 485 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount); 486 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total); 487 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min); 488 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max); 489 #endif 490 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3); 491 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4); 492 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5); 493 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6); 494 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7); 495 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid); 496 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1); 497 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared); 498 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr); 499 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr); 500 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) 501 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian); 502 #endif 503 504 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0); 505 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1); 506 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2); 507 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3); 508 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4); 509 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6); 510 511 OFFSET(VCPU_KVM, kvm_vcpu, kvm); 512 OFFSET(KVM_LPID, kvm, arch.lpid); 513 514 /* book3s */ 515 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 516 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets); 517 OFFSET(KVM_SDR1, kvm, arch.sdr1); 518 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid); 519 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr); 520 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1); 521 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits); 522 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls); 523 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v); 524 OFFSET(KVM_RADIX, kvm, arch.radix); 525 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled); 526 OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest); 527 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); 528 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar); 529 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr); 530 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty); 531 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst); 532 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested); 533 OFFSET(VCPU_CPU, kvm_vcpu, cpu); 534 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu); 535 #endif 536 #ifdef CONFIG_PPC_BOOK3S 537 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr); 538 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr); 539 OFFSET(VCPU_IC, kvm_vcpu, arch.ic); 540 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr); 541 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr); 542 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor); 543 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr); 544 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl); 545 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr); 546 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx); 547 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr); 548 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx); 549 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr); 550 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags); 551 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec); 552 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires); 553 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions); 554 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded); 555 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded); 556 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending); 557 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request); 558 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr); 559 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc); 560 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc); 561 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar); 562 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar); 563 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier); 564 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb); 565 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max); 566 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr); 567 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr); 568 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar); 569 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa); 570 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr); 571 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); 572 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap); 573 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar); 574 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr); 575 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr); 576 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb); 577 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr); 578 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr); 579 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr); 580 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr); 581 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr); 582 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr); 583 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop); 584 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort); 585 OFFSET(VCPU_TID, kvm_vcpu, arch.tid); 586 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr); 587 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr); 588 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map); 589 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest); 590 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads); 591 OFFSET(VCORE_KVM, kvmppc_vcore, kvm); 592 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset); 593 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied); 594 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr); 595 OFFSET(VCORE_PCR, kvmppc_vcore, pcr); 596 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes); 597 OFFSET(VCORE_VTB, kvmppc_vcore, vtb); 598 OFFSET(VCPU_SLB_E, kvmppc_slb, orige); 599 OFFSET(VCPU_SLB_V, kvmppc_slb, origv); 600 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb)); 601 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 602 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar); 603 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar); 604 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr); 605 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr); 606 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm); 607 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr); 608 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr); 609 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm); 610 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm); 611 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm); 612 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm); 613 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm); 614 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm); 615 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm); 616 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm); 617 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm); 618 #endif 619 620 #ifdef CONFIG_PPC_BOOK3S_64 621 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 622 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu); 623 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f)) 624 #else 625 # define SVCPU_FIELD(x, f) 626 #endif 627 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f)) 628 #else /* 32-bit */ 629 # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f)) 630 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f)) 631 #endif 632 633 SVCPU_FIELD(SVCPU_CR, cr); 634 SVCPU_FIELD(SVCPU_XER, xer); 635 SVCPU_FIELD(SVCPU_CTR, ctr); 636 SVCPU_FIELD(SVCPU_LR, lr); 637 SVCPU_FIELD(SVCPU_PC, pc); 638 SVCPU_FIELD(SVCPU_R0, gpr[0]); 639 SVCPU_FIELD(SVCPU_R1, gpr[1]); 640 SVCPU_FIELD(SVCPU_R2, gpr[2]); 641 SVCPU_FIELD(SVCPU_R3, gpr[3]); 642 SVCPU_FIELD(SVCPU_R4, gpr[4]); 643 SVCPU_FIELD(SVCPU_R5, gpr[5]); 644 SVCPU_FIELD(SVCPU_R6, gpr[6]); 645 SVCPU_FIELD(SVCPU_R7, gpr[7]); 646 SVCPU_FIELD(SVCPU_R8, gpr[8]); 647 SVCPU_FIELD(SVCPU_R9, gpr[9]); 648 SVCPU_FIELD(SVCPU_R10, gpr[10]); 649 SVCPU_FIELD(SVCPU_R11, gpr[11]); 650 SVCPU_FIELD(SVCPU_R12, gpr[12]); 651 SVCPU_FIELD(SVCPU_R13, gpr[13]); 652 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr); 653 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar); 654 SVCPU_FIELD(SVCPU_LAST_INST, last_inst); 655 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1); 656 #ifdef CONFIG_PPC_BOOK3S_32 657 SVCPU_FIELD(SVCPU_SR, sr); 658 #endif 659 #ifdef CONFIG_PPC64 660 SVCPU_FIELD(SVCPU_SLB, slb); 661 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max); 662 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr); 663 #endif 664 665 HSTATE_FIELD(HSTATE_HOST_R1, host_r1); 666 HSTATE_FIELD(HSTATE_HOST_R2, host_r2); 667 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr); 668 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler); 669 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0); 670 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1); 671 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2); 672 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest); 673 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5); 674 HSTATE_FIELD(HSTATE_NAPPING, napping); 675 676 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 677 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req); 678 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state); 679 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu); 680 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore); 681 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys); 682 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys); 683 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt); 684 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr); 685 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi); 686 HSTATE_FIELD(HSTATE_PTID, ptid); 687 HSTATE_FIELD(HSTATE_TID, tid); 688 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend); 689 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]); 690 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]); 691 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]); 692 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]); 693 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]); 694 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]); 695 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]); 696 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]); 697 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]); 698 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]); 699 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]); 700 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]); 701 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]); 702 HSTATE_FIELD(HSTATE_PURR, host_purr); 703 HSTATE_FIELD(HSTATE_SPURR, host_spurr); 704 HSTATE_FIELD(HSTATE_DSCR, host_dscr); 705 HSTATE_FIELD(HSTATE_DABR, dabr); 706 HSTATE_FIELD(HSTATE_DECEXP, dec_expires); 707 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode); 708 DEFINE(IPI_PRIORITY, IPI_PRIORITY); 709 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr); 710 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar); 711 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar); 712 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap); 713 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped); 714 OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set); 715 OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore); 716 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 717 718 #ifdef CONFIG_PPC_BOOK3S_64 719 HSTATE_FIELD(HSTATE_CFAR, cfar); 720 HSTATE_FIELD(HSTATE_PPR, ppr); 721 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr); 722 #endif /* CONFIG_PPC_BOOK3S_64 */ 723 724 #else /* CONFIG_PPC_BOOK3S */ 725 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); 726 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); 727 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); 728 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); 729 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); 730 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9); 731 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); 732 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear); 733 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr); 734 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save); 735 #endif /* CONFIG_PPC_BOOK3S */ 736 #endif /* CONFIG_KVM */ 737 738 #ifdef CONFIG_KVM_GUEST 739 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1); 740 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2); 741 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3); 742 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending); 743 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr); 744 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical); 745 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr); 746 #endif 747 748 #ifdef CONFIG_44x 749 DEFINE(PGD_T_LOG2, PGD_T_LOG2); 750 DEFINE(PTE_T_LOG2, PTE_T_LOG2); 751 #endif 752 #ifdef CONFIG_PPC_FSL_BOOK3E 753 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); 754 OFFSET(TLBCAM_MAS0, tlbcam, MAS0); 755 OFFSET(TLBCAM_MAS1, tlbcam, MAS1); 756 OFFSET(TLBCAM_MAS2, tlbcam, MAS2); 757 OFFSET(TLBCAM_MAS3, tlbcam, MAS3); 758 OFFSET(TLBCAM_MAS7, tlbcam, MAS7); 759 #endif 760 761 #if defined(CONFIG_KVM) && defined(CONFIG_SPE) 762 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]); 763 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc); 764 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr); 765 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr); 766 #endif 767 768 #ifdef CONFIG_KVM_BOOKE_HV 769 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4); 770 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6); 771 #endif 772 773 #ifdef CONFIG_KVM_XICS 774 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu, 775 arch.xive_saved_state)); 776 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu, 777 arch.xive_cam_word)); 778 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed)); 779 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on)); 780 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr)); 781 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr)); 782 #endif 783 784 #ifdef CONFIG_KVM_EXIT_TIMING 785 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu); 786 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl); 787 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu); 788 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl); 789 #endif 790 791 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); 792 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE); 793 794 #ifdef CONFIG_PPC_8xx 795 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE)); 796 #endif 797 798 return 0; 799 } 800