65c1f037 | 05-May-2023 |
Maxime Ripard <maxime@cerno.tech> |
clk: ingenic: tcu: Switch to determine_rate
The Ingenic TCU clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent(
clk: ingenic: tcu: Switch to determine_rate
The Ingenic TCU clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate.
The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent().
The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on.
Cc: Paul Cercueil <paul@crapouillou.net> Cc: linux-mips@vger.kernel.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-60-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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ff0d3ae0 | 31-Oct-2022 |
Siarhei Volkau <lis8215@gmail.com> |
clk: Add Ingenic JZ4755 CGU driver
Add support for the clocks provided by the CGU in the Ingenic JZ4755 SoC.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Link: https://lore.kernel.org/r/202210
clk: Add Ingenic JZ4755 CGU driver
Add support for the clocks provided by the CGU in the Ingenic JZ4755 SoC.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Link: https://lore.kernel.org/r/20221031183930.1338009-2-lis8215@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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8fe873d4 | 26-Oct-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Minor cosmetic fixups for X1000
Remove redundant -1 entries from the parents array and fix a couple indentation / whitespace issues.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0
clk: ingenic: Minor cosmetic fixups for X1000
Remove redundant -1 entries from the parents array and fix a couple indentation / whitespace issues.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20221026194345.243007-7-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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662e8ed7 | 26-Oct-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Add X1000 audio clocks
The X1000's CGU supplies the I2S system clock to the AIC module and ultimately the audio codec, represented by the "i2s" clock. It is a simple mux which can eith
clk: ingenic: Add X1000 audio clocks
The X1000's CGU supplies the I2S system clock to the AIC module and ultimately the audio codec, represented by the "i2s" clock. It is a simple mux which can either pass through EXCLK or a PLL multiplied by a fractional divider (the "i2s_pll" clock).
The AIC contains a separate 1/N divider controlled by the I2S driver, which generates the bit clock from the system clock. The frame clock is always fixed to 1/64th of the bit clock.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20221026194345.243007-6-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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c799a777 | 26-Oct-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock register but before the spinlock is released. This allows another register to be up
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock register but before the spinlock is released. This allows another register to be updated alongside the main one, which is needed to handle the I2S divider on some SoCs.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20221026194345.243007-4-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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d84bf9d6 | 26-Oct-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Make PLL clock enable_bit and stable_bit optional
When the enable bit is undefined, the clock is assumed to be always on and enable/disable is a no-op. When the stable bit is undefined
clk: ingenic: Make PLL clock enable_bit and stable_bit optional
When the enable bit is undefined, the clock is assumed to be always on and enable/disable is a no-op. When the stable bit is undefined, the PLL stable check is a no-op.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20221026194345.243007-3-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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e98839fb | 12-Apr-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs
The TCU clock gate on X1000 wasn't requested by the driver and could be gated automatically later on in boot, which prevents timers from runnin
clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs
The TCU clock gate on X1000 wasn't requested by the driver and could be gated automatically later on in boot, which prevents timers from running and breaks PWM.
Add a workaround to support old device trees that don't specify the "tcu" clock gate. In this case the kernel will print a warning and attempt to continue without the clock, which is wrong, but it could work if "clk_ignore_unused" is in the kernel arguments.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220412122750.279058-3-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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ca54d06f | 28-Apr-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Mark critical clocks in Ingenic SoCs
Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing cal
clk: ingenic: Mark critical clocks in Ingenic SoCs
Consider CPU, L2 cache, and memory clocks as critical to prevent them -- and the parent clocks -- from being automatically gated, since nothing calls clk_get() on these clocks.
Gating the CPU clock hangs the processor, and gating memory makes external DRAM inaccessible. Normal kernel code can't hope to deal with either situation so those clocks have to be critical.
The L2 cache is required only if caches are running, and could be gated if the kernel takes care to flush and disable caches before gating the clock. There's no mechanism to do this, and probably no reason to do it, so it's simpler to mark the L2 cache as critical.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-3-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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bdbfc029 | 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Add support for the JZ4760
Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lo
clk: ingenic: Add support for the JZ4760
Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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b60b0b55 | 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way.
Signed-off-by: Paul Cercueil <p
clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1000-neo/X1000E Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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037f1ffd | 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value.
Signed-off-by: Paul Cercueil <paul@crapouillou.n
clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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315a8423 | 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Read bypass register only when there is one
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality.
Signed-off-by: Paul Cercueil
clk: ingenic: Read bypass register only when there is one
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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1a3c4dd4 | 02-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation s
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation should modify the value pointed to by parent_rate, in order to propagate the rate change to the parent, as explained in the documentation of clk_set_rate().
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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2e4ee634 | 02-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
The custom clocks have custom functions to round, get or set their rate. Therefore, we can't assume that they need the CLK_SET_RATE_PAR
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
The custom clocks have custom functions to round, get or set their rate. Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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