1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "link_encoder.h" 31 #include "stream_encoder.h" 32 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "../virtual/virtual_stream_encoder.h" 36 #include "dce110/dce110_resource.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "irq/dce110/irq_service_dce110.h" 39 #include "dce/dce_link_encoder.h" 40 #include "dce/dce_stream_encoder.h" 41 #include "dce/dce_mem_input.h" 42 #include "dce/dce_ipp.h" 43 #include "dce/dce_transform.h" 44 #include "dce/dce_opp.h" 45 #include "dce/dce_clock_source.h" 46 #include "dce/dce_audio.h" 47 #include "dce/dce_hwseq.h" 48 #include "dce100/dce100_hw_sequencer.h" 49 50 #include "reg_helper.h" 51 52 #include "dce/dce_10_0_d.h" 53 #include "dce/dce_10_0_sh_mask.h" 54 55 #include "dce/dce_dmcu.h" 56 #include "dce/dce_aux.h" 57 #include "dce/dce_abm.h" 58 #include "dce/dce_i2c.h" 59 60 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 61 #include "gmc/gmc_8_2_d.h" 62 #include "gmc/gmc_8_2_sh_mask.h" 63 #endif 64 65 #ifndef mmDP_DPHY_INTERNAL_CTRL 66 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 70 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 71 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 72 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 73 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 74 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 75 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 76 #endif 77 78 #ifndef mmBIOS_SCRATCH_2 79 #define mmBIOS_SCRATCH_2 0x05CB 80 #define mmBIOS_SCRATCH_3 0x05CC 81 #define mmBIOS_SCRATCH_6 0x05CF 82 #endif 83 84 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 85 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 86 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 87 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 88 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 89 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 90 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 91 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 92 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 93 #endif 94 95 #ifndef mmDP_DPHY_FAST_TRAINING 96 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 97 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 98 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 99 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 100 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 101 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 102 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 103 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 104 #endif 105 106 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 107 { 108 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 109 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 110 }, 111 { 112 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 113 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 114 }, 115 { 116 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 117 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 118 }, 119 { 120 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 121 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 122 }, 123 { 124 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 125 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 126 }, 127 { 128 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 129 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 130 } 131 }; 132 133 /* set register offset */ 134 #define SR(reg_name)\ 135 .reg_name = mm ## reg_name 136 137 /* set register offset with instance */ 138 #define SRI(reg_name, block, id)\ 139 .reg_name = mm ## block ## id ## _ ## reg_name 140 141 #define ipp_regs(id)\ 142 [id] = {\ 143 IPP_DCE100_REG_LIST_DCE_BASE(id)\ 144 } 145 146 static const struct dce_ipp_registers ipp_regs[] = { 147 ipp_regs(0), 148 ipp_regs(1), 149 ipp_regs(2), 150 ipp_regs(3), 151 ipp_regs(4), 152 ipp_regs(5) 153 }; 154 155 static const struct dce_ipp_shift ipp_shift = { 156 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 157 }; 158 159 static const struct dce_ipp_mask ipp_mask = { 160 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 161 }; 162 163 #define transform_regs(id)\ 164 [id] = {\ 165 XFM_COMMON_REG_LIST_DCE100(id)\ 166 } 167 168 static const struct dce_transform_registers xfm_regs[] = { 169 transform_regs(0), 170 transform_regs(1), 171 transform_regs(2), 172 transform_regs(3), 173 transform_regs(4), 174 transform_regs(5) 175 }; 176 177 static const struct dce_transform_shift xfm_shift = { 178 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 179 }; 180 181 static const struct dce_transform_mask xfm_mask = { 182 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 183 }; 184 185 #define aux_regs(id)\ 186 [id] = {\ 187 AUX_REG_LIST(id)\ 188 } 189 190 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 191 aux_regs(0), 192 aux_regs(1), 193 aux_regs(2), 194 aux_regs(3), 195 aux_regs(4), 196 aux_regs(5) 197 }; 198 199 #define hpd_regs(id)\ 200 [id] = {\ 201 HPD_REG_LIST(id)\ 202 } 203 204 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 205 hpd_regs(0), 206 hpd_regs(1), 207 hpd_regs(2), 208 hpd_regs(3), 209 hpd_regs(4), 210 hpd_regs(5) 211 }; 212 213 #define link_regs(id)\ 214 [id] = {\ 215 LE_DCE100_REG_LIST(id)\ 216 } 217 218 static const struct dce110_link_enc_registers link_enc_regs[] = { 219 link_regs(0), 220 link_regs(1), 221 link_regs(2), 222 link_regs(3), 223 link_regs(4), 224 link_regs(5), 225 link_regs(6), 226 }; 227 228 #define stream_enc_regs(id)\ 229 [id] = {\ 230 SE_COMMON_REG_LIST_DCE_BASE(id),\ 231 .AFMT_CNTL = 0,\ 232 } 233 234 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 235 stream_enc_regs(0), 236 stream_enc_regs(1), 237 stream_enc_regs(2), 238 stream_enc_regs(3), 239 stream_enc_regs(4), 240 stream_enc_regs(5), 241 stream_enc_regs(6) 242 }; 243 244 static const struct dce_stream_encoder_shift se_shift = { 245 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 246 }; 247 248 static const struct dce_stream_encoder_mask se_mask = { 249 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 250 }; 251 252 #define opp_regs(id)\ 253 [id] = {\ 254 OPP_DCE_100_REG_LIST(id),\ 255 } 256 257 static const struct dce_opp_registers opp_regs[] = { 258 opp_regs(0), 259 opp_regs(1), 260 opp_regs(2), 261 opp_regs(3), 262 opp_regs(4), 263 opp_regs(5) 264 }; 265 266 static const struct dce_opp_shift opp_shift = { 267 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) 268 }; 269 270 static const struct dce_opp_mask opp_mask = { 271 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) 272 }; 273 #define aux_engine_regs(id)\ 274 [id] = {\ 275 AUX_COMMON_REG_LIST(id), \ 276 .AUX_RESET_MASK = 0 \ 277 } 278 279 static const struct dce110_aux_registers aux_engine_regs[] = { 280 aux_engine_regs(0), 281 aux_engine_regs(1), 282 aux_engine_regs(2), 283 aux_engine_regs(3), 284 aux_engine_regs(4), 285 aux_engine_regs(5) 286 }; 287 288 #define audio_regs(id)\ 289 [id] = {\ 290 AUD_COMMON_REG_LIST(id)\ 291 } 292 293 static const struct dce_audio_registers audio_regs[] = { 294 audio_regs(0), 295 audio_regs(1), 296 audio_regs(2), 297 audio_regs(3), 298 audio_regs(4), 299 audio_regs(5), 300 audio_regs(6), 301 }; 302 303 static const struct dce_audio_shift audio_shift = { 304 AUD_COMMON_MASK_SH_LIST(__SHIFT) 305 }; 306 307 static const struct dce_audio_mask audio_mask = { 308 AUD_COMMON_MASK_SH_LIST(_MASK) 309 }; 310 311 #define clk_src_regs(id)\ 312 [id] = {\ 313 CS_COMMON_REG_LIST_DCE_100_110(id),\ 314 } 315 316 static const struct dce110_clk_src_regs clk_src_regs[] = { 317 clk_src_regs(0), 318 clk_src_regs(1), 319 clk_src_regs(2) 320 }; 321 322 static const struct dce110_clk_src_shift cs_shift = { 323 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 324 }; 325 326 static const struct dce110_clk_src_mask cs_mask = { 327 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 328 }; 329 330 static const struct dce_dmcu_registers dmcu_regs = { 331 DMCU_DCE110_COMMON_REG_LIST() 332 }; 333 334 static const struct dce_dmcu_shift dmcu_shift = { 335 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 336 }; 337 338 static const struct dce_dmcu_mask dmcu_mask = { 339 DMCU_MASK_SH_LIST_DCE110(_MASK) 340 }; 341 342 static const struct dce_abm_registers abm_regs = { 343 ABM_DCE110_COMMON_REG_LIST() 344 }; 345 346 static const struct dce_abm_shift abm_shift = { 347 ABM_MASK_SH_LIST_DCE110(__SHIFT) 348 }; 349 350 static const struct dce_abm_mask abm_mask = { 351 ABM_MASK_SH_LIST_DCE110(_MASK) 352 }; 353 354 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 355 356 static const struct bios_registers bios_regs = { 357 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 358 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 359 }; 360 361 static const struct resource_caps res_cap = { 362 .num_timing_generator = 6, 363 .num_audio = 6, 364 .num_stream_encoder = 6, 365 .num_pll = 3, 366 .num_ddc = 6, 367 }; 368 369 static const struct dc_plane_cap plane_cap = { 370 .type = DC_PLANE_TYPE_DCE_RGB, 371 372 .pixel_format_support = { 373 .argb8888 = true, 374 .nv12 = false, 375 .fp16 = false 376 }, 377 378 .max_upscale_factor = { 379 .argb8888 = 16000, 380 .nv12 = 1, 381 .fp16 = 1 382 }, 383 384 .max_downscale_factor = { 385 .argb8888 = 250, 386 .nv12 = 1, 387 .fp16 = 1 388 } 389 }; 390 391 #define CTX ctx 392 #define REG(reg) mm ## reg 393 394 #ifndef mmCC_DC_HDMI_STRAPS 395 #define mmCC_DC_HDMI_STRAPS 0x1918 396 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 397 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 398 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 399 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 400 #endif 401 402 static void read_dce_straps( 403 struct dc_context *ctx, 404 struct resource_straps *straps) 405 { 406 REG_GET_2(CC_DC_HDMI_STRAPS, 407 HDMI_DISABLE, &straps->hdmi_disable, 408 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 409 410 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 411 } 412 413 static struct audio *create_audio( 414 struct dc_context *ctx, unsigned int inst) 415 { 416 return dce_audio_create(ctx, inst, 417 &audio_regs[inst], &audio_shift, &audio_mask); 418 } 419 420 static struct timing_generator *dce100_timing_generator_create( 421 struct dc_context *ctx, 422 uint32_t instance, 423 const struct dce110_timing_generator_offsets *offsets) 424 { 425 struct dce110_timing_generator *tg110 = 426 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 427 428 if (!tg110) 429 return NULL; 430 431 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 432 return &tg110->base; 433 } 434 435 static struct stream_encoder *dce100_stream_encoder_create( 436 enum engine_id eng_id, 437 struct dc_context *ctx) 438 { 439 struct dce110_stream_encoder *enc110 = 440 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 441 442 if (!enc110) 443 return NULL; 444 445 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 446 &stream_enc_regs[eng_id], &se_shift, &se_mask); 447 return &enc110->base; 448 } 449 450 #define SRII(reg_name, block, id)\ 451 .reg_name[id] = mm ## block ## id ## _ ## reg_name 452 453 static const struct dce_hwseq_registers hwseq_reg = { 454 HWSEQ_DCE10_REG_LIST() 455 }; 456 457 static const struct dce_hwseq_shift hwseq_shift = { 458 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) 459 }; 460 461 static const struct dce_hwseq_mask hwseq_mask = { 462 HWSEQ_DCE10_MASK_SH_LIST(_MASK) 463 }; 464 465 static struct dce_hwseq *dce100_hwseq_create( 466 struct dc_context *ctx) 467 { 468 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 469 470 if (hws) { 471 hws->ctx = ctx; 472 hws->regs = &hwseq_reg; 473 hws->shifts = &hwseq_shift; 474 hws->masks = &hwseq_mask; 475 } 476 return hws; 477 } 478 479 static const struct resource_create_funcs res_create_funcs = { 480 .read_dce_straps = read_dce_straps, 481 .create_audio = create_audio, 482 .create_stream_encoder = dce100_stream_encoder_create, 483 .create_hwseq = dce100_hwseq_create, 484 }; 485 486 #define mi_inst_regs(id) { \ 487 MI_DCE8_REG_LIST(id), \ 488 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 489 } 490 static const struct dce_mem_input_registers mi_regs[] = { 491 mi_inst_regs(0), 492 mi_inst_regs(1), 493 mi_inst_regs(2), 494 mi_inst_regs(3), 495 mi_inst_regs(4), 496 mi_inst_regs(5), 497 }; 498 499 static const struct dce_mem_input_shift mi_shifts = { 500 MI_DCE8_MASK_SH_LIST(__SHIFT), 501 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 502 }; 503 504 static const struct dce_mem_input_mask mi_masks = { 505 MI_DCE8_MASK_SH_LIST(_MASK), 506 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 507 }; 508 509 static struct mem_input *dce100_mem_input_create( 510 struct dc_context *ctx, 511 uint32_t inst) 512 { 513 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 514 GFP_KERNEL); 515 516 if (!dce_mi) { 517 BREAK_TO_DEBUGGER(); 518 return NULL; 519 } 520 521 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 522 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 523 return &dce_mi->base; 524 } 525 526 static void dce100_transform_destroy(struct transform **xfm) 527 { 528 kfree(TO_DCE_TRANSFORM(*xfm)); 529 *xfm = NULL; 530 } 531 532 static struct transform *dce100_transform_create( 533 struct dc_context *ctx, 534 uint32_t inst) 535 { 536 struct dce_transform *transform = 537 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 538 539 if (!transform) 540 return NULL; 541 542 dce_transform_construct(transform, ctx, inst, 543 &xfm_regs[inst], &xfm_shift, &xfm_mask); 544 return &transform->base; 545 } 546 547 static struct input_pixel_processor *dce100_ipp_create( 548 struct dc_context *ctx, uint32_t inst) 549 { 550 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 551 552 if (!ipp) { 553 BREAK_TO_DEBUGGER(); 554 return NULL; 555 } 556 557 dce_ipp_construct(ipp, ctx, inst, 558 &ipp_regs[inst], &ipp_shift, &ipp_mask); 559 return &ipp->base; 560 } 561 562 static const struct encoder_feature_support link_enc_feature = { 563 .max_hdmi_deep_color = COLOR_DEPTH_121212, 564 .max_hdmi_pixel_clock = 300000, 565 .flags.bits.IS_HBR2_CAPABLE = true, 566 .flags.bits.IS_TPS3_CAPABLE = true 567 }; 568 569 struct link_encoder *dce100_link_encoder_create( 570 const struct encoder_init_data *enc_init_data) 571 { 572 struct dce110_link_encoder *enc110 = 573 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 574 575 if (!enc110) 576 return NULL; 577 578 dce110_link_encoder_construct(enc110, 579 enc_init_data, 580 &link_enc_feature, 581 &link_enc_regs[enc_init_data->transmitter], 582 &link_enc_aux_regs[enc_init_data->channel - 1], 583 &link_enc_hpd_regs[enc_init_data->hpd_source]); 584 return &enc110->base; 585 } 586 587 struct output_pixel_processor *dce100_opp_create( 588 struct dc_context *ctx, 589 uint32_t inst) 590 { 591 struct dce110_opp *opp = 592 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 593 594 if (!opp) 595 return NULL; 596 597 dce110_opp_construct(opp, 598 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 599 return &opp->base; 600 } 601 602 struct dce_aux *dce100_aux_engine_create( 603 struct dc_context *ctx, 604 uint32_t inst) 605 { 606 struct aux_engine_dce110 *aux_engine = 607 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 608 609 if (!aux_engine) 610 return NULL; 611 612 dce110_aux_engine_construct(aux_engine, ctx, inst, 613 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 614 &aux_engine_regs[inst]); 615 616 return &aux_engine->base; 617 } 618 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 619 620 static const struct dce_i2c_registers i2c_hw_regs[] = { 621 i2c_inst_regs(1), 622 i2c_inst_regs(2), 623 i2c_inst_regs(3), 624 i2c_inst_regs(4), 625 i2c_inst_regs(5), 626 i2c_inst_regs(6), 627 }; 628 629 static const struct dce_i2c_shift i2c_shifts = { 630 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 631 }; 632 633 static const struct dce_i2c_mask i2c_masks = { 634 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 635 }; 636 637 struct dce_i2c_hw *dce100_i2c_hw_create( 638 struct dc_context *ctx, 639 uint32_t inst) 640 { 641 struct dce_i2c_hw *dce_i2c_hw = 642 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 643 644 if (!dce_i2c_hw) 645 return NULL; 646 647 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst, 648 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 649 650 return dce_i2c_hw; 651 } 652 struct clock_source *dce100_clock_source_create( 653 struct dc_context *ctx, 654 struct dc_bios *bios, 655 enum clock_source_id id, 656 const struct dce110_clk_src_regs *regs, 657 bool dp_clk_src) 658 { 659 struct dce110_clk_src *clk_src = 660 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 661 662 if (!clk_src) 663 return NULL; 664 665 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 666 regs, &cs_shift, &cs_mask)) { 667 clk_src->base.dp_clk_src = dp_clk_src; 668 return &clk_src->base; 669 } 670 671 BREAK_TO_DEBUGGER(); 672 return NULL; 673 } 674 675 void dce100_clock_source_destroy(struct clock_source **clk_src) 676 { 677 kfree(TO_DCE110_CLK_SRC(*clk_src)); 678 *clk_src = NULL; 679 } 680 681 static void destruct(struct dce110_resource_pool *pool) 682 { 683 unsigned int i; 684 685 for (i = 0; i < pool->base.pipe_count; i++) { 686 if (pool->base.opps[i] != NULL) 687 dce110_opp_destroy(&pool->base.opps[i]); 688 689 if (pool->base.transforms[i] != NULL) 690 dce100_transform_destroy(&pool->base.transforms[i]); 691 692 if (pool->base.ipps[i] != NULL) 693 dce_ipp_destroy(&pool->base.ipps[i]); 694 695 if (pool->base.mis[i] != NULL) { 696 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 697 pool->base.mis[i] = NULL; 698 } 699 700 if (pool->base.timing_generators[i] != NULL) { 701 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 702 pool->base.timing_generators[i] = NULL; 703 } 704 } 705 706 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 707 if (pool->base.engines[i] != NULL) 708 dce110_engine_destroy(&pool->base.engines[i]); 709 if (pool->base.hw_i2cs[i] != NULL) { 710 kfree(pool->base.hw_i2cs[i]); 711 pool->base.hw_i2cs[i] = NULL; 712 } 713 if (pool->base.sw_i2cs[i] != NULL) { 714 kfree(pool->base.sw_i2cs[i]); 715 pool->base.sw_i2cs[i] = NULL; 716 } 717 } 718 719 for (i = 0; i < pool->base.stream_enc_count; i++) { 720 if (pool->base.stream_enc[i] != NULL) 721 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 722 } 723 724 for (i = 0; i < pool->base.clk_src_count; i++) { 725 if (pool->base.clock_sources[i] != NULL) 726 dce100_clock_source_destroy(&pool->base.clock_sources[i]); 727 } 728 729 if (pool->base.dp_clock_source != NULL) 730 dce100_clock_source_destroy(&pool->base.dp_clock_source); 731 732 for (i = 0; i < pool->base.audio_count; i++) { 733 if (pool->base.audios[i] != NULL) 734 dce_aud_destroy(&pool->base.audios[i]); 735 } 736 737 if (pool->base.abm != NULL) 738 dce_abm_destroy(&pool->base.abm); 739 740 if (pool->base.dmcu != NULL) 741 dce_dmcu_destroy(&pool->base.dmcu); 742 743 if (pool->base.irqs != NULL) 744 dal_irq_service_destroy(&pool->base.irqs); 745 } 746 747 static enum dc_status build_mapped_resource( 748 const struct dc *dc, 749 struct dc_state *context, 750 struct dc_stream_state *stream) 751 { 752 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 753 754 if (!pipe_ctx) 755 return DC_ERROR_UNEXPECTED; 756 757 dce110_resource_build_pipe_hw_param(pipe_ctx); 758 759 resource_build_info_frame(pipe_ctx); 760 761 return DC_OK; 762 } 763 764 bool dce100_validate_bandwidth( 765 struct dc *dc, 766 struct dc_state *context, 767 bool fast_validate) 768 { 769 int i; 770 bool at_least_one_pipe = false; 771 772 for (i = 0; i < dc->res_pool->pipe_count; i++) { 773 if (context->res_ctx.pipe_ctx[i].stream) 774 at_least_one_pipe = true; 775 } 776 777 if (at_least_one_pipe) { 778 /* TODO implement when needed but for now hardcode max value*/ 779 context->bw_ctx.bw.dce.dispclk_khz = 681000; 780 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 781 } else { 782 context->bw_ctx.bw.dce.dispclk_khz = 0; 783 context->bw_ctx.bw.dce.yclk_khz = 0; 784 } 785 786 return true; 787 } 788 789 static bool dce100_validate_surface_sets( 790 struct dc_state *context) 791 { 792 int i; 793 794 for (i = 0; i < context->stream_count; i++) { 795 if (context->stream_status[i].plane_count == 0) 796 continue; 797 798 if (context->stream_status[i].plane_count > 1) 799 return false; 800 801 if (context->stream_status[i].plane_states[0]->format 802 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 803 return false; 804 } 805 806 return true; 807 } 808 809 enum dc_status dce100_validate_global( 810 struct dc *dc, 811 struct dc_state *context) 812 { 813 if (!dce100_validate_surface_sets(context)) 814 return DC_FAIL_SURFACE_VALIDATE; 815 816 return DC_OK; 817 } 818 819 enum dc_status dce100_add_stream_to_ctx( 820 struct dc *dc, 821 struct dc_state *new_ctx, 822 struct dc_stream_state *dc_stream) 823 { 824 enum dc_status result = DC_ERROR_UNEXPECTED; 825 826 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 827 828 if (result == DC_OK) 829 result = resource_map_clock_resources(dc, new_ctx, dc_stream); 830 831 if (result == DC_OK) 832 result = build_mapped_resource(dc, new_ctx, dc_stream); 833 834 return result; 835 } 836 837 static void dce100_destroy_resource_pool(struct resource_pool **pool) 838 { 839 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 840 841 destruct(dce110_pool); 842 kfree(dce110_pool); 843 *pool = NULL; 844 } 845 846 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 847 { 848 849 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 850 return DC_OK; 851 852 return DC_FAIL_SURFACE_VALIDATE; 853 } 854 855 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( 856 struct resource_context *res_ctx, 857 const struct resource_pool *pool, 858 struct dc_stream_state *stream) 859 { 860 int i; 861 int j = -1; 862 struct dc_link *link = stream->link; 863 864 for (i = 0; i < pool->stream_enc_count; i++) { 865 if (!res_ctx->is_stream_enc_acquired[i] && 866 pool->stream_enc[i]) { 867 /* Store first available for MST second display 868 * in daisy chain use case 869 */ 870 j = i; 871 if (pool->stream_enc[i]->id == 872 link->link_enc->preferred_engine) 873 return pool->stream_enc[i]; 874 } 875 } 876 877 /* 878 * below can happen in cases when stream encoder is acquired: 879 * 1) for second MST display in chain, so preferred engine already 880 * acquired; 881 * 2) for another link, which preferred engine already acquired by any 882 * MST configuration. 883 * 884 * If signal is of DP type and preferred engine not found, return last available 885 * 886 * TODO - This is just a patch up and a generic solution is 887 * required for non DP connectors. 888 */ 889 890 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) 891 return pool->stream_enc[j]; 892 893 return NULL; 894 } 895 896 static const struct resource_funcs dce100_res_pool_funcs = { 897 .destroy = dce100_destroy_resource_pool, 898 .link_enc_create = dce100_link_encoder_create, 899 .validate_bandwidth = dce100_validate_bandwidth, 900 .validate_plane = dce100_validate_plane, 901 .add_stream_to_ctx = dce100_add_stream_to_ctx, 902 .validate_global = dce100_validate_global, 903 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 904 }; 905 906 static bool construct( 907 uint8_t num_virtual_links, 908 struct dc *dc, 909 struct dce110_resource_pool *pool) 910 { 911 unsigned int i; 912 struct dc_context *ctx = dc->ctx; 913 struct dc_bios *bp; 914 915 ctx->dc_bios->regs = &bios_regs; 916 917 pool->base.res_cap = &res_cap; 918 pool->base.funcs = &dce100_res_pool_funcs; 919 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 920 921 bp = ctx->dc_bios; 922 923 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 924 pool->base.dp_clock_source = 925 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 926 927 pool->base.clock_sources[0] = 928 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 929 pool->base.clock_sources[1] = 930 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 931 pool->base.clock_sources[2] = 932 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 933 pool->base.clk_src_count = 3; 934 935 } else { 936 pool->base.dp_clock_source = 937 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 938 939 pool->base.clock_sources[0] = 940 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 941 pool->base.clock_sources[1] = 942 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 943 pool->base.clk_src_count = 2; 944 } 945 946 if (pool->base.dp_clock_source == NULL) { 947 dm_error("DC: failed to create dp clock source!\n"); 948 BREAK_TO_DEBUGGER(); 949 goto res_create_fail; 950 } 951 952 for (i = 0; i < pool->base.clk_src_count; i++) { 953 if (pool->base.clock_sources[i] == NULL) { 954 dm_error("DC: failed to create clock sources!\n"); 955 BREAK_TO_DEBUGGER(); 956 goto res_create_fail; 957 } 958 } 959 960 pool->base.dmcu = dce_dmcu_create(ctx, 961 &dmcu_regs, 962 &dmcu_shift, 963 &dmcu_mask); 964 if (pool->base.dmcu == NULL) { 965 dm_error("DC: failed to create dmcu!\n"); 966 BREAK_TO_DEBUGGER(); 967 goto res_create_fail; 968 } 969 970 pool->base.abm = dce_abm_create(ctx, 971 &abm_regs, 972 &abm_shift, 973 &abm_mask); 974 if (pool->base.abm == NULL) { 975 dm_error("DC: failed to create abm!\n"); 976 BREAK_TO_DEBUGGER(); 977 goto res_create_fail; 978 } 979 980 { 981 struct irq_service_init_data init_data; 982 init_data.ctx = dc->ctx; 983 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 984 if (!pool->base.irqs) 985 goto res_create_fail; 986 } 987 988 /************************************************* 989 * Resource + asic cap harcoding * 990 *************************************************/ 991 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 992 pool->base.pipe_count = res_cap.num_timing_generator; 993 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 994 dc->caps.max_downscale_ratio = 200; 995 dc->caps.i2c_speed_in_khz = 40; 996 dc->caps.max_cursor_size = 128; 997 dc->caps.dual_link_dvi = true; 998 dc->caps.disable_dp_clk_share = true; 999 for (i = 0; i < pool->base.pipe_count; i++) { 1000 pool->base.timing_generators[i] = 1001 dce100_timing_generator_create( 1002 ctx, 1003 i, 1004 &dce100_tg_offsets[i]); 1005 if (pool->base.timing_generators[i] == NULL) { 1006 BREAK_TO_DEBUGGER(); 1007 dm_error("DC: failed to create tg!\n"); 1008 goto res_create_fail; 1009 } 1010 1011 pool->base.mis[i] = dce100_mem_input_create(ctx, i); 1012 if (pool->base.mis[i] == NULL) { 1013 BREAK_TO_DEBUGGER(); 1014 dm_error( 1015 "DC: failed to create memory input!\n"); 1016 goto res_create_fail; 1017 } 1018 1019 pool->base.ipps[i] = dce100_ipp_create(ctx, i); 1020 if (pool->base.ipps[i] == NULL) { 1021 BREAK_TO_DEBUGGER(); 1022 dm_error( 1023 "DC: failed to create input pixel processor!\n"); 1024 goto res_create_fail; 1025 } 1026 1027 pool->base.transforms[i] = dce100_transform_create(ctx, i); 1028 if (pool->base.transforms[i] == NULL) { 1029 BREAK_TO_DEBUGGER(); 1030 dm_error( 1031 "DC: failed to create transform!\n"); 1032 goto res_create_fail; 1033 } 1034 1035 pool->base.opps[i] = dce100_opp_create(ctx, i); 1036 if (pool->base.opps[i] == NULL) { 1037 BREAK_TO_DEBUGGER(); 1038 dm_error( 1039 "DC: failed to create output pixel processor!\n"); 1040 goto res_create_fail; 1041 } 1042 } 1043 1044 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1045 pool->base.engines[i] = dce100_aux_engine_create(ctx, i); 1046 if (pool->base.engines[i] == NULL) { 1047 BREAK_TO_DEBUGGER(); 1048 dm_error( 1049 "DC:failed to create aux engine!!\n"); 1050 goto res_create_fail; 1051 } 1052 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i); 1053 if (pool->base.hw_i2cs[i] == NULL) { 1054 BREAK_TO_DEBUGGER(); 1055 dm_error( 1056 "DC:failed to create i2c engine!!\n"); 1057 goto res_create_fail; 1058 } 1059 pool->base.sw_i2cs[i] = NULL; 1060 } 1061 1062 dc->caps.max_planes = pool->base.pipe_count; 1063 1064 for (i = 0; i < dc->caps.max_planes; ++i) 1065 dc->caps.planes[i] = plane_cap; 1066 1067 if (!resource_construct(num_virtual_links, dc, &pool->base, 1068 &res_create_funcs)) 1069 goto res_create_fail; 1070 1071 /* Create hardware sequencer */ 1072 dce100_hw_sequencer_construct(dc); 1073 return true; 1074 1075 res_create_fail: 1076 destruct(pool); 1077 1078 return false; 1079 } 1080 1081 struct resource_pool *dce100_create_resource_pool( 1082 uint8_t num_virtual_links, 1083 struct dc *dc) 1084 { 1085 struct dce110_resource_pool *pool = 1086 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1087 1088 if (!pool) 1089 return NULL; 1090 1091 if (construct(num_virtual_links, dc, pool)) 1092 return &pool->base; 1093 1094 kfree(pool); 1095 BREAK_TO_DEBUGGER(); 1096 return NULL; 1097 } 1098 1099