1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef MBOX_H 12 #define MBOX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/sizes.h> 16 17 #include "rvu_struct.h" 18 #include "common.h" 19 20 #define MBOX_SIZE SZ_64K 21 22 /* AF/PF: PF initiated, PF/VF VF initiated */ 23 #define MBOX_DOWN_RX_START 0 24 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K) 25 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE) 26 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K) 27 /* AF/PF: AF initiated, PF/VF PF initiated */ 28 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE) 29 #define MBOX_UP_RX_SIZE SZ_1K 30 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE) 31 #define MBOX_UP_TX_SIZE SZ_1K 32 33 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE 34 # error "incorrect mailbox area sizes" 35 #endif 36 37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull)) 38 39 #define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */ 40 41 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */ 42 43 /* Mailbox directions */ 44 #define MBOX_DIR_AFPF 0 /* AF replies to PF */ 45 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */ 46 #define MBOX_DIR_PFVF 2 /* PF replies to VF */ 47 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */ 48 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */ 49 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */ 50 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */ 51 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */ 52 53 struct otx2_mbox_dev { 54 void *mbase; /* This dev's mbox region */ 55 spinlock_t mbox_lock; 56 u16 msg_size; /* Total msg size to be sent */ 57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */ 58 u16 num_msgs; /* No of msgs sent or waiting for response */ 59 u16 msgs_acked; /* No of msgs for which response is received */ 60 }; 61 62 struct otx2_mbox { 63 struct pci_dev *pdev; 64 void *hwbase; /* Mbox region advertised by HW */ 65 void *reg_base;/* CSR base for this dev */ 66 u64 trigger; /* Trigger mbox notification */ 67 u16 tr_shift; /* Mbox trigger shift */ 68 u64 rx_start; /* Offset of Rx region in mbox memory */ 69 u64 tx_start; /* Offset of Tx region in mbox memory */ 70 u16 rx_size; /* Size of Rx region */ 71 u16 tx_size; /* Size of Tx region */ 72 u16 ndevs; /* The number of peers */ 73 struct otx2_mbox_dev *dev; 74 }; 75 76 /* Header which preceeds all mbox messages */ 77 struct mbox_hdr { 78 u64 msg_size; /* Total msgs size embedded */ 79 u16 num_msgs; /* No of msgs embedded */ 80 }; 81 82 /* Header which preceeds every msg and is also part of it */ 83 struct mbox_msghdr { 84 u16 pcifunc; /* Who's sending this msg */ 85 u16 id; /* Mbox message ID */ 86 #define OTX2_MBOX_REQ_SIG (0xdead) 87 #define OTX2_MBOX_RSP_SIG (0xbeef) 88 u16 sig; /* Signature, for validating corrupted msgs */ 89 #define OTX2_MBOX_VERSION (0x0001) 90 u16 ver; /* Version of msg's structure for this ID */ 91 u16 next_msgoff; /* Offset of next msg within mailbox region */ 92 int rc; /* Msg process'ed response code */ 93 }; 94 95 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid); 96 void otx2_mbox_destroy(struct otx2_mbox *mbox); 97 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase, 98 struct pci_dev *pdev, void __force *reg_base, 99 int direction, int ndevs); 100 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid); 101 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid); 102 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid); 103 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, 104 int size, int size_rsp); 105 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, 106 struct mbox_msghdr *msg); 107 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid); 108 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, 109 u16 pcifunc, u16 id); 110 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid); 111 const char *otx2_mbox_id2name(u16 id); 112 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox, 113 int devid, int size) 114 { 115 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0); 116 } 117 118 /* Mailbox message types */ 119 #define MBOX_MSG_MASK 0xFFFF 120 #define MBOX_MSG_INVALID 0xFFFE 121 #define MBOX_MSG_MAX 0xFFFF 122 123 #define MBOX_MESSAGES \ 124 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \ 125 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \ 126 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \ 127 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \ 128 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \ 129 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \ 130 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \ 131 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ 132 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ 133 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ 134 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \ 135 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \ 136 cgx_mac_addr_set_or_get) \ 137 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \ 138 cgx_mac_addr_set_or_get) \ 139 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \ 140 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \ 141 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \ 142 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \ 143 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \ 144 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \ 145 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \ 146 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \ 147 cgx_pause_frm_cfg) \ 148 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ 149 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \ 150 npa_lf_alloc_req, npa_lf_alloc_rsp) \ 151 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \ 152 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \ 153 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\ 154 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \ 155 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \ 156 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \ 157 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \ 158 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\ 159 npc_mcam_alloc_entry_rsp) \ 160 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \ 161 npc_mcam_free_entry_req, msg_rsp) \ 162 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \ 163 npc_mcam_write_entry_req, msg_rsp) \ 164 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \ 165 npc_mcam_ena_dis_entry_req, msg_rsp) \ 166 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \ 167 npc_mcam_ena_dis_entry_req, msg_rsp) \ 168 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\ 169 npc_mcam_shift_entry_rsp) \ 170 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \ 171 npc_mcam_alloc_counter_req, \ 172 npc_mcam_alloc_counter_rsp) \ 173 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \ 174 npc_mcam_oper_counter_req, msg_rsp) \ 175 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \ 176 npc_mcam_unmap_counter_req, msg_rsp) \ 177 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \ 178 npc_mcam_oper_counter_req, msg_rsp) \ 179 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \ 180 npc_mcam_oper_counter_req, \ 181 npc_mcam_oper_counter_rsp) \ 182 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \ 183 npc_mcam_alloc_and_write_entry_req, \ 184 npc_mcam_alloc_and_write_entry_rsp) \ 185 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \ 186 msg_req, npc_get_kex_cfg_rsp) \ 187 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ 188 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ 189 nix_lf_alloc_req, nix_lf_alloc_rsp) \ 190 M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \ 191 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \ 192 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \ 193 hwctx_disable_req, msg_rsp) \ 194 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \ 195 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \ 196 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \ 197 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 198 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \ 199 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \ 200 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \ 201 nix_rss_flowkey_cfg, \ 202 nix_rss_flowkey_cfg_rsp) \ 203 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \ 204 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \ 205 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \ 206 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \ 207 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \ 208 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \ 209 nix_mark_format_cfg, \ 210 nix_mark_format_cfg_rsp) \ 211 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \ 212 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \ 213 nix_lso_format_cfg, \ 214 nix_lso_format_cfg_rsp) \ 215 M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) \ 216 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 217 nix_bp_cfg_rsp) \ 218 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 219 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \ 220 221 /* Messages initiated by AF (range 0xC00 - 0xDFF) */ 222 #define MBOX_UP_CGX_MESSAGES \ 223 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) 224 225 enum { 226 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id, 227 MBOX_MESSAGES 228 MBOX_UP_CGX_MESSAGES 229 #undef M 230 }; 231 232 /* Mailbox message formats */ 233 234 #define RVU_DEFAULT_PF_FUNC 0xFFFF 235 236 /* Generic request msg used for those mbox messages which 237 * don't send any data in the request. 238 */ 239 struct msg_req { 240 struct mbox_msghdr hdr; 241 }; 242 243 /* Generic rsponse msg used a ack or response for those mbox 244 * messages which doesn't have a specific rsp msg format. 245 */ 246 struct msg_rsp { 247 struct mbox_msghdr hdr; 248 }; 249 250 /* RVU mailbox error codes 251 * Range 256 - 300. 252 */ 253 enum rvu_af_status { 254 RVU_INVALID_VF_ID = -256, 255 }; 256 257 struct ready_msg_rsp { 258 struct mbox_msghdr hdr; 259 u16 sclk_freq; /* SCLK frequency (in MHz) */ 260 u16 rclk_freq; /* RCLK frequency (in MHz) */ 261 }; 262 263 /* Structure for requesting resource provisioning. 264 * 'modify' flag to be used when either requesting more 265 * or to detach partial of a cetain resource type. 266 * Rest of the fields specify how many of what type to 267 * be attached. 268 */ 269 struct rsrc_attach { 270 struct mbox_msghdr hdr; 271 u8 modify:1; 272 u8 npalf:1; 273 u8 nixlf:1; 274 u16 sso; 275 u16 ssow; 276 u16 timlfs; 277 u16 cptlfs; 278 }; 279 280 /* Structure for relinquishing resources. 281 * 'partial' flag to be used when relinquishing all resources 282 * but only of a certain type. If not set, all resources of all 283 * types provisioned to the RVU function will be detached. 284 */ 285 struct rsrc_detach { 286 struct mbox_msghdr hdr; 287 u8 partial:1; 288 u8 npalf:1; 289 u8 nixlf:1; 290 u8 sso:1; 291 u8 ssow:1; 292 u8 timlfs:1; 293 u8 cptlfs:1; 294 }; 295 296 #define MSIX_VECTOR_INVALID 0xFFFF 297 #define MAX_RVU_BLKLF_CNT 256 298 299 struct msix_offset_rsp { 300 struct mbox_msghdr hdr; 301 u16 npa_msixoff; 302 u16 nix_msixoff; 303 u8 sso; 304 u8 ssow; 305 u8 timlfs; 306 u8 cptlfs; 307 u16 sso_msixoff[MAX_RVU_BLKLF_CNT]; 308 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT]; 309 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT]; 310 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT]; 311 }; 312 313 struct get_hw_cap_rsp { 314 struct mbox_msghdr hdr; 315 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 316 u8 nix_shaping; /* Is shaping and coloring supported */ 317 }; 318 319 /* CGX mbox message formats */ 320 321 struct cgx_stats_rsp { 322 struct mbox_msghdr hdr; 323 #define CGX_RX_STATS_COUNT 13 324 #define CGX_TX_STATS_COUNT 18 325 u64 rx_stats[CGX_RX_STATS_COUNT]; 326 u64 tx_stats[CGX_TX_STATS_COUNT]; 327 }; 328 329 /* Structure for requesting the operation for 330 * setting/getting mac address in the CGX interface 331 */ 332 struct cgx_mac_addr_set_or_get { 333 struct mbox_msghdr hdr; 334 u8 mac_addr[ETH_ALEN]; 335 }; 336 337 struct cgx_link_user_info { 338 uint64_t link_up:1; 339 uint64_t full_duplex:1; 340 uint64_t lmac_type_id:4; 341 uint64_t speed:20; /* speed in Mbps */ 342 #define LMACTYPE_STR_LEN 16 343 char lmac_type[LMACTYPE_STR_LEN]; 344 }; 345 346 struct cgx_link_info_msg { 347 struct mbox_msghdr hdr; 348 struct cgx_link_user_info link_info; 349 }; 350 351 struct cgx_pause_frm_cfg { 352 struct mbox_msghdr hdr; 353 u8 set; 354 /* set = 1 if the request is to config pause frames */ 355 /* set = 0 if the request is to fetch pause frames config */ 356 u8 rx_pause; 357 u8 tx_pause; 358 }; 359 360 /* NPA mbox message formats */ 361 362 /* NPA mailbox error codes 363 * Range 301 - 400. 364 */ 365 enum npa_af_status { 366 NPA_AF_ERR_PARAM = -301, 367 NPA_AF_ERR_AQ_FULL = -302, 368 NPA_AF_ERR_AQ_ENQUEUE = -303, 369 NPA_AF_ERR_AF_LF_INVALID = -304, 370 NPA_AF_ERR_AF_LF_ALLOC = -305, 371 NPA_AF_ERR_LF_RESET = -306, 372 }; 373 374 /* For NPA LF context alloc and init */ 375 struct npa_lf_alloc_req { 376 struct mbox_msghdr hdr; 377 int node; 378 int aura_sz; /* No of auras */ 379 u32 nr_pools; /* No of pools */ 380 u64 way_mask; 381 }; 382 383 struct npa_lf_alloc_rsp { 384 struct mbox_msghdr hdr; 385 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 386 u32 stack_pg_bytes; /* Size of stack page */ 387 u16 qints; /* NPA_AF_CONST::QINTS */ 388 }; 389 390 /* NPA AQ enqueue msg */ 391 struct npa_aq_enq_req { 392 struct mbox_msghdr hdr; 393 u32 aura_id; 394 u8 ctype; 395 u8 op; 396 union { 397 /* Valid when op == WRITE/INIT and ctype == AURA. 398 * LF fills the pool_id in aura.pool_addr. AF will translate 399 * the pool_id to pool context pointer. 400 */ 401 struct npa_aura_s aura; 402 /* Valid when op == WRITE/INIT and ctype == POOL */ 403 struct npa_pool_s pool; 404 }; 405 /* Mask data when op == WRITE (1=write, 0=don't write) */ 406 union { 407 /* Valid when op == WRITE and ctype == AURA */ 408 struct npa_aura_s aura_mask; 409 /* Valid when op == WRITE and ctype == POOL */ 410 struct npa_pool_s pool_mask; 411 }; 412 }; 413 414 struct npa_aq_enq_rsp { 415 struct mbox_msghdr hdr; 416 union { 417 /* Valid when op == READ and ctype == AURA */ 418 struct npa_aura_s aura; 419 /* Valid when op == READ and ctype == POOL */ 420 struct npa_pool_s pool; 421 }; 422 }; 423 424 /* Disable all contexts of type 'ctype' */ 425 struct hwctx_disable_req { 426 struct mbox_msghdr hdr; 427 u8 ctype; 428 }; 429 430 /* NIX mbox message formats */ 431 432 /* NIX mailbox error codes 433 * Range 401 - 500. 434 */ 435 enum nix_af_status { 436 NIX_AF_ERR_PARAM = -401, 437 NIX_AF_ERR_AQ_FULL = -402, 438 NIX_AF_ERR_AQ_ENQUEUE = -403, 439 NIX_AF_ERR_AF_LF_INVALID = -404, 440 NIX_AF_ERR_AF_LF_ALLOC = -405, 441 NIX_AF_ERR_TLX_ALLOC_FAIL = -406, 442 NIX_AF_ERR_TLX_INVALID = -407, 443 NIX_AF_ERR_RSS_SIZE_INVALID = -408, 444 NIX_AF_ERR_RSS_GRPS_INVALID = -409, 445 NIX_AF_ERR_FRS_INVALID = -410, 446 NIX_AF_ERR_RX_LINK_INVALID = -411, 447 NIX_AF_INVAL_TXSCHQ_CFG = -412, 448 NIX_AF_SMQ_FLUSH_FAILED = -413, 449 NIX_AF_ERR_LF_RESET = -414, 450 NIX_AF_ERR_RSS_NOSPC_FIELD = -415, 451 NIX_AF_ERR_RSS_NOSPC_ALGO = -416, 452 NIX_AF_ERR_MARK_CFG_FAIL = -417, 453 NIX_AF_ERR_LSO_CFG_FAIL = -418, 454 NIX_AF_INVAL_NPA_PF_FUNC = -419, 455 NIX_AF_INVAL_SSO_PF_FUNC = -420, 456 }; 457 458 /* For NIX LF context alloc and init */ 459 struct nix_lf_alloc_req { 460 struct mbox_msghdr hdr; 461 int node; 462 u32 rq_cnt; /* No of receive queues */ 463 u32 sq_cnt; /* No of send queues */ 464 u32 cq_cnt; /* No of completion queues */ 465 u8 xqe_sz; 466 u16 rss_sz; 467 u8 rss_grps; 468 u16 npa_func; 469 u16 sso_func; 470 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */ 471 u64 way_mask; 472 }; 473 474 struct nix_lf_alloc_rsp { 475 struct mbox_msghdr hdr; 476 u16 sqb_size; 477 u16 rx_chan_base; 478 u16 tx_chan_base; 479 u8 rx_chan_cnt; /* total number of RX channels */ 480 u8 tx_chan_cnt; /* total number of TX channels */ 481 u8 lso_tsov4_idx; 482 u8 lso_tsov6_idx; 483 u8 mac_addr[ETH_ALEN]; 484 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */ 485 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */ 486 u16 cints; /* NIX_AF_CONST2::CINTS */ 487 u16 qints; /* NIX_AF_CONST2::QINTS */ 488 }; 489 490 /* NIX AQ enqueue msg */ 491 struct nix_aq_enq_req { 492 struct mbox_msghdr hdr; 493 u32 qidx; 494 u8 ctype; 495 u8 op; 496 union { 497 struct nix_rq_ctx_s rq; 498 struct nix_sq_ctx_s sq; 499 struct nix_cq_ctx_s cq; 500 struct nix_rsse_s rss; 501 struct nix_rx_mce_s mce; 502 }; 503 union { 504 struct nix_rq_ctx_s rq_mask; 505 struct nix_sq_ctx_s sq_mask; 506 struct nix_cq_ctx_s cq_mask; 507 struct nix_rsse_s rss_mask; 508 struct nix_rx_mce_s mce_mask; 509 }; 510 }; 511 512 struct nix_aq_enq_rsp { 513 struct mbox_msghdr hdr; 514 union { 515 struct nix_rq_ctx_s rq; 516 struct nix_sq_ctx_s sq; 517 struct nix_cq_ctx_s cq; 518 struct nix_rsse_s rss; 519 struct nix_rx_mce_s mce; 520 }; 521 }; 522 523 /* Tx scheduler/shaper mailbox messages */ 524 525 #define MAX_TXSCHQ_PER_FUNC 128 526 527 struct nix_txsch_alloc_req { 528 struct mbox_msghdr hdr; 529 /* Scheduler queue count request at each level */ 530 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ 531 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ 532 }; 533 534 struct nix_txsch_alloc_rsp { 535 struct mbox_msghdr hdr; 536 /* Scheduler queue count allocated at each level */ 537 u16 schq_contig[NIX_TXSCH_LVL_CNT]; 538 u16 schq[NIX_TXSCH_LVL_CNT]; 539 /* Scheduler queue list allocated at each level */ 540 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 541 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 542 u8 aggr_level; /* Traffic aggregation scheduler level */ 543 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */ 544 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */ 545 }; 546 547 struct nix_txsch_free_req { 548 struct mbox_msghdr hdr; 549 #define TXSCHQ_FREE_ALL BIT_ULL(0) 550 u16 flags; 551 /* Scheduler queue level to be freed */ 552 u16 schq_lvl; 553 /* List of scheduler queues to be freed */ 554 u16 schq; 555 }; 556 557 struct nix_txschq_config { 558 struct mbox_msghdr hdr; 559 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ 560 #define TXSCHQ_IDX_SHIFT 16 561 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) 562 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) 563 u8 num_regs; 564 #define MAX_REGS_PER_MBOX_MSG 20 565 u64 reg[MAX_REGS_PER_MBOX_MSG]; 566 u64 regval[MAX_REGS_PER_MBOX_MSG]; 567 }; 568 569 struct nix_vtag_config { 570 struct mbox_msghdr hdr; 571 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */ 572 u8 vtag_size; 573 /* cfg_type is '0' for tx vlan cfg 574 * cfg_type is '1' for rx vlan cfg 575 */ 576 u8 cfg_type; 577 union { 578 /* valid when cfg_type is '0' */ 579 struct { 580 /* tx vlan0 tag(C-VLAN) */ 581 u64 vlan0; 582 /* tx vlan1 tag(S-VLAN) */ 583 u64 vlan1; 584 /* insert tx vlan tag */ 585 u8 insert_vlan :1; 586 /* insert tx double vlan tag */ 587 u8 double_vlan :1; 588 } tx; 589 590 /* valid when cfg_type is '1' */ 591 struct { 592 /* rx vtag type index, valid values are in 0..7 range */ 593 u8 vtag_type; 594 /* rx vtag strip */ 595 u8 strip_vtag :1; 596 /* rx vtag capture */ 597 u8 capture_vtag :1; 598 } rx; 599 }; 600 }; 601 602 struct nix_rss_flowkey_cfg { 603 struct mbox_msghdr hdr; 604 int mcam_index; /* MCAM entry index to modify */ 605 #define NIX_FLOW_KEY_TYPE_PORT BIT(0) 606 #define NIX_FLOW_KEY_TYPE_IPV4 BIT(1) 607 #define NIX_FLOW_KEY_TYPE_IPV6 BIT(2) 608 #define NIX_FLOW_KEY_TYPE_TCP BIT(3) 609 #define NIX_FLOW_KEY_TYPE_UDP BIT(4) 610 #define NIX_FLOW_KEY_TYPE_SCTP BIT(5) 611 #define NIX_FLOW_KEY_TYPE_NVGRE BIT(6) 612 #define NIX_FLOW_KEY_TYPE_VXLAN BIT(7) 613 #define NIX_FLOW_KEY_TYPE_GENEVE BIT(8) 614 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9) 615 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10) 616 #define NIX_FLOW_KEY_TYPE_GTPU BIT(11) 617 #define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12) 618 #define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13) 619 #define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14) 620 #define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15) 621 #define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16) 622 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17) 623 u32 flowkey_cfg; /* Flowkey types selected */ 624 u8 group; /* RSS context or group */ 625 }; 626 627 struct nix_rss_flowkey_cfg_rsp { 628 struct mbox_msghdr hdr; 629 u8 alg_idx; /* Selected algo index */ 630 }; 631 632 struct nix_set_mac_addr { 633 struct mbox_msghdr hdr; 634 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */ 635 }; 636 637 struct nix_get_mac_addr_rsp { 638 struct mbox_msghdr hdr; 639 u8 mac_addr[ETH_ALEN]; 640 }; 641 642 struct nix_mark_format_cfg { 643 struct mbox_msghdr hdr; 644 u8 offset; 645 u8 y_mask; 646 u8 y_val; 647 u8 r_mask; 648 u8 r_val; 649 }; 650 651 struct nix_mark_format_cfg_rsp { 652 struct mbox_msghdr hdr; 653 u8 mark_format_idx; 654 }; 655 656 struct nix_rx_mode { 657 struct mbox_msghdr hdr; 658 #define NIX_RX_MODE_UCAST BIT(0) 659 #define NIX_RX_MODE_PROMISC BIT(1) 660 #define NIX_RX_MODE_ALLMULTI BIT(2) 661 u16 mode; 662 }; 663 664 struct nix_rx_cfg { 665 struct mbox_msghdr hdr; 666 #define NIX_RX_OL3_VERIFY BIT(0) 667 #define NIX_RX_OL4_VERIFY BIT(1) 668 u8 len_verify; /* Outer L3/L4 len check */ 669 #define NIX_RX_CSUM_OL4_VERIFY BIT(0) 670 u8 csum_verify; /* Outer L4 checksum verification */ 671 }; 672 673 struct nix_frs_cfg { 674 struct mbox_msghdr hdr; 675 u8 update_smq; /* Update SMQ's min/max lens */ 676 u8 update_minlen; /* Set minlen also */ 677 u8 sdp_link; /* Set SDP RX link */ 678 u16 maxlen; 679 u16 minlen; 680 }; 681 682 struct nix_lso_format_cfg { 683 struct mbox_msghdr hdr; 684 u64 field_mask; 685 #define NIX_LSO_FIELD_MAX 8 686 u64 fields[NIX_LSO_FIELD_MAX]; 687 }; 688 689 struct nix_lso_format_cfg_rsp { 690 struct mbox_msghdr hdr; 691 u8 lso_format_idx; 692 }; 693 694 struct nix_bp_cfg_req { 695 struct mbox_msghdr hdr; 696 u16 chan_base; /* Starting channel number */ 697 u8 chan_cnt; /* Number of channels */ 698 u8 bpid_per_chan; 699 /* bpid_per_chan = 0 assigns single bp id for range of channels */ 700 /* bpid_per_chan = 1 assigns separate bp id for each channel */ 701 }; 702 703 /* PF can be mapped to either CGX or LBK interface, 704 * so maximum 64 channels are possible. 705 */ 706 #define NIX_MAX_BPID_CHAN 64 707 struct nix_bp_cfg_rsp { 708 struct mbox_msghdr hdr; 709 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */ 710 u8 chan_cnt; /* Number of channel for which bpids are assigned */ 711 }; 712 713 /* NPC mbox message structs */ 714 715 #define NPC_MCAM_ENTRY_INVALID 0xFFFF 716 #define NPC_MCAM_INVALID_MAP 0xFFFF 717 718 /* NPC mailbox error codes 719 * Range 701 - 800. 720 */ 721 enum npc_af_status { 722 NPC_MCAM_INVALID_REQ = -701, 723 NPC_MCAM_ALLOC_DENIED = -702, 724 NPC_MCAM_ALLOC_FAILED = -703, 725 NPC_MCAM_PERM_DENIED = -704, 726 }; 727 728 struct npc_mcam_alloc_entry_req { 729 struct mbox_msghdr hdr; 730 #define NPC_MAX_NONCONTIG_ENTRIES 256 731 u8 contig; /* Contiguous entries ? */ 732 #define NPC_MCAM_ANY_PRIO 0 733 #define NPC_MCAM_LOWER_PRIO 1 734 #define NPC_MCAM_HIGHER_PRIO 2 735 u8 priority; /* Lower or higher w.r.t ref_entry */ 736 u16 ref_entry; 737 u16 count; /* Number of entries requested */ 738 }; 739 740 struct npc_mcam_alloc_entry_rsp { 741 struct mbox_msghdr hdr; 742 u16 entry; /* Entry allocated or start index if contiguous. 743 * Invalid incase of non-contiguous. 744 */ 745 u16 count; /* Number of entries allocated */ 746 u16 free_count; /* Number of entries available */ 747 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 748 }; 749 750 struct npc_mcam_free_entry_req { 751 struct mbox_msghdr hdr; 752 u16 entry; /* Entry index to be freed */ 753 u8 all; /* If all entries allocated to this PFVF to be freed */ 754 }; 755 756 struct mcam_entry { 757 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */ 758 u64 kw[NPC_MAX_KWS_IN_KEY]; 759 u64 kw_mask[NPC_MAX_KWS_IN_KEY]; 760 u64 action; 761 u64 vtag_action; 762 }; 763 764 struct npc_mcam_write_entry_req { 765 struct mbox_msghdr hdr; 766 struct mcam_entry entry_data; 767 u16 entry; /* MCAM entry to write this match key */ 768 u16 cntr; /* Counter for this MCAM entry */ 769 u8 intf; /* Rx or Tx interface */ 770 u8 enable_entry;/* Enable this MCAM entry ? */ 771 u8 set_cntr; /* Set counter for this entry ? */ 772 }; 773 774 /* Enable/Disable a given entry */ 775 struct npc_mcam_ena_dis_entry_req { 776 struct mbox_msghdr hdr; 777 u16 entry; 778 }; 779 780 struct npc_mcam_shift_entry_req { 781 struct mbox_msghdr hdr; 782 #define NPC_MCAM_MAX_SHIFTS 64 783 u16 curr_entry[NPC_MCAM_MAX_SHIFTS]; 784 u16 new_entry[NPC_MCAM_MAX_SHIFTS]; 785 u16 shift_count; /* Number of entries to shift */ 786 }; 787 788 struct npc_mcam_shift_entry_rsp { 789 struct mbox_msghdr hdr; 790 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */ 791 }; 792 793 struct npc_mcam_alloc_counter_req { 794 struct mbox_msghdr hdr; 795 u8 contig; /* Contiguous counters ? */ 796 #define NPC_MAX_NONCONTIG_COUNTERS 64 797 u16 count; /* Number of counters requested */ 798 }; 799 800 struct npc_mcam_alloc_counter_rsp { 801 struct mbox_msghdr hdr; 802 u16 cntr; /* Counter allocated or start index if contiguous. 803 * Invalid incase of non-contiguous. 804 */ 805 u16 count; /* Number of counters allocated */ 806 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS]; 807 }; 808 809 struct npc_mcam_oper_counter_req { 810 struct mbox_msghdr hdr; 811 u16 cntr; /* Free a counter or clear/fetch it's stats */ 812 }; 813 814 struct npc_mcam_oper_counter_rsp { 815 struct mbox_msghdr hdr; 816 u64 stat; /* valid only while fetching counter's stats */ 817 }; 818 819 struct npc_mcam_unmap_counter_req { 820 struct mbox_msghdr hdr; 821 u16 cntr; 822 u16 entry; /* Entry and counter to be unmapped */ 823 u8 all; /* Unmap all entries using this counter ? */ 824 }; 825 826 struct npc_mcam_alloc_and_write_entry_req { 827 struct mbox_msghdr hdr; 828 struct mcam_entry entry_data; 829 u16 ref_entry; 830 u8 priority; /* Lower or higher w.r.t ref_entry */ 831 u8 intf; /* Rx or Tx interface */ 832 u8 enable_entry;/* Enable this MCAM entry ? */ 833 u8 alloc_cntr; /* Allocate counter and map ? */ 834 }; 835 836 struct npc_mcam_alloc_and_write_entry_rsp { 837 struct mbox_msghdr hdr; 838 u16 entry; 839 u16 cntr; 840 }; 841 842 struct npc_get_kex_cfg_rsp { 843 struct mbox_msghdr hdr; 844 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */ 845 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */ 846 #define NPC_MAX_INTF 2 847 #define NPC_MAX_LID 8 848 #define NPC_MAX_LT 16 849 #define NPC_MAX_LD 2 850 #define NPC_MAX_LFL 16 851 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 852 u64 kex_ld_flags[NPC_MAX_LD]; 853 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 854 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 855 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 856 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 857 #define MKEX_NAME_LEN 128 858 u8 mkex_pfl_name[MKEX_NAME_LEN]; 859 }; 860 861 #endif /* MBOX_H */ 862