1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 15 #include "rvu_struct.h" 16 #include "rvu_reg.h" 17 #include "rvu.h" 18 #include "npc.h" 19 #include "cgx.h" 20 #include "npc_profile.h" 21 22 #define RSVD_MCAM_ENTRIES_PER_PF 2 /* Bcast & Promisc */ 23 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */ 24 25 #define NIXLF_UCAST_ENTRY 0 26 #define NIXLF_BCAST_ENTRY 1 27 #define NIXLF_PROMISC_ENTRY 2 28 29 #define NPC_PARSE_RESULT_DMAC_OFFSET 8 30 31 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 32 int blkaddr, u16 pcifunc); 33 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 34 u16 pcifunc); 35 36 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) 37 { 38 int blkaddr; 39 u64 val = 0; 40 41 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 42 if (blkaddr < 0) 43 return; 44 45 /* Config CPI base for the PKIND */ 46 val = pkind | 1ULL << 62; 47 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); 48 } 49 50 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) 51 { 52 struct npc_pkind *pkind = &rvu->hw->pkind; 53 u32 map; 54 int i; 55 56 for (i = 0; i < pkind->rsrc.max; i++) { 57 map = pkind->pfchan_map[i]; 58 if (((map >> 16) & 0x3F) == pf) 59 return i; 60 } 61 return -1; 62 } 63 64 static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, 65 u16 pcifunc, int nixlf, int type) 66 { 67 int pf = rvu_get_pf(pcifunc); 68 int index; 69 70 /* Check if this is for a PF */ 71 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) { 72 /* Reserved entries exclude PF0 */ 73 pf--; 74 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF); 75 /* Broadcast address matching entry should be first so 76 * that the packet can be replicated to all VFs. 77 */ 78 if (type == NIXLF_BCAST_ENTRY) 79 return index; 80 else if (type == NIXLF_PROMISC_ENTRY) 81 return index + 1; 82 } 83 84 return (mcam->nixlf_offset + (nixlf * RSVD_MCAM_ENTRIES_PER_NIXLF)); 85 } 86 87 static int npc_get_bank(struct npc_mcam *mcam, int index) 88 { 89 int bank = index / mcam->banksize; 90 91 /* 0,1 & 2,3 banks are combined for this keysize */ 92 if (mcam->keysize == NPC_MCAM_KEY_X2) 93 return bank ? 2 : 0; 94 95 return bank; 96 } 97 98 static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, 99 int blkaddr, int index) 100 { 101 int bank = npc_get_bank(mcam, index); 102 u64 cfg; 103 104 index &= (mcam->banksize - 1); 105 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank)); 106 return (cfg & 1); 107 } 108 109 static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 110 int blkaddr, int index, bool enable) 111 { 112 int bank = npc_get_bank(mcam, index); 113 int actbank = bank; 114 115 index &= (mcam->banksize - 1); 116 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 117 rvu_write64(rvu, blkaddr, 118 NPC_AF_MCAMEX_BANKX_CFG(index, bank), 119 enable ? 1 : 0); 120 } 121 } 122 123 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 124 int blkaddr, int index) 125 { 126 int bank = npc_get_bank(mcam, index); 127 int actbank = bank; 128 129 index &= (mcam->banksize - 1); 130 for (; bank < (actbank + mcam->banks_per_entry); bank++) { 131 rvu_write64(rvu, blkaddr, 132 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0); 133 rvu_write64(rvu, blkaddr, 134 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0); 135 136 rvu_write64(rvu, blkaddr, 137 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0); 138 rvu_write64(rvu, blkaddr, 139 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0); 140 141 rvu_write64(rvu, blkaddr, 142 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0); 143 rvu_write64(rvu, blkaddr, 144 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0); 145 } 146 } 147 148 static void npc_get_keyword(struct mcam_entry *entry, int idx, 149 u64 *cam0, u64 *cam1) 150 { 151 u64 kw_mask = 0x00; 152 153 #define CAM_MASK(n) (BIT_ULL(n) - 1) 154 155 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and 156 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1. 157 * 158 * Also, only 48 bits of BANKX_CAMX_W1 are valid. 159 */ 160 switch (idx) { 161 case 0: 162 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */ 163 *cam1 = entry->kw[0]; 164 kw_mask = entry->kw_mask[0]; 165 break; 166 case 1: 167 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */ 168 *cam1 = entry->kw[1] & CAM_MASK(48); 169 kw_mask = entry->kw_mask[1] & CAM_MASK(48); 170 break; 171 case 2: 172 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48> 173 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0> 174 */ 175 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16); 176 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16); 177 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16); 178 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16); 179 break; 180 case 3: 181 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48> 182 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0> 183 */ 184 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16); 185 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16); 186 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16); 187 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16); 188 break; 189 case 4: 190 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32> 191 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0> 192 */ 193 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32); 194 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32); 195 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32); 196 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32); 197 break; 198 case 5: 199 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32> 200 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0> 201 */ 202 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32); 203 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32); 204 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32); 205 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32); 206 break; 207 case 6: 208 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16> 209 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0> 210 */ 211 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48); 212 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48); 213 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48); 214 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48); 215 break; 216 case 7: 217 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */ 218 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48); 219 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48); 220 break; 221 } 222 223 *cam1 &= kw_mask; 224 *cam0 = ~*cam1 & kw_mask; 225 } 226 227 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 228 int blkaddr, int index, u8 intf, 229 struct mcam_entry *entry, bool enable) 230 { 231 int bank = npc_get_bank(mcam, index); 232 int kw = 0, actbank, actindex; 233 u64 cam0, cam1; 234 235 actbank = bank; /* Save bank id, to set action later on */ 236 actindex = index; 237 index &= (mcam->banksize - 1); 238 239 /* Disable before mcam entry update */ 240 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false); 241 242 /* Clear mcam entry to avoid writes being suppressed by NPC */ 243 npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex); 244 245 /* CAM1 takes the comparison value and 246 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'. 247 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0 248 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1 249 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare. 250 */ 251 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) { 252 /* Interface should be set in all banks */ 253 rvu_write64(rvu, blkaddr, 254 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 255 intf); 256 rvu_write64(rvu, blkaddr, 257 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 258 ~intf & 0x3); 259 260 /* Set the match key */ 261 npc_get_keyword(entry, kw, &cam0, &cam1); 262 rvu_write64(rvu, blkaddr, 263 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1); 264 rvu_write64(rvu, blkaddr, 265 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0); 266 267 npc_get_keyword(entry, kw + 1, &cam0, &cam1); 268 rvu_write64(rvu, blkaddr, 269 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1); 270 rvu_write64(rvu, blkaddr, 271 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0); 272 } 273 274 /* Set 'action' */ 275 rvu_write64(rvu, blkaddr, 276 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action); 277 278 /* Set TAG 'action' */ 279 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank), 280 entry->vtag_action); 281 282 /* Enable the entry */ 283 if (enable) 284 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true); 285 } 286 287 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 288 int blkaddr, u16 src, u16 dest) 289 { 290 int dbank = npc_get_bank(mcam, dest); 291 int sbank = npc_get_bank(mcam, src); 292 u64 cfg, sreg, dreg; 293 int bank, i; 294 295 src &= (mcam->banksize - 1); 296 dest &= (mcam->banksize - 1); 297 298 /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */ 299 for (bank = 0; bank < mcam->banks_per_entry; bank++) { 300 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0); 301 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0); 302 for (i = 0; i < 6; i++) { 303 cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8)); 304 rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg); 305 } 306 } 307 308 /* Copy action */ 309 cfg = rvu_read64(rvu, blkaddr, 310 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank)); 311 rvu_write64(rvu, blkaddr, 312 NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg); 313 314 /* Copy TAG action */ 315 cfg = rvu_read64(rvu, blkaddr, 316 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank)); 317 rvu_write64(rvu, blkaddr, 318 NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg); 319 320 /* Enable or disable */ 321 cfg = rvu_read64(rvu, blkaddr, 322 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)); 323 rvu_write64(rvu, blkaddr, 324 NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg); 325 } 326 327 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 328 int blkaddr, int index) 329 { 330 int bank = npc_get_bank(mcam, index); 331 332 index &= (mcam->banksize - 1); 333 return rvu_read64(rvu, blkaddr, 334 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 335 } 336 337 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 338 int nixlf, u64 chan, u8 *mac_addr) 339 { 340 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 341 struct npc_mcam *mcam = &rvu->hw->mcam; 342 struct mcam_entry entry = { {0} }; 343 struct nix_rx_action action; 344 int blkaddr, index, kwi; 345 u64 mac = 0; 346 347 /* AF's VFs work in promiscuous mode */ 348 if (is_afvf(pcifunc)) 349 return; 350 351 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 352 if (blkaddr < 0) 353 return; 354 355 for (index = ETH_ALEN - 1; index >= 0; index--) 356 mac |= ((u64)*mac_addr++) << (8 * index); 357 358 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 359 nixlf, NIXLF_UCAST_ENTRY); 360 361 /* Match ingress channel and DMAC */ 362 entry.kw[0] = chan; 363 entry.kw_mask[0] = 0xFFFULL; 364 365 kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64); 366 entry.kw[kwi] = mac; 367 entry.kw_mask[kwi] = BIT_ULL(48) - 1; 368 369 /* Don't change the action if entry is already enabled 370 * Otherwise RSS action may get overwritten. 371 */ 372 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { 373 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 374 blkaddr, index); 375 } else { 376 *(u64 *)&action = 0x00; 377 action.op = NIX_RX_ACTIONOP_UCAST; 378 action.pf_func = pcifunc; 379 } 380 381 entry.action = *(u64 *)&action; 382 npc_config_mcam_entry(rvu, mcam, blkaddr, index, 383 NIX_INTF_RX, &entry, true); 384 385 /* add VLAN matching, setup action and save entry back for later */ 386 entry.kw[0] |= (NPC_LT_LB_STAG_QINQ | NPC_LT_LB_CTAG) << 20; 387 entry.kw_mask[0] |= (NPC_LT_LB_STAG_QINQ & NPC_LT_LB_CTAG) << 20; 388 389 entry.vtag_action = VTAG0_VALID_BIT | 390 FIELD_PREP(VTAG0_TYPE_MASK, 0) | 391 FIELD_PREP(VTAG0_LID_MASK, NPC_LID_LA) | 392 FIELD_PREP(VTAG0_RELPTR_MASK, 12); 393 394 memcpy(&pfvf->entry, &entry, sizeof(entry)); 395 } 396 397 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 398 int nixlf, u64 chan, bool allmulti) 399 { 400 struct npc_mcam *mcam = &rvu->hw->mcam; 401 int blkaddr, ucast_idx, index, kwi; 402 struct mcam_entry entry = { {0} }; 403 struct nix_rx_action action = { }; 404 405 /* Only PF or AF VF can add a promiscuous entry */ 406 if ((pcifunc & RVU_PFVF_FUNC_MASK) && !is_afvf(pcifunc)) 407 return; 408 409 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 410 if (blkaddr < 0) 411 return; 412 413 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 414 nixlf, NIXLF_PROMISC_ENTRY); 415 416 entry.kw[0] = chan; 417 entry.kw_mask[0] = 0xFFFULL; 418 419 if (allmulti) { 420 kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64); 421 entry.kw[kwi] = BIT_ULL(40); /* LSB bit of 1st byte in DMAC */ 422 entry.kw_mask[kwi] = BIT_ULL(40); 423 } 424 425 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc, 426 nixlf, NIXLF_UCAST_ENTRY); 427 428 /* If the corresponding PF's ucast action is RSS, 429 * use the same action for promisc also 430 */ 431 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx)) 432 *(u64 *)&action = npc_get_mcam_action(rvu, mcam, 433 blkaddr, ucast_idx); 434 435 if (action.op != NIX_RX_ACTIONOP_RSS) { 436 *(u64 *)&action = 0x00; 437 action.op = NIX_RX_ACTIONOP_UCAST; 438 action.pf_func = pcifunc; 439 } 440 441 entry.action = *(u64 *)&action; 442 npc_config_mcam_entry(rvu, mcam, blkaddr, index, 443 NIX_INTF_RX, &entry, true); 444 } 445 446 static void npc_enadis_promisc_entry(struct rvu *rvu, u16 pcifunc, 447 int nixlf, bool enable) 448 { 449 struct npc_mcam *mcam = &rvu->hw->mcam; 450 int blkaddr, index; 451 452 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 453 if (blkaddr < 0) 454 return; 455 456 /* Only PF's have a promiscuous entry */ 457 if (pcifunc & RVU_PFVF_FUNC_MASK) 458 return; 459 460 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 461 nixlf, NIXLF_PROMISC_ENTRY); 462 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 463 } 464 465 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf) 466 { 467 npc_enadis_promisc_entry(rvu, pcifunc, nixlf, false); 468 } 469 470 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf) 471 { 472 npc_enadis_promisc_entry(rvu, pcifunc, nixlf, true); 473 } 474 475 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 476 int nixlf, u64 chan) 477 { 478 struct npc_mcam *mcam = &rvu->hw->mcam; 479 struct mcam_entry entry = { {0} }; 480 struct rvu_hwinfo *hw = rvu->hw; 481 struct nix_rx_action action; 482 struct rvu_pfvf *pfvf; 483 int blkaddr, index; 484 485 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 486 if (blkaddr < 0) 487 return; 488 489 /* Skip LBK VFs */ 490 if (is_afvf(pcifunc)) 491 return; 492 493 /* If pkt replication is not supported, 494 * then only PF is allowed to add a bcast match entry. 495 */ 496 if (!hw->cap.nix_rx_multicast && pcifunc & RVU_PFVF_FUNC_MASK) 497 return; 498 499 /* Get 'pcifunc' of PF device */ 500 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 501 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 502 nixlf, NIXLF_BCAST_ENTRY); 503 504 /* Match ingress channel */ 505 entry.kw[0] = chan; 506 entry.kw_mask[0] = 0xfffull; 507 508 /* Match broadcast MAC address. 509 * DMAC is extracted at 0th bit of PARSE_KEX::KW1 510 */ 511 entry.kw[1] = 0xffffffffffffull; 512 entry.kw_mask[1] = 0xffffffffffffull; 513 514 *(u64 *)&action = 0x00; 515 if (!hw->cap.nix_rx_multicast) { 516 /* Early silicon doesn't support pkt replication, 517 * so install entry with UCAST action, so that PF 518 * receives all broadcast packets. 519 */ 520 action.op = NIX_RX_ACTIONOP_UCAST; 521 action.pf_func = pcifunc; 522 } else { 523 pfvf = rvu_get_pfvf(rvu, pcifunc); 524 action.index = pfvf->bcast_mce_idx; 525 action.op = NIX_RX_ACTIONOP_MCAST; 526 } 527 528 entry.action = *(u64 *)&action; 529 npc_config_mcam_entry(rvu, mcam, blkaddr, index, 530 NIX_INTF_RX, &entry, true); 531 } 532 533 void rvu_npc_disable_bcast_entry(struct rvu *rvu, u16 pcifunc) 534 { 535 struct npc_mcam *mcam = &rvu->hw->mcam; 536 int blkaddr, index; 537 538 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 539 if (blkaddr < 0) 540 return; 541 542 /* Get 'pcifunc' of PF device */ 543 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK; 544 545 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 0, NIXLF_BCAST_ENTRY); 546 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 547 } 548 549 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 550 int group, int alg_idx, int mcam_index) 551 { 552 struct npc_mcam *mcam = &rvu->hw->mcam; 553 struct nix_rx_action action; 554 int blkaddr, index, bank; 555 556 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 557 if (blkaddr < 0) 558 return; 559 560 /* Check if this is for reserved default entry */ 561 if (mcam_index < 0) { 562 if (group != DEFAULT_RSS_CONTEXT_GROUP) 563 return; 564 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 565 nixlf, NIXLF_UCAST_ENTRY); 566 } else { 567 /* TODO: validate this mcam index */ 568 index = mcam_index; 569 } 570 571 if (index >= mcam->total_entries) 572 return; 573 574 bank = npc_get_bank(mcam, index); 575 index &= (mcam->banksize - 1); 576 577 *(u64 *)&action = rvu_read64(rvu, blkaddr, 578 NPC_AF_MCAMEX_BANKX_ACTION(index, bank)); 579 /* Ignore if no action was set earlier */ 580 if (!*(u64 *)&action) 581 return; 582 583 action.op = NIX_RX_ACTIONOP_RSS; 584 action.pf_func = pcifunc; 585 action.index = group; 586 action.flow_key_alg = alg_idx; 587 588 rvu_write64(rvu, blkaddr, 589 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action); 590 591 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 592 nixlf, NIXLF_PROMISC_ENTRY); 593 594 /* If PF's promiscuous entry is enabled, 595 * Set RSS action for that entry as well 596 */ 597 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) { 598 bank = npc_get_bank(mcam, index); 599 index &= (mcam->banksize - 1); 600 601 rvu_write64(rvu, blkaddr, 602 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), 603 *(u64 *)&action); 604 } 605 606 rvu_npc_update_rxvlan(rvu, pcifunc, nixlf); 607 } 608 609 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc, 610 int nixlf, bool enable) 611 { 612 struct npc_mcam *mcam = &rvu->hw->mcam; 613 struct nix_rx_action action; 614 int index, bank, blkaddr; 615 616 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 617 if (blkaddr < 0) 618 return; 619 620 /* Ucast MCAM match entry of this PF/VF */ 621 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 622 nixlf, NIXLF_UCAST_ENTRY); 623 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable); 624 625 /* For PF, ena/dis promisc and bcast MCAM match entries */ 626 if (pcifunc & RVU_PFVF_FUNC_MASK) 627 return; 628 629 /* For bcast, enable/disable only if it's action is not 630 * packet replication, incase if action is replication 631 * then this PF's nixlf is removed from bcast replication 632 * list. 633 */ 634 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 635 nixlf, NIXLF_BCAST_ENTRY); 636 bank = npc_get_bank(mcam, index); 637 *(u64 *)&action = rvu_read64(rvu, blkaddr, 638 NPC_AF_MCAMEX_BANKX_ACTION(index & (mcam->banksize - 1), bank)); 639 if (action.op != NIX_RX_ACTIONOP_MCAST) 640 npc_enable_mcam_entry(rvu, mcam, 641 blkaddr, index, enable); 642 if (enable) 643 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf); 644 else 645 rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf); 646 647 rvu_npc_update_rxvlan(rvu, pcifunc, nixlf); 648 } 649 650 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 651 { 652 npc_enadis_default_entries(rvu, pcifunc, nixlf, false); 653 } 654 655 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 656 { 657 npc_enadis_default_entries(rvu, pcifunc, nixlf, true); 658 } 659 660 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf) 661 { 662 struct npc_mcam *mcam = &rvu->hw->mcam; 663 int blkaddr; 664 665 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 666 if (blkaddr < 0) 667 return; 668 669 mutex_lock(&mcam->lock); 670 671 /* Disable and free all MCAM entries mapped to this 'pcifunc' */ 672 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 673 674 /* Free all MCAM counters mapped to this 'pcifunc' */ 675 npc_mcam_free_all_counters(rvu, mcam, pcifunc); 676 677 mutex_unlock(&mcam->lock); 678 679 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf); 680 } 681 682 #define SET_KEX_LD(intf, lid, ltype, ld, cfg) \ 683 rvu_write64(rvu, blkaddr, \ 684 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg) 685 686 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \ 687 rvu_write64(rvu, blkaddr, \ 688 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg) 689 690 #define KEX_LD_CFG(bytesm1, hdr_ofs, ena, flags_ena, key_ofs) \ 691 (((bytesm1) << 16) | ((hdr_ofs) << 8) | ((ena) << 7) | \ 692 ((flags_ena) << 6) | ((key_ofs) & 0x3F)) 693 694 static void npc_config_ldata_extract(struct rvu *rvu, int blkaddr) 695 { 696 struct npc_mcam *mcam = &rvu->hw->mcam; 697 int lid, ltype; 698 int lid_count; 699 u64 cfg; 700 701 cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 702 lid_count = (cfg >> 4) & 0xF; 703 704 /* First clear any existing config i.e 705 * disable LDATA and FLAGS extraction. 706 */ 707 for (lid = 0; lid < lid_count; lid++) { 708 for (ltype = 0; ltype < 16; ltype++) { 709 SET_KEX_LD(NIX_INTF_RX, lid, ltype, 0, 0ULL); 710 SET_KEX_LD(NIX_INTF_RX, lid, ltype, 1, 0ULL); 711 SET_KEX_LD(NIX_INTF_TX, lid, ltype, 0, 0ULL); 712 SET_KEX_LD(NIX_INTF_TX, lid, ltype, 1, 0ULL); 713 714 SET_KEX_LDFLAGS(NIX_INTF_RX, 0, ltype, 0ULL); 715 SET_KEX_LDFLAGS(NIX_INTF_RX, 1, ltype, 0ULL); 716 SET_KEX_LDFLAGS(NIX_INTF_TX, 0, ltype, 0ULL); 717 SET_KEX_LDFLAGS(NIX_INTF_TX, 1, ltype, 0ULL); 718 } 719 } 720 721 if (mcam->keysize != NPC_MCAM_KEY_X2) 722 return; 723 724 /* Default MCAM KEX profile */ 725 /* Layer A: Ethernet: */ 726 727 /* DMAC: 6 bytes, KW1[47:0] */ 728 cfg = KEX_LD_CFG(0x05, 0x0, 0x1, 0x0, NPC_PARSE_RESULT_DMAC_OFFSET); 729 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LA, NPC_LT_LA_ETHER, 0, cfg); 730 731 /* Ethertype: 2 bytes, KW0[47:32] */ 732 cfg = KEX_LD_CFG(0x01, 0xc, 0x1, 0x0, 0x4); 733 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LA, NPC_LT_LA_ETHER, 1, cfg); 734 735 /* Layer B: Single VLAN (CTAG) */ 736 /* CTAG VLAN[2..3] + Ethertype, 4 bytes, KW0[63:32] */ 737 cfg = KEX_LD_CFG(0x03, 0x0, 0x1, 0x0, 0x4); 738 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LB, NPC_LT_LB_CTAG, 0, cfg); 739 740 /* Layer B: Stacked VLAN (STAG|QinQ) */ 741 /* CTAG VLAN[2..3] + Ethertype, 4 bytes, KW0[63:32] */ 742 cfg = KEX_LD_CFG(0x03, 0x4, 0x1, 0x0, 0x4); 743 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LB, NPC_LT_LB_STAG_QINQ, 0, cfg); 744 745 /* Layer C: IPv4 */ 746 /* SIP+DIP: 8 bytes, KW2[63:0] */ 747 cfg = KEX_LD_CFG(0x07, 0xc, 0x1, 0x0, 0x10); 748 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LC, NPC_LT_LC_IP, 0, cfg); 749 /* TOS: 1 byte, KW1[63:56] */ 750 cfg = KEX_LD_CFG(0x0, 0x1, 0x1, 0x0, 0xf); 751 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LC, NPC_LT_LC_IP, 1, cfg); 752 753 /* Layer D:UDP */ 754 /* SPORT: 2 bytes, KW3[15:0] */ 755 cfg = KEX_LD_CFG(0x1, 0x0, 0x1, 0x0, 0x18); 756 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_UDP, 0, cfg); 757 /* DPORT: 2 bytes, KW3[31:16] */ 758 cfg = KEX_LD_CFG(0x1, 0x2, 0x1, 0x0, 0x1a); 759 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_UDP, 1, cfg); 760 761 /* Layer D:TCP */ 762 /* SPORT: 2 bytes, KW3[15:0] */ 763 cfg = KEX_LD_CFG(0x1, 0x0, 0x1, 0x0, 0x18); 764 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_TCP, 0, cfg); 765 /* DPORT: 2 bytes, KW3[31:16] */ 766 cfg = KEX_LD_CFG(0x1, 0x2, 0x1, 0x0, 0x1a); 767 SET_KEX_LD(NIX_INTF_RX, NPC_LID_LD, NPC_LT_LD_TCP, 1, cfg); 768 } 769 770 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr, 771 struct npc_mcam_kex *mkex) 772 { 773 int lid, lt, ld, fl; 774 775 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX), 776 mkex->keyx_cfg[NIX_INTF_RX]); 777 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX), 778 mkex->keyx_cfg[NIX_INTF_TX]); 779 780 for (ld = 0; ld < NPC_MAX_LD; ld++) 781 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld), 782 mkex->kex_ld_flags[ld]); 783 784 for (lid = 0; lid < NPC_MAX_LID; lid++) { 785 for (lt = 0; lt < NPC_MAX_LT; lt++) { 786 for (ld = 0; ld < NPC_MAX_LD; ld++) { 787 SET_KEX_LD(NIX_INTF_RX, lid, lt, ld, 788 mkex->intf_lid_lt_ld[NIX_INTF_RX] 789 [lid][lt][ld]); 790 791 SET_KEX_LD(NIX_INTF_TX, lid, lt, ld, 792 mkex->intf_lid_lt_ld[NIX_INTF_TX] 793 [lid][lt][ld]); 794 } 795 } 796 } 797 798 for (ld = 0; ld < NPC_MAX_LD; ld++) { 799 for (fl = 0; fl < NPC_MAX_LFL; fl++) { 800 SET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl, 801 mkex->intf_ld_flags[NIX_INTF_RX] 802 [ld][fl]); 803 804 SET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl, 805 mkex->intf_ld_flags[NIX_INTF_TX] 806 [ld][fl]); 807 } 808 } 809 } 810 811 /* strtoull of "mkexprof" with base:36 */ 812 #define MKEX_SIGN 0x19bbfdbd15f 813 #define MKEX_END_SIGN 0xdeadbeef 814 815 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr) 816 { 817 const char *mkex_profile = rvu->mkex_pfl_name; 818 struct device *dev = &rvu->pdev->dev; 819 void __iomem *mkex_prfl_addr = NULL; 820 struct npc_mcam_kex *mcam_kex; 821 u64 prfl_addr; 822 u64 prfl_sz; 823 824 /* If user not selected mkex profile */ 825 if (!strncmp(mkex_profile, "default", MKEX_NAME_LEN)) 826 goto load_default; 827 828 if (cgx_get_mkex_prfl_info(&prfl_addr, &prfl_sz)) 829 goto load_default; 830 831 if (!prfl_addr || !prfl_sz) 832 goto load_default; 833 834 mkex_prfl_addr = ioremap_wc(prfl_addr, prfl_sz); 835 if (!mkex_prfl_addr) 836 goto load_default; 837 838 mcam_kex = (struct npc_mcam_kex *)mkex_prfl_addr; 839 840 while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) { 841 /* Compare with mkex mod_param name string */ 842 if (mcam_kex->mkex_sign == MKEX_SIGN && 843 !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) { 844 /* Due to an errata (35786) in A0/B0 pass silicon, 845 * parse nibble enable configuration has to be 846 * identical for both Rx and Tx interfaces. 847 */ 848 if (is_rvu_96xx_B0(rvu) && 849 mcam_kex->keyx_cfg[NIX_INTF_RX] != 850 mcam_kex->keyx_cfg[NIX_INTF_TX]) 851 goto load_default; 852 853 /* Program selected mkex profile */ 854 npc_program_mkex_profile(rvu, blkaddr, mcam_kex); 855 856 goto unmap; 857 } 858 859 mcam_kex++; 860 prfl_sz -= sizeof(struct npc_mcam_kex); 861 } 862 dev_warn(dev, "Failed to load requested profile: %s\n", 863 rvu->mkex_pfl_name); 864 865 load_default: 866 dev_info(rvu->dev, "Using default mkex profile\n"); 867 /* Config packet data and flags extraction into PARSE result */ 868 npc_config_ldata_extract(rvu, blkaddr); 869 870 unmap: 871 if (mkex_prfl_addr) 872 iounmap(mkex_prfl_addr); 873 } 874 875 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr, 876 struct npc_kpu_profile_action *kpuaction, 877 int kpu, int entry, bool pkind) 878 { 879 struct npc_kpu_action0 action0 = {0}; 880 struct npc_kpu_action1 action1 = {0}; 881 u64 reg; 882 883 action1.errlev = kpuaction->errlev; 884 action1.errcode = kpuaction->errcode; 885 action1.dp0_offset = kpuaction->dp0_offset; 886 action1.dp1_offset = kpuaction->dp1_offset; 887 action1.dp2_offset = kpuaction->dp2_offset; 888 889 if (pkind) 890 reg = NPC_AF_PKINDX_ACTION1(entry); 891 else 892 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry); 893 894 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1); 895 896 action0.byp_count = kpuaction->bypass_count; 897 action0.capture_ena = kpuaction->cap_ena; 898 action0.parse_done = kpuaction->parse_done; 899 action0.next_state = kpuaction->next_state; 900 action0.capture_lid = kpuaction->lid; 901 action0.capture_ltype = kpuaction->ltype; 902 action0.capture_flags = kpuaction->flags; 903 action0.ptr_advance = kpuaction->ptr_advance; 904 action0.var_len_offset = kpuaction->offset; 905 action0.var_len_mask = kpuaction->mask; 906 action0.var_len_right = kpuaction->right; 907 action0.var_len_shift = kpuaction->shift; 908 909 if (pkind) 910 reg = NPC_AF_PKINDX_ACTION0(entry); 911 else 912 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry); 913 914 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0); 915 } 916 917 static void npc_config_kpucam(struct rvu *rvu, int blkaddr, 918 struct npc_kpu_profile_cam *kpucam, 919 int kpu, int entry) 920 { 921 struct npc_kpu_cam cam0 = {0}; 922 struct npc_kpu_cam cam1 = {0}; 923 924 cam1.state = kpucam->state & kpucam->state_mask; 925 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask; 926 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask; 927 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask; 928 929 cam0.state = ~kpucam->state & kpucam->state_mask; 930 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask; 931 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask; 932 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask; 933 934 rvu_write64(rvu, blkaddr, 935 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0); 936 rvu_write64(rvu, blkaddr, 937 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1); 938 } 939 940 static inline u64 enable_mask(int count) 941 { 942 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL)); 943 } 944 945 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu, 946 struct npc_kpu_profile *profile) 947 { 948 int entry, num_entries, max_entries; 949 950 if (profile->cam_entries != profile->action_entries) { 951 dev_err(rvu->dev, 952 "KPU%d: CAM and action entries [%d != %d] not equal\n", 953 kpu, profile->cam_entries, profile->action_entries); 954 } 955 956 max_entries = rvu_read64(rvu, blkaddr, NPC_AF_CONST1) & 0xFFF; 957 958 /* Program CAM match entries for previous KPU extracted data */ 959 num_entries = min_t(int, profile->cam_entries, max_entries); 960 for (entry = 0; entry < num_entries; entry++) 961 npc_config_kpucam(rvu, blkaddr, 962 &profile->cam[entry], kpu, entry); 963 964 /* Program this KPU's actions */ 965 num_entries = min_t(int, profile->action_entries, max_entries); 966 for (entry = 0; entry < num_entries; entry++) 967 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry], 968 kpu, entry, false); 969 970 /* Enable all programmed entries */ 971 num_entries = min_t(int, profile->action_entries, profile->cam_entries); 972 rvu_write64(rvu, blkaddr, 973 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries)); 974 if (num_entries > 64) { 975 rvu_write64(rvu, blkaddr, 976 NPC_AF_KPUX_ENTRY_DISX(kpu, 1), 977 enable_mask(num_entries - 64)); 978 } 979 980 /* Enable this KPU */ 981 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01); 982 } 983 984 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr) 985 { 986 struct rvu_hwinfo *hw = rvu->hw; 987 int num_pkinds, num_kpus, idx; 988 struct npc_pkind *pkind; 989 990 /* Get HW limits */ 991 hw->npc_kpus = (rvu_read64(rvu, blkaddr, NPC_AF_CONST) >> 8) & 0x1F; 992 993 /* Disable all KPUs and their entries */ 994 for (idx = 0; idx < hw->npc_kpus; idx++) { 995 rvu_write64(rvu, blkaddr, 996 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL); 997 rvu_write64(rvu, blkaddr, 998 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL); 999 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00); 1000 } 1001 1002 /* First program IKPU profile i.e PKIND configs. 1003 * Check HW max count to avoid configuring junk or 1004 * writing to unsupported CSR addresses. 1005 */ 1006 pkind = &hw->pkind; 1007 num_pkinds = ARRAY_SIZE(ikpu_action_entries); 1008 num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds); 1009 1010 for (idx = 0; idx < num_pkinds; idx++) 1011 npc_config_kpuaction(rvu, blkaddr, 1012 &ikpu_action_entries[idx], 0, idx, true); 1013 1014 /* Program KPU CAM and Action profiles */ 1015 num_kpus = ARRAY_SIZE(npc_kpu_profiles); 1016 num_kpus = min_t(int, hw->npc_kpus, num_kpus); 1017 1018 for (idx = 0; idx < num_kpus; idx++) 1019 npc_program_kpu_profile(rvu, blkaddr, 1020 idx, &npc_kpu_profiles[idx]); 1021 } 1022 1023 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr) 1024 { 1025 int nixlf_count = rvu_get_nixlf_count(rvu); 1026 struct npc_mcam *mcam = &rvu->hw->mcam; 1027 int rsvd, err; 1028 u64 cfg; 1029 1030 /* Get HW limits */ 1031 cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 1032 mcam->banks = (cfg >> 44) & 0xF; 1033 mcam->banksize = (cfg >> 28) & 0xFFFF; 1034 mcam->counters.max = (cfg >> 48) & 0xFFFF; 1035 1036 /* Actual number of MCAM entries vary by entry size */ 1037 cfg = (rvu_read64(rvu, blkaddr, 1038 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07; 1039 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize; 1040 mcam->keysize = cfg; 1041 1042 /* Number of banks combined per MCAM entry */ 1043 if (cfg == NPC_MCAM_KEY_X4) 1044 mcam->banks_per_entry = 4; 1045 else if (cfg == NPC_MCAM_KEY_X2) 1046 mcam->banks_per_entry = 2; 1047 else 1048 mcam->banks_per_entry = 1; 1049 1050 /* Reserve one MCAM entry for each of the NIX LF to 1051 * guarantee space to install default matching DMAC rule. 1052 * Also reserve 2 MCAM entries for each PF for default 1053 * channel based matching or 'bcast & promisc' matching to 1054 * support BCAST and PROMISC modes of operation for PFs. 1055 * PF0 is excluded. 1056 */ 1057 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) + 1058 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF); 1059 if (mcam->total_entries <= rsvd) { 1060 dev_warn(rvu->dev, 1061 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n", 1062 mcam->total_entries); 1063 return -ENOMEM; 1064 } 1065 1066 mcam->bmap_entries = mcam->total_entries - rsvd; 1067 mcam->nixlf_offset = mcam->bmap_entries; 1068 mcam->pf_offset = mcam->nixlf_offset + nixlf_count; 1069 1070 /* Allocate bitmaps for managing MCAM entries */ 1071 mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries), 1072 sizeof(long), GFP_KERNEL); 1073 if (!mcam->bmap) 1074 return -ENOMEM; 1075 1076 mcam->bmap_reverse = devm_kcalloc(rvu->dev, 1077 BITS_TO_LONGS(mcam->bmap_entries), 1078 sizeof(long), GFP_KERNEL); 1079 if (!mcam->bmap_reverse) 1080 return -ENOMEM; 1081 1082 mcam->bmap_fcnt = mcam->bmap_entries; 1083 1084 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */ 1085 mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, 1086 sizeof(u16), GFP_KERNEL); 1087 if (!mcam->entry2pfvf_map) 1088 return -ENOMEM; 1089 1090 /* Reserve 1/8th of MCAM entries at the bottom for low priority 1091 * allocations and another 1/8th at the top for high priority 1092 * allocations. 1093 */ 1094 mcam->lprio_count = mcam->bmap_entries / 8; 1095 if (mcam->lprio_count > BITS_PER_LONG) 1096 mcam->lprio_count = round_down(mcam->lprio_count, 1097 BITS_PER_LONG); 1098 mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count; 1099 mcam->hprio_count = mcam->lprio_count; 1100 mcam->hprio_end = mcam->hprio_count; 1101 1102 /* Reserve last counter for MCAM RX miss action which is set to 1103 * drop pkt. This way we will know how many pkts didn't match 1104 * any MCAM entry. 1105 */ 1106 mcam->counters.max--; 1107 mcam->rx_miss_act_cntr = mcam->counters.max; 1108 1109 /* Allocate bitmap for managing MCAM counters and memory 1110 * for saving counter to RVU PFFUNC allocation mapping. 1111 */ 1112 err = rvu_alloc_bitmap(&mcam->counters); 1113 if (err) 1114 return err; 1115 1116 mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max, 1117 sizeof(u16), GFP_KERNEL); 1118 if (!mcam->cntr2pfvf_map) 1119 goto free_mem; 1120 1121 /* Alloc memory for MCAM entry to counter mapping and for tracking 1122 * counter's reference count. 1123 */ 1124 mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries, 1125 sizeof(u16), GFP_KERNEL); 1126 if (!mcam->entry2cntr_map) 1127 goto free_mem; 1128 1129 mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max, 1130 sizeof(u16), GFP_KERNEL); 1131 if (!mcam->cntr_refcnt) 1132 goto free_mem; 1133 1134 mutex_init(&mcam->lock); 1135 1136 return 0; 1137 1138 free_mem: 1139 kfree(mcam->counters.bmap); 1140 return -ENOMEM; 1141 } 1142 1143 int rvu_npc_init(struct rvu *rvu) 1144 { 1145 struct npc_pkind *pkind = &rvu->hw->pkind; 1146 struct npc_mcam *mcam = &rvu->hw->mcam; 1147 u64 keyz = NPC_MCAM_KEY_X2; 1148 int blkaddr, entry, bank, err; 1149 u64 cfg, nibble_ena; 1150 1151 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1152 if (blkaddr < 0) { 1153 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__); 1154 return -ENODEV; 1155 } 1156 1157 /* First disable all MCAM entries, to stop traffic towards NIXLFs */ 1158 cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST); 1159 for (bank = 0; bank < ((cfg >> 44) & 0xF); bank++) { 1160 for (entry = 0; entry < ((cfg >> 28) & 0xFFFF); entry++) 1161 rvu_write64(rvu, blkaddr, 1162 NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0); 1163 } 1164 1165 /* Allocate resource bimap for pkind*/ 1166 pkind->rsrc.max = (rvu_read64(rvu, blkaddr, 1167 NPC_AF_CONST1) >> 12) & 0xFF; 1168 err = rvu_alloc_bitmap(&pkind->rsrc); 1169 if (err) 1170 return err; 1171 1172 /* Allocate mem for pkind to PF and channel mapping info */ 1173 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max, 1174 sizeof(u32), GFP_KERNEL); 1175 if (!pkind->pfchan_map) 1176 return -ENOMEM; 1177 1178 /* Configure KPU profile */ 1179 npc_parser_profile_init(rvu, blkaddr); 1180 1181 /* Config Outer L2, IPv4's NPC layer info */ 1182 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2, 1183 (NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F); 1184 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4, 1185 (NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F); 1186 1187 /* Config Inner IPV4 NPC layer info */ 1188 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4, 1189 (NPC_LID_LG << 8) | (NPC_LT_LG_TU_IP << 4) | 0x0F); 1190 1191 /* Enable below for Rx pkts. 1192 * - Outer IPv4 header checksum validation. 1193 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M]. 1194 * - Inner IPv4 header checksum validation. 1195 * - Set non zero checksum error code value 1196 */ 1197 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG, 1198 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) | 1199 BIT_ULL(32) | BIT_ULL(24) | BIT_ULL(6) | 1200 BIT_ULL(2) | BIT_ULL(1)); 1201 1202 /* Set RX and TX side MCAM search key size. 1203 * LA..LD (ltype only) + Channel 1204 */ 1205 nibble_ena = 0x49247; 1206 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX), 1207 ((keyz & 0x3) << 32) | nibble_ena); 1208 /* Due to an errata (35786) in A0 pass silicon, parse nibble enable 1209 * configuration has to be identical for both Rx and Tx interfaces. 1210 */ 1211 if (!is_rvu_96xx_B0(rvu)) 1212 nibble_ena = (1ULL << 19) - 1; 1213 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX), 1214 ((keyz & 0x3) << 32) | nibble_ena); 1215 1216 err = npc_mcam_rsrcs_init(rvu, blkaddr); 1217 if (err) 1218 return err; 1219 1220 /* Configure MKEX profile */ 1221 npc_load_mkex_profile(rvu, blkaddr); 1222 1223 /* Set TX miss action to UCAST_DEFAULT i.e 1224 * transmit the packet on NIX LF SQ's default channel. 1225 */ 1226 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_TX), 1227 NIX_TX_ACTIONOP_UCAST_DEFAULT); 1228 1229 /* If MCAM lookup doesn't result in a match, drop the received packet. 1230 * And map this action to a counter to count dropped pkts. 1231 */ 1232 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_RX), 1233 NIX_RX_ACTIONOP_DROP); 1234 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_STAT_ACT(NIX_INTF_RX), 1235 BIT_ULL(9) | mcam->rx_miss_act_cntr); 1236 1237 return 0; 1238 } 1239 1240 void rvu_npc_freemem(struct rvu *rvu) 1241 { 1242 struct npc_pkind *pkind = &rvu->hw->pkind; 1243 struct npc_mcam *mcam = &rvu->hw->mcam; 1244 1245 kfree(pkind->rsrc.bmap); 1246 kfree(mcam->counters.bmap); 1247 mutex_destroy(&mcam->lock); 1248 } 1249 1250 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 1251 int blkaddr, int *alloc_cnt, 1252 int *enable_cnt) 1253 { 1254 struct npc_mcam *mcam = &rvu->hw->mcam; 1255 int entry; 1256 1257 *alloc_cnt = 0; 1258 *enable_cnt = 0; 1259 1260 for (entry = 0; entry < mcam->bmap_entries; entry++) { 1261 if (mcam->entry2pfvf_map[entry] == pcifunc) { 1262 (*alloc_cnt)++; 1263 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry)) 1264 (*enable_cnt)++; 1265 } 1266 } 1267 } 1268 1269 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 1270 int blkaddr, int *alloc_cnt, 1271 int *enable_cnt) 1272 { 1273 struct npc_mcam *mcam = &rvu->hw->mcam; 1274 int cntr; 1275 1276 *alloc_cnt = 0; 1277 *enable_cnt = 0; 1278 1279 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 1280 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 1281 (*alloc_cnt)++; 1282 if (mcam->cntr_refcnt[cntr]) 1283 (*enable_cnt)++; 1284 } 1285 } 1286 } 1287 1288 static int npc_mcam_verify_entry(struct npc_mcam *mcam, 1289 u16 pcifunc, int entry) 1290 { 1291 /* Verify if entry is valid and if it is indeed 1292 * allocated to the requesting PFFUNC. 1293 */ 1294 if (entry >= mcam->bmap_entries) 1295 return NPC_MCAM_INVALID_REQ; 1296 1297 if (pcifunc != mcam->entry2pfvf_map[entry]) 1298 return NPC_MCAM_PERM_DENIED; 1299 1300 return 0; 1301 } 1302 1303 static int npc_mcam_verify_counter(struct npc_mcam *mcam, 1304 u16 pcifunc, int cntr) 1305 { 1306 /* Verify if counter is valid and if it is indeed 1307 * allocated to the requesting PFFUNC. 1308 */ 1309 if (cntr >= mcam->counters.max) 1310 return NPC_MCAM_INVALID_REQ; 1311 1312 if (pcifunc != mcam->cntr2pfvf_map[cntr]) 1313 return NPC_MCAM_PERM_DENIED; 1314 1315 return 0; 1316 } 1317 1318 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam, 1319 int blkaddr, u16 entry, u16 cntr) 1320 { 1321 u16 index = entry & (mcam->banksize - 1); 1322 u16 bank = npc_get_bank(mcam, entry); 1323 1324 /* Set mapping and increment counter's refcnt */ 1325 mcam->entry2cntr_map[entry] = cntr; 1326 mcam->cntr_refcnt[cntr]++; 1327 /* Enable stats */ 1328 rvu_write64(rvu, blkaddr, 1329 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 1330 BIT_ULL(9) | cntr); 1331 } 1332 1333 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu, 1334 struct npc_mcam *mcam, 1335 int blkaddr, u16 entry, u16 cntr) 1336 { 1337 u16 index = entry & (mcam->banksize - 1); 1338 u16 bank = npc_get_bank(mcam, entry); 1339 1340 /* Remove mapping and reduce counter's refcnt */ 1341 mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP; 1342 mcam->cntr_refcnt[cntr]--; 1343 /* Disable stats */ 1344 rvu_write64(rvu, blkaddr, 1345 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00); 1346 } 1347 1348 /* Sets MCAM entry in bitmap as used. Update 1349 * reverse bitmap too. Should be called with 1350 * 'mcam->lock' held. 1351 */ 1352 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index) 1353 { 1354 u16 entry, rentry; 1355 1356 entry = index; 1357 rentry = mcam->bmap_entries - index - 1; 1358 1359 __set_bit(entry, mcam->bmap); 1360 __set_bit(rentry, mcam->bmap_reverse); 1361 mcam->bmap_fcnt--; 1362 } 1363 1364 /* Sets MCAM entry in bitmap as free. Update 1365 * reverse bitmap too. Should be called with 1366 * 'mcam->lock' held. 1367 */ 1368 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index) 1369 { 1370 u16 entry, rentry; 1371 1372 entry = index; 1373 rentry = mcam->bmap_entries - index - 1; 1374 1375 __clear_bit(entry, mcam->bmap); 1376 __clear_bit(rentry, mcam->bmap_reverse); 1377 mcam->bmap_fcnt++; 1378 } 1379 1380 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam, 1381 int blkaddr, u16 pcifunc) 1382 { 1383 u16 index, cntr; 1384 1385 /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */ 1386 for (index = 0; index < mcam->bmap_entries; index++) { 1387 if (mcam->entry2pfvf_map[index] == pcifunc) { 1388 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP; 1389 /* Free the entry in bitmap */ 1390 npc_mcam_clear_bit(mcam, index); 1391 /* Disable the entry */ 1392 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false); 1393 1394 /* Update entry2counter mapping */ 1395 cntr = mcam->entry2cntr_map[index]; 1396 if (cntr != NPC_MCAM_INVALID_MAP) 1397 npc_unmap_mcam_entry_and_cntr(rvu, mcam, 1398 blkaddr, index, 1399 cntr); 1400 } 1401 } 1402 } 1403 1404 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam, 1405 u16 pcifunc) 1406 { 1407 u16 cntr; 1408 1409 /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */ 1410 for (cntr = 0; cntr < mcam->counters.max; cntr++) { 1411 if (mcam->cntr2pfvf_map[cntr] == pcifunc) { 1412 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP; 1413 mcam->cntr_refcnt[cntr] = 0; 1414 rvu_free_rsrc(&mcam->counters, cntr); 1415 /* This API is expected to be called after freeing 1416 * MCAM entries, which inturn will remove 1417 * 'entry to counter' mapping. 1418 * No need to do it again. 1419 */ 1420 } 1421 } 1422 } 1423 1424 /* Find area of contiguous free entries of size 'nr'. 1425 * If not found return max contiguous free entries available. 1426 */ 1427 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start, 1428 u16 nr, u16 *max_area) 1429 { 1430 u16 max_area_start = 0; 1431 u16 index, next, end; 1432 1433 *max_area = 0; 1434 1435 again: 1436 index = find_next_zero_bit(map, size, start); 1437 if (index >= size) 1438 return max_area_start; 1439 1440 end = ((index + nr) >= size) ? size : index + nr; 1441 next = find_next_bit(map, end, index); 1442 if (*max_area < (next - index)) { 1443 *max_area = next - index; 1444 max_area_start = index; 1445 } 1446 1447 if (next < end) { 1448 start = next + 1; 1449 goto again; 1450 } 1451 1452 return max_area_start; 1453 } 1454 1455 /* Find number of free MCAM entries available 1456 * within range i.e in between 'start' and 'end'. 1457 */ 1458 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end) 1459 { 1460 u16 index, next; 1461 u16 fcnt = 0; 1462 1463 again: 1464 if (start >= end) 1465 return fcnt; 1466 1467 index = find_next_zero_bit(map, end, start); 1468 if (index >= end) 1469 return fcnt; 1470 1471 next = find_next_bit(map, end, index); 1472 if (next <= end) { 1473 fcnt += next - index; 1474 start = next + 1; 1475 goto again; 1476 } 1477 1478 fcnt += end - index; 1479 return fcnt; 1480 } 1481 1482 static void 1483 npc_get_mcam_search_range_priority(struct npc_mcam *mcam, 1484 struct npc_mcam_alloc_entry_req *req, 1485 u16 *start, u16 *end, bool *reverse) 1486 { 1487 u16 fcnt; 1488 1489 if (req->priority == NPC_MCAM_HIGHER_PRIO) 1490 goto hprio; 1491 1492 /* For a low priority entry allocation 1493 * - If reference entry is not in hprio zone then 1494 * search range: ref_entry to end. 1495 * - If reference entry is in hprio zone and if 1496 * request can be accomodated in non-hprio zone then 1497 * search range: 'start of middle zone' to 'end' 1498 * - else search in reverse, so that less number of hprio 1499 * zone entries are allocated. 1500 */ 1501 1502 *reverse = false; 1503 *start = req->ref_entry + 1; 1504 *end = mcam->bmap_entries; 1505 1506 if (req->ref_entry >= mcam->hprio_end) 1507 return; 1508 1509 fcnt = npc_mcam_get_free_count(mcam->bmap, 1510 mcam->hprio_end, mcam->bmap_entries); 1511 if (fcnt > req->count) 1512 *start = mcam->hprio_end; 1513 else 1514 *reverse = true; 1515 return; 1516 1517 hprio: 1518 /* For a high priority entry allocation, search is always 1519 * in reverse to preserve hprio zone entries. 1520 * - If reference entry is not in lprio zone then 1521 * search range: 0 to ref_entry. 1522 * - If reference entry is in lprio zone and if 1523 * request can be accomodated in middle zone then 1524 * search range: 'hprio_end' to 'lprio_start' 1525 */ 1526 1527 *reverse = true; 1528 *start = 0; 1529 *end = req->ref_entry; 1530 1531 if (req->ref_entry <= mcam->lprio_start) 1532 return; 1533 1534 fcnt = npc_mcam_get_free_count(mcam->bmap, 1535 mcam->hprio_end, mcam->lprio_start); 1536 if (fcnt < req->count) 1537 return; 1538 *start = mcam->hprio_end; 1539 *end = mcam->lprio_start; 1540 } 1541 1542 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc, 1543 struct npc_mcam_alloc_entry_req *req, 1544 struct npc_mcam_alloc_entry_rsp *rsp) 1545 { 1546 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; 1547 u16 fcnt, hp_fcnt, lp_fcnt; 1548 u16 start, end, index; 1549 int entry, next_start; 1550 bool reverse = false; 1551 unsigned long *bmap; 1552 u16 max_contig; 1553 1554 mutex_lock(&mcam->lock); 1555 1556 /* Check if there are any free entries */ 1557 if (!mcam->bmap_fcnt) { 1558 mutex_unlock(&mcam->lock); 1559 return NPC_MCAM_ALLOC_FAILED; 1560 } 1561 1562 /* MCAM entries are divided into high priority, middle and 1563 * low priority zones. Idea is to not allocate top and lower 1564 * most entries as much as possible, this is to increase 1565 * probability of honouring priority allocation requests. 1566 * 1567 * Two bitmaps are used for mcam entry management, 1568 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'. 1569 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'. 1570 * 1571 * Reverse bitmap is used to allocate entries 1572 * - when a higher priority entry is requested 1573 * - when available free entries are less. 1574 * Lower priority ones out of avaialble free entries are always 1575 * chosen when 'high vs low' question arises. 1576 */ 1577 1578 /* Get the search range for priority allocation request */ 1579 if (req->priority) { 1580 npc_get_mcam_search_range_priority(mcam, req, 1581 &start, &end, &reverse); 1582 goto alloc; 1583 } 1584 1585 /* Find out the search range for non-priority allocation request 1586 * 1587 * Get MCAM free entry count in middle zone. 1588 */ 1589 lp_fcnt = npc_mcam_get_free_count(mcam->bmap, 1590 mcam->lprio_start, 1591 mcam->bmap_entries); 1592 hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end); 1593 fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt; 1594 1595 /* Check if request can be accomodated in the middle zone */ 1596 if (fcnt > req->count) { 1597 start = mcam->hprio_end; 1598 end = mcam->lprio_start; 1599 } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) { 1600 /* Expand search zone from half of hprio zone to 1601 * half of lprio zone. 1602 */ 1603 start = mcam->hprio_end / 2; 1604 end = mcam->bmap_entries - (mcam->lprio_count / 2); 1605 reverse = true; 1606 } else { 1607 /* Not enough free entries, search all entries in reverse, 1608 * so that low priority ones will get used up. 1609 */ 1610 reverse = true; 1611 start = 0; 1612 end = mcam->bmap_entries; 1613 } 1614 1615 alloc: 1616 if (reverse) { 1617 bmap = mcam->bmap_reverse; 1618 start = mcam->bmap_entries - start; 1619 end = mcam->bmap_entries - end; 1620 index = start; 1621 start = end; 1622 end = index; 1623 } else { 1624 bmap = mcam->bmap; 1625 } 1626 1627 if (req->contig) { 1628 /* Allocate requested number of contiguous entries, if 1629 * unsuccessful find max contiguous entries available. 1630 */ 1631 index = npc_mcam_find_zero_area(bmap, end, start, 1632 req->count, &max_contig); 1633 rsp->count = max_contig; 1634 if (reverse) 1635 rsp->entry = mcam->bmap_entries - index - max_contig; 1636 else 1637 rsp->entry = index; 1638 } else { 1639 /* Allocate requested number of non-contiguous entries, 1640 * if unsuccessful allocate as many as possible. 1641 */ 1642 rsp->count = 0; 1643 next_start = start; 1644 for (entry = 0; entry < req->count; entry++) { 1645 index = find_next_zero_bit(bmap, end, next_start); 1646 if (index >= end) 1647 break; 1648 1649 next_start = start + (index - start) + 1; 1650 1651 /* Save the entry's index */ 1652 if (reverse) 1653 index = mcam->bmap_entries - index - 1; 1654 entry_list[entry] = index; 1655 rsp->count++; 1656 } 1657 } 1658 1659 /* If allocating requested no of entries is unsucessful, 1660 * expand the search range to full bitmap length and retry. 1661 */ 1662 if (!req->priority && (rsp->count < req->count) && 1663 ((end - start) != mcam->bmap_entries)) { 1664 reverse = true; 1665 start = 0; 1666 end = mcam->bmap_entries; 1667 goto alloc; 1668 } 1669 1670 /* For priority entry allocation requests, if allocation is 1671 * failed then expand search to max possible range and retry. 1672 */ 1673 if (req->priority && rsp->count < req->count) { 1674 if (req->priority == NPC_MCAM_LOWER_PRIO && 1675 (start != (req->ref_entry + 1))) { 1676 start = req->ref_entry + 1; 1677 end = mcam->bmap_entries; 1678 reverse = false; 1679 goto alloc; 1680 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) && 1681 ((end - start) != req->ref_entry)) { 1682 start = 0; 1683 end = req->ref_entry; 1684 reverse = true; 1685 goto alloc; 1686 } 1687 } 1688 1689 /* Copy MCAM entry indices into mbox response entry_list. 1690 * Requester always expects indices in ascending order, so 1691 * so reverse the list if reverse bitmap is used for allocation. 1692 */ 1693 if (!req->contig && rsp->count) { 1694 index = 0; 1695 for (entry = rsp->count - 1; entry >= 0; entry--) { 1696 if (reverse) 1697 rsp->entry_list[index++] = entry_list[entry]; 1698 else 1699 rsp->entry_list[entry] = entry_list[entry]; 1700 } 1701 } 1702 1703 /* Mark the allocated entries as used and set nixlf mapping */ 1704 for (entry = 0; entry < rsp->count; entry++) { 1705 index = req->contig ? 1706 (rsp->entry + entry) : rsp->entry_list[entry]; 1707 npc_mcam_set_bit(mcam, index); 1708 mcam->entry2pfvf_map[index] = pcifunc; 1709 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP; 1710 } 1711 1712 /* Update available free count in mbox response */ 1713 rsp->free_count = mcam->bmap_fcnt; 1714 1715 mutex_unlock(&mcam->lock); 1716 return 0; 1717 } 1718 1719 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu, 1720 struct npc_mcam_alloc_entry_req *req, 1721 struct npc_mcam_alloc_entry_rsp *rsp) 1722 { 1723 struct npc_mcam *mcam = &rvu->hw->mcam; 1724 u16 pcifunc = req->hdr.pcifunc; 1725 int blkaddr; 1726 1727 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1728 if (blkaddr < 0) 1729 return NPC_MCAM_INVALID_REQ; 1730 1731 rsp->entry = NPC_MCAM_ENTRY_INVALID; 1732 rsp->free_count = 0; 1733 1734 /* Check if ref_entry is within range */ 1735 if (req->priority && req->ref_entry >= mcam->bmap_entries) 1736 return NPC_MCAM_INVALID_REQ; 1737 1738 /* ref_entry can't be '0' if requested priority is high. 1739 * Can't be last entry if requested priority is low. 1740 */ 1741 if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) || 1742 ((req->ref_entry == (mcam->bmap_entries - 1)) && 1743 req->priority == NPC_MCAM_LOWER_PRIO)) 1744 return NPC_MCAM_INVALID_REQ; 1745 1746 /* Since list of allocated indices needs to be sent to requester, 1747 * max number of non-contiguous entries per mbox msg is limited. 1748 */ 1749 if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES) 1750 return NPC_MCAM_INVALID_REQ; 1751 1752 /* Alloc request from PFFUNC with no NIXLF attached should be denied */ 1753 if (!is_nixlf_attached(rvu, pcifunc)) 1754 return NPC_MCAM_ALLOC_DENIED; 1755 1756 return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp); 1757 } 1758 1759 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu, 1760 struct npc_mcam_free_entry_req *req, 1761 struct msg_rsp *rsp) 1762 { 1763 struct npc_mcam *mcam = &rvu->hw->mcam; 1764 u16 pcifunc = req->hdr.pcifunc; 1765 int blkaddr, rc = 0; 1766 u16 cntr; 1767 1768 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1769 if (blkaddr < 0) 1770 return NPC_MCAM_INVALID_REQ; 1771 1772 /* Free request from PFFUNC with no NIXLF attached, ignore */ 1773 if (!is_nixlf_attached(rvu, pcifunc)) 1774 return NPC_MCAM_INVALID_REQ; 1775 1776 mutex_lock(&mcam->lock); 1777 1778 if (req->all) 1779 goto free_all; 1780 1781 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 1782 if (rc) 1783 goto exit; 1784 1785 mcam->entry2pfvf_map[req->entry] = 0; 1786 npc_mcam_clear_bit(mcam, req->entry); 1787 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 1788 1789 /* Update entry2counter mapping */ 1790 cntr = mcam->entry2cntr_map[req->entry]; 1791 if (cntr != NPC_MCAM_INVALID_MAP) 1792 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 1793 req->entry, cntr); 1794 1795 goto exit; 1796 1797 free_all: 1798 /* Free up all entries allocated to requesting PFFUNC */ 1799 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc); 1800 exit: 1801 mutex_unlock(&mcam->lock); 1802 return rc; 1803 } 1804 1805 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu, 1806 struct npc_mcam_write_entry_req *req, 1807 struct msg_rsp *rsp) 1808 { 1809 struct npc_mcam *mcam = &rvu->hw->mcam; 1810 u16 pcifunc = req->hdr.pcifunc; 1811 int blkaddr, rc; 1812 1813 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1814 if (blkaddr < 0) 1815 return NPC_MCAM_INVALID_REQ; 1816 1817 mutex_lock(&mcam->lock); 1818 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 1819 if (rc) 1820 goto exit; 1821 1822 if (req->set_cntr && 1823 npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) { 1824 rc = NPC_MCAM_INVALID_REQ; 1825 goto exit; 1826 } 1827 1828 if (req->intf != NIX_INTF_RX && req->intf != NIX_INTF_TX) { 1829 rc = NPC_MCAM_INVALID_REQ; 1830 goto exit; 1831 } 1832 1833 npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, req->intf, 1834 &req->entry_data, req->enable_entry); 1835 1836 if (req->set_cntr) 1837 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 1838 req->entry, req->cntr); 1839 1840 rc = 0; 1841 exit: 1842 mutex_unlock(&mcam->lock); 1843 return rc; 1844 } 1845 1846 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu, 1847 struct npc_mcam_ena_dis_entry_req *req, 1848 struct msg_rsp *rsp) 1849 { 1850 struct npc_mcam *mcam = &rvu->hw->mcam; 1851 u16 pcifunc = req->hdr.pcifunc; 1852 int blkaddr, rc; 1853 1854 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1855 if (blkaddr < 0) 1856 return NPC_MCAM_INVALID_REQ; 1857 1858 mutex_lock(&mcam->lock); 1859 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 1860 mutex_unlock(&mcam->lock); 1861 if (rc) 1862 return rc; 1863 1864 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true); 1865 1866 return 0; 1867 } 1868 1869 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu, 1870 struct npc_mcam_ena_dis_entry_req *req, 1871 struct msg_rsp *rsp) 1872 { 1873 struct npc_mcam *mcam = &rvu->hw->mcam; 1874 u16 pcifunc = req->hdr.pcifunc; 1875 int blkaddr, rc; 1876 1877 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1878 if (blkaddr < 0) 1879 return NPC_MCAM_INVALID_REQ; 1880 1881 mutex_lock(&mcam->lock); 1882 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry); 1883 mutex_unlock(&mcam->lock); 1884 if (rc) 1885 return rc; 1886 1887 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false); 1888 1889 return 0; 1890 } 1891 1892 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu, 1893 struct npc_mcam_shift_entry_req *req, 1894 struct npc_mcam_shift_entry_rsp *rsp) 1895 { 1896 struct npc_mcam *mcam = &rvu->hw->mcam; 1897 u16 pcifunc = req->hdr.pcifunc; 1898 u16 old_entry, new_entry; 1899 u16 index, cntr; 1900 int blkaddr, rc; 1901 1902 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1903 if (blkaddr < 0) 1904 return NPC_MCAM_INVALID_REQ; 1905 1906 if (req->shift_count > NPC_MCAM_MAX_SHIFTS) 1907 return NPC_MCAM_INVALID_REQ; 1908 1909 mutex_lock(&mcam->lock); 1910 for (index = 0; index < req->shift_count; index++) { 1911 old_entry = req->curr_entry[index]; 1912 new_entry = req->new_entry[index]; 1913 1914 /* Check if both old and new entries are valid and 1915 * does belong to this PFFUNC or not. 1916 */ 1917 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry); 1918 if (rc) 1919 break; 1920 1921 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry); 1922 if (rc) 1923 break; 1924 1925 /* new_entry should not have a counter mapped */ 1926 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) { 1927 rc = NPC_MCAM_PERM_DENIED; 1928 break; 1929 } 1930 1931 /* Disable the new_entry */ 1932 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false); 1933 1934 /* Copy rule from old entry to new entry */ 1935 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry); 1936 1937 /* Copy counter mapping, if any */ 1938 cntr = mcam->entry2cntr_map[old_entry]; 1939 if (cntr != NPC_MCAM_INVALID_MAP) { 1940 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 1941 old_entry, cntr); 1942 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, 1943 new_entry, cntr); 1944 } 1945 1946 /* Enable new_entry and disable old_entry */ 1947 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true); 1948 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false); 1949 } 1950 1951 /* If shift has failed then report the failed index */ 1952 if (index != req->shift_count) { 1953 rc = NPC_MCAM_PERM_DENIED; 1954 rsp->failed_entry_idx = index; 1955 } 1956 1957 mutex_unlock(&mcam->lock); 1958 return rc; 1959 } 1960 1961 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, 1962 struct npc_mcam_alloc_counter_req *req, 1963 struct npc_mcam_alloc_counter_rsp *rsp) 1964 { 1965 struct npc_mcam *mcam = &rvu->hw->mcam; 1966 u16 pcifunc = req->hdr.pcifunc; 1967 u16 max_contig, cntr; 1968 int blkaddr, index; 1969 1970 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 1971 if (blkaddr < 0) 1972 return NPC_MCAM_INVALID_REQ; 1973 1974 /* If the request is from a PFFUNC with no NIXLF attached, ignore */ 1975 if (!is_nixlf_attached(rvu, pcifunc)) 1976 return NPC_MCAM_INVALID_REQ; 1977 1978 /* Since list of allocated counter IDs needs to be sent to requester, 1979 * max number of non-contiguous counters per mbox msg is limited. 1980 */ 1981 if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) 1982 return NPC_MCAM_INVALID_REQ; 1983 1984 mutex_lock(&mcam->lock); 1985 1986 /* Check if unused counters are available or not */ 1987 if (!rvu_rsrc_free_count(&mcam->counters)) { 1988 mutex_unlock(&mcam->lock); 1989 return NPC_MCAM_ALLOC_FAILED; 1990 } 1991 1992 rsp->count = 0; 1993 1994 if (req->contig) { 1995 /* Allocate requested number of contiguous counters, if 1996 * unsuccessful find max contiguous entries available. 1997 */ 1998 index = npc_mcam_find_zero_area(mcam->counters.bmap, 1999 mcam->counters.max, 0, 2000 req->count, &max_contig); 2001 rsp->count = max_contig; 2002 rsp->cntr = index; 2003 for (cntr = index; cntr < (index + max_contig); cntr++) { 2004 __set_bit(cntr, mcam->counters.bmap); 2005 mcam->cntr2pfvf_map[cntr] = pcifunc; 2006 } 2007 } else { 2008 /* Allocate requested number of non-contiguous counters, 2009 * if unsuccessful allocate as many as possible. 2010 */ 2011 for (cntr = 0; cntr < req->count; cntr++) { 2012 index = rvu_alloc_rsrc(&mcam->counters); 2013 if (index < 0) 2014 break; 2015 rsp->cntr_list[cntr] = index; 2016 rsp->count++; 2017 mcam->cntr2pfvf_map[index] = pcifunc; 2018 } 2019 } 2020 2021 mutex_unlock(&mcam->lock); 2022 return 0; 2023 } 2024 2025 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, 2026 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 2027 { 2028 struct npc_mcam *mcam = &rvu->hw->mcam; 2029 u16 index, entry = 0; 2030 int blkaddr, err; 2031 2032 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2033 if (blkaddr < 0) 2034 return NPC_MCAM_INVALID_REQ; 2035 2036 mutex_lock(&mcam->lock); 2037 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 2038 if (err) { 2039 mutex_unlock(&mcam->lock); 2040 return err; 2041 } 2042 2043 /* Mark counter as free/unused */ 2044 mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP; 2045 rvu_free_rsrc(&mcam->counters, req->cntr); 2046 2047 /* Disable all MCAM entry's stats which are using this counter */ 2048 while (entry < mcam->bmap_entries) { 2049 if (!mcam->cntr_refcnt[req->cntr]) 2050 break; 2051 2052 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 2053 if (index >= mcam->bmap_entries) 2054 break; 2055 if (mcam->entry2cntr_map[index] != req->cntr) 2056 continue; 2057 2058 entry = index + 1; 2059 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2060 index, req->cntr); 2061 } 2062 2063 mutex_unlock(&mcam->lock); 2064 return 0; 2065 } 2066 2067 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, 2068 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp) 2069 { 2070 struct npc_mcam *mcam = &rvu->hw->mcam; 2071 u16 index, entry = 0; 2072 int blkaddr, rc; 2073 2074 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2075 if (blkaddr < 0) 2076 return NPC_MCAM_INVALID_REQ; 2077 2078 mutex_lock(&mcam->lock); 2079 rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 2080 if (rc) 2081 goto exit; 2082 2083 /* Unmap the MCAM entry and counter */ 2084 if (!req->all) { 2085 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry); 2086 if (rc) 2087 goto exit; 2088 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2089 req->entry, req->cntr); 2090 goto exit; 2091 } 2092 2093 /* Disable all MCAM entry's stats which are using this counter */ 2094 while (entry < mcam->bmap_entries) { 2095 if (!mcam->cntr_refcnt[req->cntr]) 2096 break; 2097 2098 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry); 2099 if (index >= mcam->bmap_entries) 2100 break; 2101 if (mcam->entry2cntr_map[index] != req->cntr) 2102 continue; 2103 2104 entry = index + 1; 2105 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr, 2106 index, req->cntr); 2107 } 2108 exit: 2109 mutex_unlock(&mcam->lock); 2110 return rc; 2111 } 2112 2113 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu, 2114 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) 2115 { 2116 struct npc_mcam *mcam = &rvu->hw->mcam; 2117 int blkaddr, err; 2118 2119 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2120 if (blkaddr < 0) 2121 return NPC_MCAM_INVALID_REQ; 2122 2123 mutex_lock(&mcam->lock); 2124 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 2125 mutex_unlock(&mcam->lock); 2126 if (err) 2127 return err; 2128 2129 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00); 2130 2131 return 0; 2132 } 2133 2134 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu, 2135 struct npc_mcam_oper_counter_req *req, 2136 struct npc_mcam_oper_counter_rsp *rsp) 2137 { 2138 struct npc_mcam *mcam = &rvu->hw->mcam; 2139 int blkaddr, err; 2140 2141 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2142 if (blkaddr < 0) 2143 return NPC_MCAM_INVALID_REQ; 2144 2145 mutex_lock(&mcam->lock); 2146 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); 2147 mutex_unlock(&mcam->lock); 2148 if (err) 2149 return err; 2150 2151 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr)); 2152 rsp->stat &= BIT_ULL(48) - 1; 2153 2154 return 0; 2155 } 2156 2157 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu, 2158 struct npc_mcam_alloc_and_write_entry_req *req, 2159 struct npc_mcam_alloc_and_write_entry_rsp *rsp) 2160 { 2161 struct npc_mcam_alloc_counter_req cntr_req; 2162 struct npc_mcam_alloc_counter_rsp cntr_rsp; 2163 struct npc_mcam_alloc_entry_req entry_req; 2164 struct npc_mcam_alloc_entry_rsp entry_rsp; 2165 struct npc_mcam *mcam = &rvu->hw->mcam; 2166 u16 entry = NPC_MCAM_ENTRY_INVALID; 2167 u16 cntr = NPC_MCAM_ENTRY_INVALID; 2168 int blkaddr, rc; 2169 2170 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2171 if (blkaddr < 0) 2172 return NPC_MCAM_INVALID_REQ; 2173 2174 if (req->intf != NIX_INTF_RX && req->intf != NIX_INTF_TX) 2175 return NPC_MCAM_INVALID_REQ; 2176 2177 /* Try to allocate a MCAM entry */ 2178 entry_req.hdr.pcifunc = req->hdr.pcifunc; 2179 entry_req.contig = true; 2180 entry_req.priority = req->priority; 2181 entry_req.ref_entry = req->ref_entry; 2182 entry_req.count = 1; 2183 2184 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, 2185 &entry_req, &entry_rsp); 2186 if (rc) 2187 return rc; 2188 2189 if (!entry_rsp.count) 2190 return NPC_MCAM_ALLOC_FAILED; 2191 2192 entry = entry_rsp.entry; 2193 2194 if (!req->alloc_cntr) 2195 goto write_entry; 2196 2197 /* Now allocate counter */ 2198 cntr_req.hdr.pcifunc = req->hdr.pcifunc; 2199 cntr_req.contig = true; 2200 cntr_req.count = 1; 2201 2202 rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); 2203 if (rc) { 2204 /* Free allocated MCAM entry */ 2205 mutex_lock(&mcam->lock); 2206 mcam->entry2pfvf_map[entry] = 0; 2207 npc_mcam_clear_bit(mcam, entry); 2208 mutex_unlock(&mcam->lock); 2209 return rc; 2210 } 2211 2212 cntr = cntr_rsp.cntr; 2213 2214 write_entry: 2215 mutex_lock(&mcam->lock); 2216 npc_config_mcam_entry(rvu, mcam, blkaddr, entry, req->intf, 2217 &req->entry_data, req->enable_entry); 2218 2219 if (req->alloc_cntr) 2220 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr); 2221 mutex_unlock(&mcam->lock); 2222 2223 rsp->entry = entry; 2224 rsp->cntr = cntr; 2225 2226 return 0; 2227 } 2228 2229 #define GET_KEX_CFG(intf) \ 2230 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) 2231 2232 #define GET_KEX_FLAGS(ld) \ 2233 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld)) 2234 2235 #define GET_KEX_LD(intf, lid, lt, ld) \ 2236 rvu_read64(rvu, BLKADDR_NPC, \ 2237 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld)) 2238 2239 #define GET_KEX_LDFLAGS(intf, ld, fl) \ 2240 rvu_read64(rvu, BLKADDR_NPC, \ 2241 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl)) 2242 2243 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req, 2244 struct npc_get_kex_cfg_rsp *rsp) 2245 { 2246 int lid, lt, ld, fl; 2247 2248 rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX); 2249 rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX); 2250 for (lid = 0; lid < NPC_MAX_LID; lid++) { 2251 for (lt = 0; lt < NPC_MAX_LT; lt++) { 2252 for (ld = 0; ld < NPC_MAX_LD; ld++) { 2253 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] = 2254 GET_KEX_LD(NIX_INTF_RX, lid, lt, ld); 2255 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] = 2256 GET_KEX_LD(NIX_INTF_TX, lid, lt, ld); 2257 } 2258 } 2259 } 2260 for (ld = 0; ld < NPC_MAX_LD; ld++) 2261 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld); 2262 2263 for (ld = 0; ld < NPC_MAX_LD; ld++) { 2264 for (fl = 0; fl < NPC_MAX_LFL; fl++) { 2265 rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] = 2266 GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl); 2267 rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] = 2268 GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl); 2269 } 2270 } 2271 memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN); 2272 return 0; 2273 } 2274 2275 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf) 2276 { 2277 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); 2278 struct npc_mcam *mcam = &rvu->hw->mcam; 2279 int blkaddr, index; 2280 bool enable; 2281 2282 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); 2283 if (blkaddr < 0) 2284 return NIX_AF_ERR_AF_LF_INVALID; 2285 2286 if (!pfvf->rxvlan) 2287 return 0; 2288 2289 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf, 2290 NIXLF_UCAST_ENTRY); 2291 pfvf->entry.action = npc_get_mcam_action(rvu, mcam, blkaddr, index); 2292 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr, index); 2293 npc_config_mcam_entry(rvu, mcam, blkaddr, pfvf->rxvlan_index, 2294 NIX_INTF_RX, &pfvf->entry, enable); 2295 2296 return 0; 2297 } 2298