1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Texas Instruments AM65x Display Subsystem
9
10maintainers:
11  - Jyri Sarha <jsarha@ti.com>
12  - Tomi Valkeinen <tomi.valkeinen@ti.com>
13
14description: |
15  The AM65x TI Keystone Display SubSystem with two output ports and
16  two video planes. The first video port supports OLDI and the second
17  supports DPI format. The fist plane is full video plane with all
18  features and the second is a "lite plane" without scaling support.
19
20properties:
21  compatible:
22    const: ti,am65x-dss
23
24  reg:
25    description:
26      Addresses to each DSS memory region described in the SoC's TRM.
27    items:
28      - description: common DSS register area
29      - description: VIDL1 light video plane
30      - description: VID video plane
31      - description: OVR1 overlay manager for vp1
32      - description: OVR2 overlay manager for vp2
33      - description: VP1 video port 1
34      - description: VP2 video port 2
35
36  reg-names:
37    items:
38      - const: common
39      - const: vidl1
40      - const: vid
41      - const: ovr1
42      - const: ovr2
43      - const: vp1
44      - const: vp2
45
46  clocks:
47    items:
48      - description: fck DSS functional clock
49      - description: vp1 Video Port 1 pixel clock
50      - description: vp2 Video Port 2 pixel clock
51
52  clock-names:
53    items:
54      - const: fck
55      - const: vp1
56      - const: vp2
57
58  interrupts:
59    maxItems: 1
60
61  power-domains:
62    maxItems: 1
63    description: phandle to the associated power domain
64
65  ports:
66    type: object
67    description:
68      Ports as described in Documentation/devicetree/bindings/graph.txt
69    properties:
70      "#address-cells":
71        const: 1
72
73      "#size-cells":
74        const: 0
75
76      port@0:
77        type: object
78        description:
79          The DSS OLDI output port node form video port 1
80
81      port@1:
82        type: object
83        description:
84          The DSS DPI output port node from video port 2
85
86    required:
87      - "#address-cells"
88      - "#size-cells"
89
90  ti,am65x-oldi-io-ctrl:
91    allOf:
92      - $ref: "/schemas/types.yaml#/definitions/phandle-array"
93      - maxItems: 1
94    description:
95      phandle to syscon device node mapping OLDI IO_CTRL registers.
96      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
97      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
98      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
99      interface to work.
100
101  max-memory-bandwidth:
102    $ref: /schemas/types.yaml#/definitions/uint32
103    description:
104      Input memory (from main memory to dispc) bandwidth limit in
105      bytes per second
106
107required:
108  - compatible
109  - reg
110  - reg-names
111  - clocks
112  - clock-names
113  - interrupts
114  - ports
115
116additionalProperties: false
117
118examples:
119  - |
120    #include <dt-bindings/interrupt-controller/arm-gic.h>
121    #include <dt-bindings/interrupt-controller/irq.h>
122    #include <dt-bindings/soc/ti,sci_pm_domain.h>
123
124    dss: dss@4a00000 {
125            compatible = "ti,am65x-dss";
126            reg =   <0x0 0x04a00000 0x0 0x1000>, /* common */
127                    <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
128                    <0x0 0x04a06000 0x0 0x1000>, /* vid */
129                    <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
130                    <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
131                    <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
132                    <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
133            reg-names = "common", "vidl1", "vid",
134                    "ovr1", "ovr2", "vp1", "vp2";
135            ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
136            power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
137            clocks =        <&k3_clks 67 1>,
138                            <&k3_clks 216 1>,
139                            <&k3_clks 67 2>;
140            clock-names = "fck", "vp1", "vp2";
141            interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
142            ports {
143                    #address-cells = <1>;
144                    #size-cells = <0>;
145                    port@0 {
146                            reg = <0>;
147                            oldi_out0: endpoint {
148                                    remote-endpoint = <&lcd_in0>;
149                            };
150                    };
151            };
152    };
153