1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../inc/dmub_srv.h" 27 #include "dmub_reg.h" 28 #include "dmub_dcn20.h" 29 30 #include "dcn/dcn_2_0_0_offset.h" 31 #include "dcn/dcn_2_0_0_sh_mask.h" 32 #include "soc15_hw_ip.h" 33 #include "vega10_ip_offset.h" 34 35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg 36 #define CTX dmub 37 #define REGS dmub->regs 38 39 /* Registers. */ 40 41 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = { 42 #define DMUB_SR(reg) REG_OFFSET(reg), 43 { DMUB_COMMON_REGS() }, 44 #undef DMUB_SR 45 46 #define DMUB_SF(reg, field) FD_MASK(reg, field), 47 { DMUB_COMMON_FIELDS() }, 48 #undef DMUB_SF 49 50 #define DMUB_SF(reg, field) FD_SHIFT(reg, field), 51 { DMUB_COMMON_FIELDS() }, 52 #undef DMUB_SF 53 }; 54 55 /* Shared functions. */ 56 57 static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub, 58 uint64_t *fb_base, 59 uint64_t *fb_offset) 60 { 61 uint32_t tmp; 62 63 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 64 *fb_base = (uint64_t)tmp << 24; 65 66 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 67 *fb_offset = (uint64_t)tmp << 24; 68 } 69 70 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in, 71 uint64_t fb_base, 72 uint64_t fb_offset, 73 union dmub_addr *addr_out) 74 { 75 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 76 } 77 78 void dmub_dcn20_reset(struct dmub_srv *dmub) 79 { 80 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1); 81 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 82 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 83 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 84 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 85 } 86 87 void dmub_dcn20_reset_release(struct dmub_srv *dmub) 88 { 89 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 90 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 91 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 92 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0); 93 } 94 95 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, 96 const struct dmub_window *cw0, 97 const struct dmub_window *cw1) 98 { 99 union dmub_addr offset; 100 uint64_t fb_base, fb_offset; 101 102 dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset); 103 104 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 105 REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3, 106 DMCUB_MEM_WRITE_SPACE, 0x3); 107 108 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 109 110 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 111 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 112 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 113 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 114 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 115 DMCUB_REGION3_CW0_ENABLE, 1); 116 117 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 118 119 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 120 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 121 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 122 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 123 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 124 DMCUB_REGION3_CW1_ENABLE, 1); 125 126 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 127 0x20); 128 } 129 130 void dmub_dcn20_setup_windows(struct dmub_srv *dmub, 131 const struct dmub_window *cw2, 132 const struct dmub_window *cw3, 133 const struct dmub_window *cw4, 134 const struct dmub_window *cw5, 135 const struct dmub_window *cw6) 136 { 137 union dmub_addr offset; 138 uint64_t fb_base, fb_offset; 139 140 dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset); 141 142 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset); 143 144 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); 145 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); 146 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); 147 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0, 148 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, 149 DMCUB_REGION3_CW2_ENABLE, 1); 150 151 dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset); 152 153 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 154 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 155 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 156 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 157 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 158 DMCUB_REGION3_CW3_ENABLE, 1); 159 160 /* TODO: Move this to CW4. */ 161 dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); 162 163 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); 164 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); 165 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS, 166 cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE, 167 1); 168 169 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); 170 171 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 172 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 173 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 174 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 175 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 176 DMCUB_REGION3_CW5_ENABLE, 1); 177 178 dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); 179 180 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 181 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 182 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 183 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 184 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 185 DMCUB_REGION3_CW6_ENABLE, 1); 186 } 187 188 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, 189 const struct dmub_region *inbox1) 190 { 191 /* TODO: Use CW4 instead of region 4. */ 192 193 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000); 194 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 195 } 196 197 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub) 198 { 199 return REG_READ(DMCUB_INBOX1_RPTR); 200 } 201 202 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 203 { 204 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 205 } 206 207 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub) 208 { 209 return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0; 210 } 211 212 bool dmub_dcn20_is_supported(struct dmub_srv *dmub) 213 { 214 uint32_t supported = 0; 215 216 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); 217 218 return supported; 219 } 220