1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called COPYING. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <linuxwifi@intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 * BSD LICENSE 29 * 30 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation. All rights reserved. 31 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 32 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 39 * * Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * * Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in 43 * the documentation and/or other materials provided with the 44 * distribution. 45 * * Neither the name Intel Corporation nor the names of its 46 * contributors may be used to endorse or promote products derived 47 * from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 *****************************************************************************/ 62 63 #ifndef __iwl_fw_api_rx_h__ 64 #define __iwl_fw_api_rx_h__ 65 66 /* API for pre-9000 hardware */ 67 68 #define IWL_RX_INFO_PHY_CNT 8 69 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 70 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 71 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 72 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 73 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 74 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 75 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 76 77 enum iwl_mac_context_info { 78 MAC_CONTEXT_INFO_NONE, 79 MAC_CONTEXT_INFO_GSCAN, 80 }; 81 82 /** 83 * struct iwl_rx_phy_info - phy info 84 * (REPLY_RX_PHY_CMD = 0xc0) 85 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 86 * @cfg_phy_cnt: configurable DSP phy data byte count 87 * @stat_id: configurable DSP phy data set ID 88 * @reserved1: reserved 89 * @system_timestamp: GP2 at on air rise 90 * @timestamp: TSF at on air rise 91 * @beacon_time_stamp: beacon at on-air rise 92 * @phy_flags: general phy flags: band, modulation, ... 93 * @channel: channel number 94 * @non_cfg_phy: for various implementations of non_cfg_phy 95 * @rate_n_flags: RATE_MCS_* 96 * @byte_count: frame's byte-count 97 * @frame_time: frame's time on the air, based on byte count and frame rate 98 * calculation 99 * @mac_active_msk: what MACs were active when the frame was received 100 * @mac_context_info: additional info on the context in which the frame was 101 * received as defined in &enum iwl_mac_context_info 102 * 103 * Before each Rx, the device sends this data. It contains PHY information 104 * about the reception of the packet. 105 */ 106 struct iwl_rx_phy_info { 107 u8 non_cfg_phy_cnt; 108 u8 cfg_phy_cnt; 109 u8 stat_id; 110 u8 reserved1; 111 __le32 system_timestamp; 112 __le64 timestamp; 113 __le32 beacon_time_stamp; 114 __le16 phy_flags; 115 __le16 channel; 116 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 117 __le32 rate_n_flags; 118 __le32 byte_count; 119 u8 mac_active_msk; 120 u8 mac_context_info; 121 __le16 frame_time; 122 } __packed; 123 124 /* 125 * TCP offload Rx assist info 126 * 127 * bits 0:3 - reserved 128 * bits 4:7 - MIC CRC length 129 * bits 8:12 - MAC header length 130 * bit 13 - Padding indication 131 * bit 14 - A-AMSDU indication 132 * bit 15 - Offload enabled 133 */ 134 enum iwl_csum_rx_assist_info { 135 CSUM_RXA_RESERVED_MASK = 0x000f, 136 CSUM_RXA_MICSIZE_MASK = 0x00f0, 137 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 138 CSUM_RXA_PADD = BIT(13), 139 CSUM_RXA_AMSDU = BIT(14), 140 CSUM_RXA_ENA = BIT(15) 141 }; 142 143 /** 144 * struct iwl_rx_mpdu_res_start - phy info 145 * @byte_count: byte count of the frame 146 * @assist: see &enum iwl_csum_rx_assist_info 147 */ 148 struct iwl_rx_mpdu_res_start { 149 __le16 byte_count; 150 __le16 assist; 151 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 152 153 /** 154 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 155 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 156 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 157 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 158 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 159 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 160 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 161 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 162 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 163 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 164 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 165 */ 166 enum iwl_rx_phy_flags { 167 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 168 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 169 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 170 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 171 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 172 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 173 RX_RES_PHY_FLAGS_AGG = BIT(7), 174 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 175 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 176 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 177 }; 178 179 /** 180 * enum iwl_mvm_rx_status - written by fw for each Rx packet 181 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 182 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 183 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 184 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 185 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable 186 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 187 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 188 * in the driver. 189 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 190 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 191 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 192 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 193 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 194 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 195 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 196 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 197 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 198 * algorithm 199 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 200 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 201 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 202 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 203 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP) 204 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done 205 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 206 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 207 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 208 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 209 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 210 */ 211 enum iwl_mvm_rx_status { 212 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 213 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 214 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 215 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 216 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), 217 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 218 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 219 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 220 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 221 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 222 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 223 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 224 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 225 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 226 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 227 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 228 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 229 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 230 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), 231 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), 232 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), 233 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 234 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 235 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 236 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 237 }; 238 239 /* 9000 series API */ 240 enum iwl_rx_mpdu_mac_flags1 { 241 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 242 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 243 /* shift should be 4, but the length is measured in 2-byte 244 * words, so shifting only by 3 gives a byte result 245 */ 246 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 247 }; 248 249 enum iwl_rx_mpdu_mac_flags2 { 250 /* in 2-byte words */ 251 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 252 IWL_RX_MPDU_MFLG2_PAD = 0x20, 253 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 254 }; 255 256 enum iwl_rx_mpdu_amsdu_info { 257 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 258 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 259 }; 260 261 #define RX_MPDU_BAND_POS 6 262 #define RX_MPDU_BAND_MASK 0xC0 263 #define BAND_IN_RX_STATUS(_val) \ 264 (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS) 265 266 enum iwl_rx_l3_proto_values { 267 IWL_RX_L3_TYPE_NONE, 268 IWL_RX_L3_TYPE_IPV4, 269 IWL_RX_L3_TYPE_IPV4_FRAG, 270 IWL_RX_L3_TYPE_IPV6_FRAG, 271 IWL_RX_L3_TYPE_IPV6, 272 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 273 IWL_RX_L3_TYPE_ARP, 274 IWL_RX_L3_TYPE_EAPOL, 275 }; 276 277 #define IWL_RX_L3_PROTO_POS 4 278 279 enum iwl_rx_l3l4_flags { 280 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 281 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 282 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 283 IWL_RX_L3L4_TCP_ACK = BIT(3), 284 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 285 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 286 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 287 }; 288 289 enum iwl_rx_mpdu_status { 290 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 291 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 292 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 293 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 294 IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4), 295 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 296 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 297 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 298 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 299 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 300 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 301 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 302 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 303 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 304 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 305 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 306 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 307 IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12), 308 IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13), 309 IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14), 310 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 311 }; 312 313 enum iwl_rx_mpdu_hash_filter { 314 IWL_RX_MPDU_HF_A1_HASH_MASK = 0x3f, 315 IWL_RX_MPDU_HF_FILTER_STATUS_MASK = 0xc0, 316 }; 317 318 enum iwl_rx_mpdu_sta_id_flags { 319 IWL_RX_MPDU_SIF_STA_ID_MASK = 0x1f, 320 IWL_RX_MPDU_SIF_RRF_ABORT = 0x20, 321 IWL_RX_MPDU_SIF_FILTER_STATUS_MASK = 0xc0, 322 }; 323 324 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 325 326 enum iwl_rx_mpdu_reorder_data { 327 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 328 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 329 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 330 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 331 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 332 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 333 }; 334 335 enum iwl_rx_mpdu_phy_info { 336 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 337 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 338 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 339 /* short preamble is only for CCK, for non-CCK overridden by this */ 340 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 341 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 342 }; 343 344 enum iwl_rx_mpdu_mac_info { 345 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 346 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 347 }; 348 349 /* TSF overload low dword */ 350 enum iwl_rx_phy_data0 { 351 /* info type: HE any */ 352 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 353 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 354 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 355 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 356 /* 1 bit reserved */ 357 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 358 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 359 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 360 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 361 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 362 /* 6 bits reserved */ 363 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 364 }; 365 366 enum iwl_rx_phy_info_type { 367 IWL_RX_PHY_INFO_TYPE_NONE = 0, 368 IWL_RX_PHY_INFO_TYPE_CCK = 1, 369 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 370 IWL_RX_PHY_INFO_TYPE_HT = 3, 371 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 372 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 373 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 374 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 375 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 376 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 377 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 378 }; 379 380 /* TSF overload high dword */ 381 enum iwl_rx_phy_data1 { 382 /* 383 * check this first - if TSF overload is set, 384 * see &enum iwl_rx_phy_info_type 385 */ 386 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 387 388 /* info type: HT/VHT/HE any */ 389 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 390 391 /* info type: HE MU/MU-EXT */ 392 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 393 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 394 395 /* info type: HE any */ 396 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 397 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 398 /* trigger encoded */ 399 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 400 401 /* info type: HE TB/TX-EXT */ 402 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 403 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 404 }; 405 406 /* goes into Metadata DW 7 */ 407 enum iwl_rx_phy_data2 { 408 /* info type: HE MU-EXT */ 409 /* the a1/a2/... is what the PHY/firmware calls the values */ 410 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 411 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 412 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 413 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 414 415 /* info type: HE TB-EXT */ 416 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 417 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 418 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 419 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 420 }; 421 422 /* goes into Metadata DW 8 */ 423 enum iwl_rx_phy_data3 { 424 /* info type: HE MU-EXT */ 425 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 426 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 427 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 428 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 429 }; 430 431 /* goes into Metadata DW 4 high 16 bits */ 432 enum iwl_rx_phy_data4 { 433 /* info type: HE MU-EXT */ 434 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 435 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 436 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 437 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 438 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 439 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 440 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 441 }; 442 443 /** 444 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 445 */ 446 struct iwl_rx_mpdu_desc_v1 { 447 /* DW7 - carries rss_hash only when rpa_en == 1 */ 448 union { 449 /** 450 * @rss_hash: RSS hash value 451 */ 452 __le32 rss_hash; 453 454 /** 455 * @phy_data2: depends on info type (see @phy_data1) 456 */ 457 __le32 phy_data2; 458 }; 459 460 /* DW8 - carries filter_match only when rpa_en == 1 */ 461 union { 462 /** 463 * @filter_match: filter match value 464 */ 465 __le32 filter_match; 466 467 /** 468 * @phy_data3: depends on info type (see @phy_data1) 469 */ 470 __le32 phy_data3; 471 }; 472 473 /* DW9 */ 474 /** 475 * @rate_n_flags: RX rate/flags encoding 476 */ 477 __le32 rate_n_flags; 478 /* DW10 */ 479 /** 480 * @energy_a: energy chain A 481 */ 482 u8 energy_a; 483 /** 484 * @energy_b: energy chain B 485 */ 486 u8 energy_b; 487 /** 488 * @channel: channel number 489 */ 490 u8 channel; 491 /** 492 * @mac_context: MAC context mask 493 */ 494 u8 mac_context; 495 /* DW11 */ 496 /** 497 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 498 */ 499 __le32 gp2_on_air_rise; 500 /* DW12 & DW13 */ 501 union { 502 /** 503 * @tsf_on_air_rise: 504 * TSF value on air rise (INA), only valid if 505 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 506 */ 507 __le64 tsf_on_air_rise; 508 509 struct { 510 /** 511 * @phy_data0: depends on info_type, see @phy_data1 512 */ 513 __le32 phy_data0; 514 /** 515 * @phy_data1: valid only if 516 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 517 * see &enum iwl_rx_phy_data1. 518 */ 519 __le32 phy_data1; 520 }; 521 }; 522 } __packed; 523 524 /** 525 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 526 */ 527 struct iwl_rx_mpdu_desc_v3 { 528 /* DW7 - carries filter_match only when rpa_en == 1 */ 529 union { 530 /** 531 * @filter_match: filter match value 532 */ 533 __le32 filter_match; 534 535 /** 536 * @phy_data3: depends on info type (see @phy_data1) 537 */ 538 __le32 phy_data3; 539 }; 540 541 /* DW8 - carries rss_hash only when rpa_en == 1 */ 542 union { 543 /** 544 * @rss_hash: RSS hash value 545 */ 546 __le32 rss_hash; 547 548 /** 549 * @phy_data2: depends on info type (see @phy_data1) 550 */ 551 __le32 phy_data2; 552 }; 553 /* DW9 */ 554 /** 555 * @partial_hash: 31:0 ip/tcp header hash 556 * w/o some fields (such as IP SRC addr) 557 */ 558 __le32 partial_hash; 559 /* DW10 */ 560 /** 561 * @raw_xsum: raw xsum value 562 */ 563 __le32 raw_xsum; 564 /* DW11 */ 565 /** 566 * @rate_n_flags: RX rate/flags encoding 567 */ 568 __le32 rate_n_flags; 569 /* DW12 */ 570 /** 571 * @energy_a: energy chain A 572 */ 573 u8 energy_a; 574 /** 575 * @energy_b: energy chain B 576 */ 577 u8 energy_b; 578 /** 579 * @channel: channel number 580 */ 581 u8 channel; 582 /** 583 * @mac_context: MAC context mask 584 */ 585 u8 mac_context; 586 /* DW13 */ 587 /** 588 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 589 */ 590 __le32 gp2_on_air_rise; 591 /* DW14 & DW15 */ 592 union { 593 /** 594 * @tsf_on_air_rise: 595 * TSF value on air rise (INA), only valid if 596 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 597 */ 598 __le64 tsf_on_air_rise; 599 600 struct { 601 /** 602 * @phy_data0: depends on info_type, see @phy_data1 603 */ 604 __le32 phy_data0; 605 /** 606 * @phy_data1: valid only if 607 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 608 * see &enum iwl_rx_phy_data1. 609 */ 610 __le32 phy_data1; 611 }; 612 }; 613 /* DW16 & DW17 */ 614 /** 615 * @reserved: reserved 616 */ 617 __le32 reserved[2]; 618 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 619 620 /** 621 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 622 */ 623 struct iwl_rx_mpdu_desc { 624 /* DW2 */ 625 /** 626 * @mpdu_len: MPDU length 627 */ 628 __le16 mpdu_len; 629 /** 630 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 631 */ 632 u8 mac_flags1; 633 /** 634 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 635 */ 636 u8 mac_flags2; 637 /* DW3 */ 638 /** 639 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 640 */ 641 u8 amsdu_info; 642 /** 643 * @phy_info: &enum iwl_rx_mpdu_phy_info 644 */ 645 __le16 phy_info; 646 /** 647 * @mac_phy_idx: MAC/PHY index 648 */ 649 u8 mac_phy_idx; 650 /* DW4 - carries csum data only when rpa_en == 1 */ 651 /** 652 * @raw_csum: raw checksum (alledgedly unreliable) 653 */ 654 __le16 raw_csum; 655 656 union { 657 /** 658 * @l3l4_flags: &enum iwl_rx_l3l4_flags 659 */ 660 __le16 l3l4_flags; 661 662 /** 663 * @phy_data4: depends on info type, see phy_data1 664 */ 665 __le16 phy_data4; 666 }; 667 /* DW5 */ 668 /** 669 * @status: &enum iwl_rx_mpdu_status 670 */ 671 __le16 status; 672 /** 673 * @hash_filter: hash filter value 674 */ 675 u8 hash_filter; 676 /** 677 * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags 678 */ 679 u8 sta_id_flags; 680 /* DW6 */ 681 /** 682 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 683 */ 684 __le32 reorder_data; 685 686 union { 687 struct iwl_rx_mpdu_desc_v1 v1; 688 struct iwl_rx_mpdu_desc_v3 v3; 689 }; 690 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 691 692 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 693 694 #define RX_NO_DATA_CHAIN_A_POS 0 695 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 696 #define RX_NO_DATA_CHAIN_B_POS 8 697 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 698 #define RX_NO_DATA_CHANNEL_POS 16 699 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 700 701 #define RX_NO_DATA_INFO_TYPE_POS 0 702 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 703 #define RX_NO_DATA_INFO_TYPE_NONE 0 704 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 705 #define RX_NO_DATA_INFO_TYPE_NDP 2 706 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 707 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED 4 708 709 #define RX_NO_DATA_INFO_ERR_POS 8 710 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 711 #define RX_NO_DATA_INFO_ERR_NONE 0 712 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 713 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 714 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 715 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 716 717 #define RX_NO_DATA_FRAME_TIME_POS 0 718 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 719 720 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 721 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 722 723 /** 724 * struct iwl_rx_no_data - RX no data descriptor 725 * @info: 7:0 frame type, 15:8 RX error type 726 * @rssi: 7:0 energy chain-A, 727 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 728 * @on_air_rise_time: GP2 during on air rise 729 * @fr_time: frame time 730 * @rate: rate/mcs of frame 731 * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type 732 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 733 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 734 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 735 */ 736 struct iwl_rx_no_data { 737 __le32 info; 738 __le32 rssi; 739 __le32 on_air_rise_time; 740 __le32 fr_time; 741 __le32 rate; 742 __le32 phy_info[2]; 743 __le32 rx_vec[2]; 744 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */ 745 746 struct iwl_frame_release { 747 u8 baid; 748 u8 reserved; 749 __le16 nssn; 750 }; 751 752 /** 753 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 754 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 755 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 756 */ 757 enum iwl_bar_frame_release_sta_tid { 758 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 759 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 760 }; 761 762 /** 763 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 764 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 765 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 766 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 767 */ 768 enum iwl_bar_frame_release_ba_info { 769 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 770 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 771 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 772 }; 773 774 /** 775 * struct iwl_bar_frame_release - frame release from BAR info 776 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 777 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 778 */ 779 struct iwl_bar_frame_release { 780 __le32 sta_tid; 781 __le32 ba_info; 782 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 783 784 enum iwl_rss_hash_func_en { 785 IWL_RSS_HASH_TYPE_IPV4_TCP, 786 IWL_RSS_HASH_TYPE_IPV4_UDP, 787 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 788 IWL_RSS_HASH_TYPE_IPV6_TCP, 789 IWL_RSS_HASH_TYPE_IPV6_UDP, 790 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 791 }; 792 793 #define IWL_RSS_HASH_KEY_CNT 10 794 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 795 #define IWL_RSS_ENABLE 1 796 797 /** 798 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 799 * 800 * @flags: 1 - enable, 0 - disable 801 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 802 * @reserved: reserved 803 * @secret_key: 320 bit input of random key configuration from driver 804 * @indirection_table: indirection table 805 */ 806 struct iwl_rss_config_cmd { 807 __le32 flags; 808 u8 hash_mask; 809 u8 reserved[3]; 810 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 811 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 812 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 813 814 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 815 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 816 817 /** 818 * struct iwl_rxq_sync_cmd - RXQ notification trigger 819 * 820 * @flags: flags of the notification. bit 0:3 are the sender queue 821 * @rxq_mask: rx queues to send the notification on 822 * @count: number of bytes in payload, should be DWORD aligned 823 * @payload: data to send to rx queues 824 */ 825 struct iwl_rxq_sync_cmd { 826 __le32 flags; 827 __le32 rxq_mask; 828 __le32 count; 829 u8 payload[]; 830 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 831 832 /** 833 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 834 * sync command 835 * 836 * @count: number of bytes in payload 837 * @payload: data to send to rx queues 838 */ 839 struct iwl_rxq_sync_notification { 840 __le32 count; 841 u8 payload[]; 842 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 843 844 /** 845 * enum iwl_mvm_rxq_notif_type - Internal message identifier 846 * 847 * @IWL_MVM_RXQ_EMPTY: empty sync notification 848 * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA 849 * @IWL_MVM_RXQ_NSSN_SYNC: notify all the RSS queues with the new NSSN 850 */ 851 enum iwl_mvm_rxq_notif_type { 852 IWL_MVM_RXQ_EMPTY, 853 IWL_MVM_RXQ_NOTIF_DEL_BA, 854 IWL_MVM_RXQ_NSSN_SYNC, 855 }; 856 857 /** 858 * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent 859 * in &iwl_rxq_sync_cmd. Should be DWORD aligned. 860 * FW is agnostic to the payload, so there are no endianity requirements. 861 * 862 * @type: value from &iwl_mvm_rxq_notif_type 863 * @sync: ctrl path is waiting for all notifications to be received 864 * @cookie: internal cookie to identify old notifications 865 * @data: payload 866 */ 867 struct iwl_mvm_internal_rxq_notif { 868 u16 type; 869 u16 sync; 870 u32 cookie; 871 u8 data[]; 872 } __packed; 873 874 /** 875 * enum iwl_mvm_pm_event - type of station PM event 876 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 877 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 878 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 879 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 880 */ 881 enum iwl_mvm_pm_event { 882 IWL_MVM_PM_EVENT_AWAKE, 883 IWL_MVM_PM_EVENT_ASLEEP, 884 IWL_MVM_PM_EVENT_UAPSD, 885 IWL_MVM_PM_EVENT_PS_POLL, 886 }; /* PEER_PM_NTFY_API_E_VER_1 */ 887 888 /** 889 * struct iwl_mvm_pm_state_notification - station PM state notification 890 * @sta_id: station ID of the station changing state 891 * @type: the new powersave state, see &enum iwl_mvm_pm_event 892 */ 893 struct iwl_mvm_pm_state_notification { 894 u8 sta_id; 895 u8 type; 896 /* private: */ 897 __le16 reserved; 898 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 899 900 #define BA_WINDOW_STREAMS_MAX 16 901 #define BA_WINDOW_STATUS_TID_MSK 0x000F 902 #define BA_WINDOW_STATUS_STA_ID_POS 4 903 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 904 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 905 906 /** 907 * struct iwl_ba_window_status_notif - reordering window's status notification 908 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 909 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 910 * @start_seq_num: the start sequence number of the bitmap 911 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 912 */ 913 struct iwl_ba_window_status_notif { 914 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 915 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 916 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 917 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 918 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 919 920 /** 921 * struct iwl_rfh_queue_config - RX queue configuration 922 * @q_num: Q num 923 * @enable: enable queue 924 * @reserved: alignment 925 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 926 * @fr_bd_cb: DMA address of freeRB table 927 * @ur_bd_cb: DMA address of used RB table 928 * @fr_bd_wid: Initial index of the free table 929 */ 930 struct iwl_rfh_queue_data { 931 u8 q_num; 932 u8 enable; 933 __le16 reserved; 934 __le64 urbd_stts_wrptr; 935 __le64 fr_bd_cb; 936 __le64 ur_bd_cb; 937 __le32 fr_bd_wid; 938 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 939 940 /** 941 * struct iwl_rfh_queue_config - RX queue configuration 942 * @num_queues: number of queues configured 943 * @reserved: alignment 944 * @data: DMA addresses per-queue 945 */ 946 struct iwl_rfh_queue_config { 947 u8 num_queues; 948 u8 reserved[3]; 949 struct iwl_rfh_queue_data data[]; 950 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 951 952 #endif /* __iwl_fw_api_rx_h__ */ 953