1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 soc: soc { 14 #address-cells = <0x1>; 15 #size-cells = <0x1>; 16 ranges = <0 0 0 0xffffffff>; 17 compatible = "simple-bus"; 18 19 tlmm: pinctrl@1000000 { 20 compatible = "qcom,ipq8074-pinctrl"; 21 reg = <0x1000000 0x300000>; 22 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 23 gpio-controller; 24 gpio-ranges = <&tlmm 0 0 70>; 25 #gpio-cells = <0x2>; 26 interrupt-controller; 27 #interrupt-cells = <0x2>; 28 29 serial_4_pins: serial4-pinmux { 30 pins = "gpio23", "gpio24"; 31 function = "blsp4_uart1"; 32 drive-strength = <8>; 33 bias-disable; 34 }; 35 36 i2c_0_pins: i2c-0-pinmux { 37 pins = "gpio42", "gpio43"; 38 function = "blsp1_i2c"; 39 drive-strength = <8>; 40 bias-disable; 41 }; 42 43 spi_0_pins: spi-0-pins { 44 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 45 function = "blsp0_spi"; 46 drive-strength = <8>; 47 bias-disable; 48 }; 49 50 hsuart_pins: hsuart-pins { 51 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 52 function = "blsp2_uart"; 53 drive-strength = <8>; 54 bias-disable; 55 }; 56 57 qpic_pins: qpic-pins { 58 pins = "gpio1", "gpio3", "gpio4", 59 "gpio5", "gpio6", "gpio7", 60 "gpio8", "gpio10", "gpio11", 61 "gpio12", "gpio13", "gpio14", 62 "gpio15", "gpio16", "gpio17"; 63 function = "qpic"; 64 drive-strength = <8>; 65 bias-disable; 66 }; 67 }; 68 69 intc: interrupt-controller@b000000 { 70 compatible = "qcom,msm-qgic2"; 71 interrupt-controller; 72 #interrupt-cells = <0x3>; 73 reg = <0xb000000 0x1000>, <0xb002000 0x1000>; 74 }; 75 76 timer { 77 compatible = "arm,armv8-timer"; 78 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 80 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 82 }; 83 84 timer@b120000 { 85 #address-cells = <1>; 86 #size-cells = <1>; 87 ranges; 88 compatible = "arm,armv7-timer-mem"; 89 reg = <0xb120000 0x1000>; 90 clock-frequency = <19200000>; 91 92 frame@b120000 { 93 frame-number = <0>; 94 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 96 reg = <0xb121000 0x1000>, 97 <0xb122000 0x1000>; 98 }; 99 100 frame@b123000 { 101 frame-number = <1>; 102 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 103 reg = <0xb123000 0x1000>; 104 status = "disabled"; 105 }; 106 107 frame@b124000 { 108 frame-number = <2>; 109 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 110 reg = <0xb124000 0x1000>; 111 status = "disabled"; 112 }; 113 114 frame@b125000 { 115 frame-number = <3>; 116 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 117 reg = <0xb125000 0x1000>; 118 status = "disabled"; 119 }; 120 121 frame@b126000 { 122 frame-number = <4>; 123 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 124 reg = <0xb126000 0x1000>; 125 status = "disabled"; 126 }; 127 128 frame@b127000 { 129 frame-number = <5>; 130 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 131 reg = <0xb127000 0x1000>; 132 status = "disabled"; 133 }; 134 135 frame@b128000 { 136 frame-number = <6>; 137 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 138 reg = <0xb128000 0x1000>; 139 status = "disabled"; 140 }; 141 }; 142 143 gcc: gcc@1800000 { 144 compatible = "qcom,gcc-ipq8074"; 145 reg = <0x1800000 0x80000>; 146 #clock-cells = <0x1>; 147 #reset-cells = <0x1>; 148 }; 149 150 blsp1_uart5: serial@78b3000 { 151 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 152 reg = <0x78b3000 0x200>; 153 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 155 <&gcc GCC_BLSP1_AHB_CLK>; 156 clock-names = "core", "iface"; 157 pinctrl-0 = <&serial_4_pins>; 158 pinctrl-names = "default"; 159 status = "disabled"; 160 }; 161 162 blsp_dma: dma@7884000 { 163 compatible = "qcom,bam-v1.7.0"; 164 reg = <0x7884000 0x2b000>; 165 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 167 clock-names = "bam_clk"; 168 #dma-cells = <1>; 169 qcom,ee = <0>; 170 }; 171 172 blsp1_uart1: serial@78af000 { 173 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 174 reg = <0x78af000 0x200>; 175 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 177 <&gcc GCC_BLSP1_AHB_CLK>; 178 clock-names = "core", "iface"; 179 status = "disabled"; 180 }; 181 182 blsp1_uart3: serial@78b1000 { 183 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 184 reg = <0x78b1000 0x200>; 185 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 187 <&gcc GCC_BLSP1_AHB_CLK>; 188 clock-names = "core", "iface"; 189 dmas = <&blsp_dma 4>, 190 <&blsp_dma 5>; 191 dma-names = "tx", "rx"; 192 pinctrl-0 = <&hsuart_pins>; 193 pinctrl-names = "default"; 194 status = "disabled"; 195 }; 196 197 blsp1_spi1: spi@78b5000 { 198 compatible = "qcom,spi-qup-v2.2.1"; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 reg = <0x78b5000 0x600>; 202 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 203 spi-max-frequency = <50000000>; 204 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 205 <&gcc GCC_BLSP1_AHB_CLK>; 206 clock-names = "core", "iface"; 207 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 208 dma-names = "tx", "rx"; 209 pinctrl-0 = <&spi_0_pins>; 210 pinctrl-names = "default"; 211 status = "disabled"; 212 }; 213 214 blsp1_i2c2: i2c@78b6000 { 215 compatible = "qcom,i2c-qup-v2.2.1"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 reg = <0x78b6000 0x600>; 219 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 221 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 222 clock-names = "iface", "core"; 223 clock-frequency = <400000>; 224 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 225 dma-names = "rx", "tx"; 226 pinctrl-0 = <&i2c_0_pins>; 227 pinctrl-names = "default"; 228 status = "disabled"; 229 }; 230 231 blsp1_i2c3: i2c@78b7000 { 232 compatible = "qcom,i2c-qup-v2.2.1"; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0x78b7000 0x600>; 236 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 238 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 239 clock-names = "iface", "core"; 240 clock-frequency = <100000>; 241 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 242 dma-names = "rx", "tx"; 243 status = "disabled"; 244 }; 245 246 qpic_bam: dma@7984000 { 247 compatible = "qcom,bam-v1.7.0"; 248 reg = <0x7984000 0x1a000>; 249 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&gcc GCC_QPIC_AHB_CLK>; 251 clock-names = "bam_clk"; 252 #dma-cells = <1>; 253 qcom,ee = <0>; 254 status = "disabled"; 255 }; 256 257 qpic_nand: nand@79b0000 { 258 compatible = "qcom,ipq8074-nand"; 259 reg = <0x79b0000 0x10000>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 clocks = <&gcc GCC_QPIC_CLK>, 263 <&gcc GCC_QPIC_AHB_CLK>; 264 clock-names = "core", "aon"; 265 266 dmas = <&qpic_bam 0>, 267 <&qpic_bam 1>, 268 <&qpic_bam 2>; 269 dma-names = "tx", "rx", "cmd"; 270 pinctrl-0 = <&qpic_pins>; 271 pinctrl-names = "default"; 272 status = "disabled"; 273 }; 274 275 pcie_phy0: phy@86000 { 276 compatible = "qcom,ipq8074-qmp-pcie-phy"; 277 reg = <0x86000 0x1000>; 278 #phy-cells = <0>; 279 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 280 clock-names = "pipe_clk"; 281 clock-output-names = "pcie20_phy0_pipe_clk"; 282 283 resets = <&gcc GCC_PCIE0_PHY_BCR>, 284 <&gcc GCC_PCIE0PHY_PHY_BCR>; 285 reset-names = "phy", 286 "common"; 287 status = "disabled"; 288 }; 289 290 pcie0: pci@20000000 { 291 compatible = "qcom,pcie-ipq8074"; 292 reg = <0x20000000 0xf1d 293 0x20000f20 0xa8 294 0x80000 0x2000 295 0x20100000 0x1000>; 296 reg-names = "dbi", "elbi", "parf", "config"; 297 device_type = "pci"; 298 linux,pci-domain = <0>; 299 bus-range = <0x00 0xff>; 300 num-lanes = <1>; 301 #address-cells = <3>; 302 #size-cells = <2>; 303 304 phys = <&pcie_phy0>; 305 phy-names = "pciephy"; 306 307 ranges = <0x81000000 0 0x20200000 0x20200000 308 0 0x100000 /* downstream I/O */ 309 0x82000000 0 0x20300000 0x20300000 310 0 0xd00000>; /* non-prefetchable memory */ 311 312 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-names = "msi"; 314 #interrupt-cells = <1>; 315 interrupt-map-mask = <0 0 0 0x7>; 316 interrupt-map = <0 0 0 1 &intc 0 75 317 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 318 <0 0 0 2 &intc 0 78 319 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 320 <0 0 0 3 &intc 0 79 321 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 322 <0 0 0 4 &intc 0 83 323 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 324 325 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 326 <&gcc GCC_PCIE0_AXI_M_CLK>, 327 <&gcc GCC_PCIE0_AXI_S_CLK>, 328 <&gcc GCC_PCIE0_AHB_CLK>, 329 <&gcc GCC_PCIE0_AUX_CLK>; 330 331 clock-names = "iface", 332 "axi_m", 333 "axi_s", 334 "ahb", 335 "aux"; 336 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 337 <&gcc GCC_PCIE0_SLEEP_ARES>, 338 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 339 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 340 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 341 <&gcc GCC_PCIE0_AHB_ARES>, 342 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; 343 reset-names = "pipe", 344 "sleep", 345 "sticky", 346 "axi_m", 347 "axi_s", 348 "ahb", 349 "axi_m_sticky"; 350 status = "disabled"; 351 }; 352 353 pcie_phy1: phy@8e000 { 354 compatible = "qcom,ipq8074-qmp-pcie-phy"; 355 reg = <0x8e000 0x1000>; 356 #phy-cells = <0>; 357 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 358 clock-names = "pipe_clk"; 359 clock-output-names = "pcie20_phy1_pipe_clk"; 360 361 resets = <&gcc GCC_PCIE1_PHY_BCR>, 362 <&gcc GCC_PCIE1PHY_PHY_BCR>; 363 reset-names = "phy", 364 "common"; 365 status = "disabled"; 366 }; 367 368 pcie1: pci@10000000 { 369 compatible = "qcom,pcie-ipq8074"; 370 reg = <0x10000000 0xf1d 371 0x10000f20 0xa8 372 0x88000 0x2000 373 0x10100000 0x1000>; 374 reg-names = "dbi", "elbi", "parf", "config"; 375 device_type = "pci"; 376 linux,pci-domain = <1>; 377 bus-range = <0x00 0xff>; 378 num-lanes = <1>; 379 #address-cells = <3>; 380 #size-cells = <2>; 381 382 phys = <&pcie_phy1>; 383 phy-names = "pciephy"; 384 385 ranges = <0x81000000 0 0x10200000 0x10200000 386 0 0x100000 /* downstream I/O */ 387 0x82000000 0 0x10300000 0x10300000 388 0 0xd00000>; /* non-prefetchable memory */ 389 390 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 391 interrupt-names = "msi"; 392 #interrupt-cells = <1>; 393 interrupt-map-mask = <0 0 0 0x7>; 394 interrupt-map = <0 0 0 1 &intc 0 142 395 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 396 <0 0 0 2 &intc 0 143 397 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 398 <0 0 0 3 &intc 0 144 399 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 400 <0 0 0 4 &intc 0 145 401 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 402 403 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 404 <&gcc GCC_PCIE1_AXI_M_CLK>, 405 <&gcc GCC_PCIE1_AXI_S_CLK>, 406 <&gcc GCC_PCIE1_AHB_CLK>, 407 <&gcc GCC_PCIE1_AUX_CLK>; 408 clock-names = "iface", 409 "axi_m", 410 "axi_s", 411 "ahb", 412 "aux"; 413 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 414 <&gcc GCC_PCIE1_SLEEP_ARES>, 415 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 416 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 417 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 418 <&gcc GCC_PCIE1_AHB_ARES>, 419 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 420 reset-names = "pipe", 421 "sleep", 422 "sticky", 423 "axi_m", 424 "axi_s", 425 "ahb", 426 "axi_m_sticky"; 427 status = "disabled"; 428 }; 429 }; 430 431 cpus { 432 #address-cells = <0x1>; 433 #size-cells = <0x0>; 434 435 CPU0: cpu@0 { 436 device_type = "cpu"; 437 compatible = "arm,cortex-a53"; 438 reg = <0x0>; 439 next-level-cache = <&L2_0>; 440 enable-method = "psci"; 441 }; 442 443 CPU1: cpu@1 { 444 device_type = "cpu"; 445 compatible = "arm,cortex-a53"; 446 enable-method = "psci"; 447 reg = <0x1>; 448 next-level-cache = <&L2_0>; 449 }; 450 451 CPU2: cpu@2 { 452 device_type = "cpu"; 453 compatible = "arm,cortex-a53"; 454 enable-method = "psci"; 455 reg = <0x2>; 456 next-level-cache = <&L2_0>; 457 }; 458 459 CPU3: cpu@3 { 460 device_type = "cpu"; 461 compatible = "arm,cortex-a53"; 462 enable-method = "psci"; 463 reg = <0x3>; 464 next-level-cache = <&L2_0>; 465 }; 466 467 L2_0: l2-cache { 468 compatible = "cache"; 469 cache-level = <0x2>; 470 }; 471 }; 472 473 psci { 474 compatible = "arm,psci-1.0"; 475 method = "smc"; 476 }; 477 478 pmu { 479 compatible = "arm,armv8-pmuv3"; 480 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 481 }; 482 483 clocks { 484 sleep_clk: sleep_clk { 485 compatible = "fixed-clock"; 486 clock-frequency = <32000>; 487 #clock-cells = <0>; 488 }; 489 490 xo: xo { 491 compatible = "fixed-clock"; 492 clock-frequency = <19200000>; 493 #clock-cells = <0>; 494 }; 495 }; 496}; 497