1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/cl006b.h> 29 #include <nvif/cl506f.h> 30 #include <nvif/cl906f.h> 31 #include <nvif/cla06f.h> 32 #include <nvif/clc36f.h> 33 #include <nvif/ioctl.h> 34 35 /*XXX*/ 36 #include <core/client.h> 37 38 #include "nouveau_drv.h" 39 #include "nouveau_dma.h" 40 #include "nouveau_bo.h" 41 #include "nouveau_chan.h" 42 #include "nouveau_fence.h" 43 #include "nouveau_abi16.h" 44 #include "nouveau_vmm.h" 45 #include "nouveau_svm.h" 46 47 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 48 int nouveau_vram_pushbuf; 49 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 50 51 static int 52 nouveau_channel_killed(struct nvif_notify *ntfy) 53 { 54 struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill); 55 struct nouveau_cli *cli = (void *)chan->user.client; 56 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 57 atomic_set(&chan->killed, 1); 58 if (chan->fence) 59 nouveau_fence_context_kill(chan->fence, -ENODEV); 60 return NVIF_NOTIFY_DROP; 61 } 62 63 int 64 nouveau_channel_idle(struct nouveau_channel *chan) 65 { 66 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 67 struct nouveau_cli *cli = (void *)chan->user.client; 68 struct nouveau_fence *fence = NULL; 69 int ret; 70 71 ret = nouveau_fence_new(chan, false, &fence); 72 if (!ret) { 73 ret = nouveau_fence_wait(fence, false, false); 74 nouveau_fence_unref(&fence); 75 } 76 77 if (ret) { 78 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 79 chan->chid, nvxx_client(&cli->base)->name); 80 return ret; 81 } 82 } 83 return 0; 84 } 85 86 void 87 nouveau_channel_del(struct nouveau_channel **pchan) 88 { 89 struct nouveau_channel *chan = *pchan; 90 if (chan) { 91 struct nouveau_cli *cli = (void *)chan->user.client; 92 bool super; 93 94 if (cli) { 95 super = cli->base.super; 96 cli->base.super = true; 97 } 98 99 if (chan->fence) 100 nouveau_fence(chan->drm)->context_del(chan); 101 102 if (cli) 103 nouveau_svmm_part(chan->vmm->svmm, chan->inst); 104 105 nvif_object_fini(&chan->nvsw); 106 nvif_object_fini(&chan->gart); 107 nvif_object_fini(&chan->vram); 108 nvif_notify_fini(&chan->kill); 109 nvif_object_fini(&chan->user); 110 nvif_object_fini(&chan->push.ctxdma); 111 nouveau_vma_del(&chan->push.vma); 112 nouveau_bo_unmap(chan->push.buffer); 113 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 114 nouveau_bo_unpin(chan->push.buffer); 115 nouveau_bo_ref(NULL, &chan->push.buffer); 116 kfree(chan); 117 118 if (cli) 119 cli->base.super = super; 120 } 121 *pchan = NULL; 122 } 123 124 static int 125 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 126 u32 size, struct nouveau_channel **pchan) 127 { 128 struct nouveau_cli *cli = (void *)device->object.client; 129 struct nv_dma_v0 args = {}; 130 struct nouveau_channel *chan; 131 u32 target; 132 int ret; 133 134 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 135 if (!chan) 136 return -ENOMEM; 137 138 chan->device = device; 139 chan->drm = drm; 140 chan->vmm = cli->svm.cli ? &cli->svm : &cli->vmm; 141 atomic_set(&chan->killed, 0); 142 143 /* allocate memory for dma push buffer */ 144 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 145 if (nouveau_vram_pushbuf) 146 target = TTM_PL_FLAG_VRAM; 147 148 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 149 &chan->push.buffer); 150 if (ret == 0) { 151 ret = nouveau_bo_pin(chan->push.buffer, target, false); 152 if (ret == 0) 153 ret = nouveau_bo_map(chan->push.buffer); 154 } 155 156 if (ret) { 157 nouveau_channel_del(pchan); 158 return ret; 159 } 160 161 /* create dma object covering the *entire* memory space that the 162 * pushbuf lives in, this is because the GEM code requires that 163 * we be able to call out to other (indirect) push buffers 164 */ 165 chan->push.addr = chan->push.buffer->bo.offset; 166 167 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 168 ret = nouveau_vma_new(chan->push.buffer, chan->vmm, 169 &chan->push.vma); 170 if (ret) { 171 nouveau_channel_del(pchan); 172 return ret; 173 } 174 175 chan->push.addr = chan->push.vma->addr; 176 177 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI) 178 return 0; 179 180 args.target = NV_DMA_V0_TARGET_VM; 181 args.access = NV_DMA_V0_ACCESS_VM; 182 args.start = 0; 183 args.limit = chan->vmm->vmm.limit - 1; 184 } else 185 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 186 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 187 /* nv04 vram pushbuf hack, retarget to its location in 188 * the framebuffer bar rather than direct vram access.. 189 * nfi why this exists, it came from the -nv ddx. 190 */ 191 args.target = NV_DMA_V0_TARGET_PCI; 192 args.access = NV_DMA_V0_ACCESS_RDWR; 193 args.start = nvxx_device(device)->func-> 194 resource_addr(nvxx_device(device), 1); 195 args.limit = args.start + device->info.ram_user - 1; 196 } else { 197 args.target = NV_DMA_V0_TARGET_VRAM; 198 args.access = NV_DMA_V0_ACCESS_RDWR; 199 args.start = 0; 200 args.limit = device->info.ram_user - 1; 201 } 202 } else { 203 if (chan->drm->agp.bridge) { 204 args.target = NV_DMA_V0_TARGET_AGP; 205 args.access = NV_DMA_V0_ACCESS_RDWR; 206 args.start = chan->drm->agp.base; 207 args.limit = chan->drm->agp.base + 208 chan->drm->agp.size - 1; 209 } else { 210 args.target = NV_DMA_V0_TARGET_VM; 211 args.access = NV_DMA_V0_ACCESS_RDWR; 212 args.start = 0; 213 args.limit = chan->vmm->vmm.limit - 1; 214 } 215 } 216 217 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, 218 &args, sizeof(args), &chan->push.ctxdma); 219 if (ret) { 220 nouveau_channel_del(pchan); 221 return ret; 222 } 223 224 return 0; 225 } 226 227 static int 228 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 229 u64 runlist, bool priv, struct nouveau_channel **pchan) 230 { 231 static const u16 oclasses[] = { TURING_CHANNEL_GPFIFO_A, 232 VOLTA_CHANNEL_GPFIFO_A, 233 PASCAL_CHANNEL_GPFIFO_A, 234 MAXWELL_CHANNEL_GPFIFO_A, 235 KEPLER_CHANNEL_GPFIFO_B, 236 KEPLER_CHANNEL_GPFIFO_A, 237 FERMI_CHANNEL_GPFIFO, 238 G82_CHANNEL_GPFIFO, 239 NV50_CHANNEL_GPFIFO, 240 0 }; 241 const u16 *oclass = oclasses; 242 union { 243 struct nv50_channel_gpfifo_v0 nv50; 244 struct fermi_channel_gpfifo_v0 fermi; 245 struct kepler_channel_gpfifo_a_v0 kepler; 246 struct volta_channel_gpfifo_a_v0 volta; 247 } args; 248 struct nouveau_channel *chan; 249 u32 size; 250 int ret; 251 252 /* allocate dma push buffer */ 253 ret = nouveau_channel_prep(drm, device, 0x12000, &chan); 254 *pchan = chan; 255 if (ret) 256 return ret; 257 258 /* create channel object */ 259 do { 260 if (oclass[0] >= VOLTA_CHANNEL_GPFIFO_A) { 261 args.volta.version = 0; 262 args.volta.ilength = 0x02000; 263 args.volta.ioffset = 0x10000 + chan->push.addr; 264 args.volta.runlist = runlist; 265 args.volta.vmm = nvif_handle(&chan->vmm->vmm.object); 266 args.volta.priv = priv; 267 size = sizeof(args.volta); 268 } else 269 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 270 args.kepler.version = 0; 271 args.kepler.ilength = 0x02000; 272 args.kepler.ioffset = 0x10000 + chan->push.addr; 273 args.kepler.runlist = runlist; 274 args.kepler.vmm = nvif_handle(&chan->vmm->vmm.object); 275 args.kepler.priv = priv; 276 size = sizeof(args.kepler); 277 } else 278 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 279 args.fermi.version = 0; 280 args.fermi.ilength = 0x02000; 281 args.fermi.ioffset = 0x10000 + chan->push.addr; 282 args.fermi.vmm = nvif_handle(&chan->vmm->vmm.object); 283 size = sizeof(args.fermi); 284 } else { 285 args.nv50.version = 0; 286 args.nv50.ilength = 0x02000; 287 args.nv50.ioffset = 0x10000 + chan->push.addr; 288 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 289 args.nv50.vmm = nvif_handle(&chan->vmm->vmm.object); 290 size = sizeof(args.nv50); 291 } 292 293 ret = nvif_object_init(&device->object, 0, *oclass++, 294 &args, size, &chan->user); 295 if (ret == 0) { 296 if (chan->user.oclass >= VOLTA_CHANNEL_GPFIFO_A) { 297 chan->chid = args.volta.chid; 298 chan->inst = args.volta.inst; 299 chan->token = args.volta.token; 300 } else 301 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) { 302 chan->chid = args.kepler.chid; 303 chan->inst = args.kepler.inst; 304 } else 305 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 306 chan->chid = args.fermi.chid; 307 } else { 308 chan->chid = args.nv50.chid; 309 } 310 return ret; 311 } 312 } while (*oclass); 313 314 nouveau_channel_del(pchan); 315 return ret; 316 } 317 318 static int 319 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 320 struct nouveau_channel **pchan) 321 { 322 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 323 NV17_CHANNEL_DMA, 324 NV10_CHANNEL_DMA, 325 NV03_CHANNEL_DMA, 326 0 }; 327 const u16 *oclass = oclasses; 328 struct nv03_channel_dma_v0 args; 329 struct nouveau_channel *chan; 330 int ret; 331 332 /* allocate dma push buffer */ 333 ret = nouveau_channel_prep(drm, device, 0x10000, &chan); 334 *pchan = chan; 335 if (ret) 336 return ret; 337 338 /* create channel object */ 339 args.version = 0; 340 args.pushbuf = nvif_handle(&chan->push.ctxdma); 341 args.offset = chan->push.addr; 342 343 do { 344 ret = nvif_object_init(&device->object, 0, *oclass++, 345 &args, sizeof(args), &chan->user); 346 if (ret == 0) { 347 chan->chid = args.chid; 348 return ret; 349 } 350 } while (ret && *oclass); 351 352 nouveau_channel_del(pchan); 353 return ret; 354 } 355 356 static int 357 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 358 { 359 struct nvif_device *device = chan->device; 360 struct nouveau_drm *drm = chan->drm; 361 struct nv_dma_v0 args = {}; 362 int ret, i; 363 364 nvif_object_map(&chan->user, NULL, 0); 365 366 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 367 ret = nvif_notify_init(&chan->user, nouveau_channel_killed, 368 true, NV906F_V0_NTFY_KILLED, 369 NULL, 0, 0, &chan->kill); 370 if (ret == 0) 371 ret = nvif_notify_get(&chan->kill); 372 if (ret) { 373 NV_ERROR(drm, "Failed to request channel kill " 374 "notification: %d\n", ret); 375 return ret; 376 } 377 } 378 379 /* allocate dma objects to cover all allowed vram, and gart */ 380 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 381 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 382 args.target = NV_DMA_V0_TARGET_VM; 383 args.access = NV_DMA_V0_ACCESS_VM; 384 args.start = 0; 385 args.limit = chan->vmm->vmm.limit - 1; 386 } else { 387 args.target = NV_DMA_V0_TARGET_VRAM; 388 args.access = NV_DMA_V0_ACCESS_RDWR; 389 args.start = 0; 390 args.limit = device->info.ram_user - 1; 391 } 392 393 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 394 &args, sizeof(args), &chan->vram); 395 if (ret) 396 return ret; 397 398 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 399 args.target = NV_DMA_V0_TARGET_VM; 400 args.access = NV_DMA_V0_ACCESS_VM; 401 args.start = 0; 402 args.limit = chan->vmm->vmm.limit - 1; 403 } else 404 if (chan->drm->agp.bridge) { 405 args.target = NV_DMA_V0_TARGET_AGP; 406 args.access = NV_DMA_V0_ACCESS_RDWR; 407 args.start = chan->drm->agp.base; 408 args.limit = chan->drm->agp.base + 409 chan->drm->agp.size - 1; 410 } else { 411 args.target = NV_DMA_V0_TARGET_VM; 412 args.access = NV_DMA_V0_ACCESS_RDWR; 413 args.start = 0; 414 args.limit = chan->vmm->vmm.limit - 1; 415 } 416 417 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 418 &args, sizeof(args), &chan->gart); 419 if (ret) 420 return ret; 421 } 422 423 /* initialise dma tracking parameters */ 424 switch (chan->user.oclass & 0x00ff) { 425 case 0x006b: 426 case 0x006e: 427 chan->user_put = 0x40; 428 chan->user_get = 0x44; 429 chan->dma.max = (0x10000 / 4) - 2; 430 break; 431 default: 432 chan->user_put = 0x40; 433 chan->user_get = 0x44; 434 chan->user_get_hi = 0x60; 435 chan->dma.ib_base = 0x10000 / 4; 436 chan->dma.ib_max = (0x02000 / 8) - 1; 437 chan->dma.ib_put = 0; 438 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 439 chan->dma.max = chan->dma.ib_base; 440 break; 441 } 442 443 chan->dma.put = 0; 444 chan->dma.cur = chan->dma.put; 445 chan->dma.free = chan->dma.max - chan->dma.cur; 446 447 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 448 if (ret) 449 return ret; 450 451 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 452 OUT_RING(chan, 0x00000000); 453 454 /* allocate software object class (used for fences on <= nv05) */ 455 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 456 ret = nvif_object_init(&chan->user, 0x006e, 457 NVIF_CLASS_SW_NV04, 458 NULL, 0, &chan->nvsw); 459 if (ret) 460 return ret; 461 462 ret = RING_SPACE(chan, 2); 463 if (ret) 464 return ret; 465 466 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 467 OUT_RING (chan, chan->nvsw.handle); 468 FIRE_RING (chan); 469 } 470 471 /* initialise synchronisation */ 472 return nouveau_fence(chan->drm)->context_new(chan); 473 } 474 475 int 476 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 477 u32 arg0, u32 arg1, bool priv, 478 struct nouveau_channel **pchan) 479 { 480 struct nouveau_cli *cli = (void *)device->object.client; 481 bool super; 482 int ret; 483 484 /* hack until fencenv50 is fixed, and agp access relaxed */ 485 super = cli->base.super; 486 cli->base.super = true; 487 488 ret = nouveau_channel_ind(drm, device, arg0, priv, pchan); 489 if (ret) { 490 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 491 ret = nouveau_channel_dma(drm, device, pchan); 492 if (ret) { 493 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 494 goto done; 495 } 496 } 497 498 ret = nouveau_channel_init(*pchan, arg0, arg1); 499 if (ret) { 500 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 501 nouveau_channel_del(pchan); 502 } 503 504 ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst); 505 if (ret) 506 nouveau_channel_del(pchan); 507 508 done: 509 cli->base.super = super; 510 return ret; 511 } 512 513 int 514 nouveau_channels_init(struct nouveau_drm *drm) 515 { 516 struct { 517 struct nv_device_info_v1 m; 518 struct { 519 struct nv_device_info_v1_data channels; 520 } v; 521 } args = { 522 .m.version = 1, 523 .m.count = sizeof(args.v) / sizeof(args.v.channels), 524 .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS, 525 }; 526 struct nvif_object *device = &drm->client.device.object; 527 int ret; 528 529 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); 530 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) 531 return -ENODEV; 532 533 drm->chan.nr = args.v.channels.data; 534 drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr); 535 return 0; 536 } 537