1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <linux/console.h> 26 #include <linux/delay.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/vga_switcheroo.h> 31 #include <linux/mmu_notifier.h> 32 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_ioctl.h> 35 #include <drm/drm_vblank.h> 36 37 #include <core/gpuobj.h> 38 #include <core/option.h> 39 #include <core/pci.h> 40 #include <core/tegra.h> 41 42 #include <nvif/driver.h> 43 #include <nvif/fifo.h> 44 #include <nvif/user.h> 45 46 #include <nvif/class.h> 47 #include <nvif/cl0002.h> 48 #include <nvif/cla06f.h> 49 50 #include "nouveau_drv.h" 51 #include "nouveau_dma.h" 52 #include "nouveau_ttm.h" 53 #include "nouveau_gem.h" 54 #include "nouveau_vga.h" 55 #include "nouveau_led.h" 56 #include "nouveau_hwmon.h" 57 #include "nouveau_acpi.h" 58 #include "nouveau_bios.h" 59 #include "nouveau_ioctl.h" 60 #include "nouveau_abi16.h" 61 #include "nouveau_fbcon.h" 62 #include "nouveau_fence.h" 63 #include "nouveau_debugfs.h" 64 #include "nouveau_usif.h" 65 #include "nouveau_connector.h" 66 #include "nouveau_platform.h" 67 #include "nouveau_svm.h" 68 #include "nouveau_dmem.h" 69 70 MODULE_PARM_DESC(config, "option string to pass to driver core"); 71 static char *nouveau_config; 72 module_param_named(config, nouveau_config, charp, 0400); 73 74 MODULE_PARM_DESC(debug, "debug string to pass to driver core"); 75 static char *nouveau_debug; 76 module_param_named(debug, nouveau_debug, charp, 0400); 77 78 MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); 79 static int nouveau_noaccel = 0; 80 module_param_named(noaccel, nouveau_noaccel, int, 0400); 81 82 MODULE_PARM_DESC(modeset, "enable driver (default: auto, " 83 "0 = disabled, 1 = enabled, 2 = headless)"); 84 int nouveau_modeset = -1; 85 module_param_named(modeset, nouveau_modeset, int, 0400); 86 87 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); 88 static int nouveau_atomic = 0; 89 module_param_named(atomic, nouveau_atomic, int, 0400); 90 91 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); 92 static int nouveau_runtime_pm = -1; 93 module_param_named(runpm, nouveau_runtime_pm, int, 0400); 94 95 static struct drm_driver driver_stub; 96 static struct drm_driver driver_pci; 97 static struct drm_driver driver_platform; 98 99 static u64 100 nouveau_pci_name(struct pci_dev *pdev) 101 { 102 u64 name = (u64)pci_domain_nr(pdev->bus) << 32; 103 name |= pdev->bus->number << 16; 104 name |= PCI_SLOT(pdev->devfn) << 8; 105 return name | PCI_FUNC(pdev->devfn); 106 } 107 108 static u64 109 nouveau_platform_name(struct platform_device *platformdev) 110 { 111 return platformdev->id; 112 } 113 114 static u64 115 nouveau_name(struct drm_device *dev) 116 { 117 if (dev->pdev) 118 return nouveau_pci_name(dev->pdev); 119 else 120 return nouveau_platform_name(to_platform_device(dev->dev)); 121 } 122 123 static inline bool 124 nouveau_cli_work_ready(struct dma_fence *fence) 125 { 126 if (!dma_fence_is_signaled(fence)) 127 return false; 128 dma_fence_put(fence); 129 return true; 130 } 131 132 static void 133 nouveau_cli_work(struct work_struct *w) 134 { 135 struct nouveau_cli *cli = container_of(w, typeof(*cli), work); 136 struct nouveau_cli_work *work, *wtmp; 137 mutex_lock(&cli->lock); 138 list_for_each_entry_safe(work, wtmp, &cli->worker, head) { 139 if (!work->fence || nouveau_cli_work_ready(work->fence)) { 140 list_del(&work->head); 141 work->func(work); 142 } 143 } 144 mutex_unlock(&cli->lock); 145 } 146 147 static void 148 nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb) 149 { 150 struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb); 151 schedule_work(&work->cli->work); 152 } 153 154 void 155 nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence, 156 struct nouveau_cli_work *work) 157 { 158 work->fence = dma_fence_get(fence); 159 work->cli = cli; 160 mutex_lock(&cli->lock); 161 list_add_tail(&work->head, &cli->worker); 162 if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence)) 163 nouveau_cli_work_fence(fence, &work->cb); 164 mutex_unlock(&cli->lock); 165 } 166 167 static void 168 nouveau_cli_fini(struct nouveau_cli *cli) 169 { 170 /* All our channels are dead now, which means all the fences they 171 * own are signalled, and all callback functions have been called. 172 * 173 * So, after flushing the workqueue, there should be nothing left. 174 */ 175 flush_work(&cli->work); 176 WARN_ON(!list_empty(&cli->worker)); 177 178 usif_client_fini(cli); 179 nouveau_vmm_fini(&cli->svm); 180 nouveau_vmm_fini(&cli->vmm); 181 nvif_mmu_fini(&cli->mmu); 182 nvif_device_fini(&cli->device); 183 mutex_lock(&cli->drm->master.lock); 184 nvif_client_fini(&cli->base); 185 mutex_unlock(&cli->drm->master.lock); 186 } 187 188 static int 189 nouveau_cli_init(struct nouveau_drm *drm, const char *sname, 190 struct nouveau_cli *cli) 191 { 192 static const struct nvif_mclass 193 mems[] = { 194 { NVIF_CLASS_MEM_GF100, -1 }, 195 { NVIF_CLASS_MEM_NV50 , -1 }, 196 { NVIF_CLASS_MEM_NV04 , -1 }, 197 {} 198 }; 199 static const struct nvif_mclass 200 mmus[] = { 201 { NVIF_CLASS_MMU_GF100, -1 }, 202 { NVIF_CLASS_MMU_NV50 , -1 }, 203 { NVIF_CLASS_MMU_NV04 , -1 }, 204 {} 205 }; 206 static const struct nvif_mclass 207 vmms[] = { 208 { NVIF_CLASS_VMM_GP100, -1 }, 209 { NVIF_CLASS_VMM_GM200, -1 }, 210 { NVIF_CLASS_VMM_GF100, -1 }, 211 { NVIF_CLASS_VMM_NV50 , -1 }, 212 { NVIF_CLASS_VMM_NV04 , -1 }, 213 {} 214 }; 215 u64 device = nouveau_name(drm->dev); 216 int ret; 217 218 snprintf(cli->name, sizeof(cli->name), "%s", sname); 219 cli->drm = drm; 220 mutex_init(&cli->mutex); 221 usif_client_init(cli); 222 223 INIT_WORK(&cli->work, nouveau_cli_work); 224 INIT_LIST_HEAD(&cli->worker); 225 mutex_init(&cli->lock); 226 227 if (cli == &drm->master) { 228 ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, 229 cli->name, device, &cli->base); 230 } else { 231 mutex_lock(&drm->master.lock); 232 ret = nvif_client_init(&drm->master.base, cli->name, device, 233 &cli->base); 234 mutex_unlock(&drm->master.lock); 235 } 236 if (ret) { 237 NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret); 238 goto done; 239 } 240 241 ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE, 242 &(struct nv_device_v0) { 243 .device = ~0, 244 }, sizeof(struct nv_device_v0), 245 &cli->device); 246 if (ret) { 247 NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret); 248 goto done; 249 } 250 251 ret = nvif_mclass(&cli->device.object, mmus); 252 if (ret < 0) { 253 NV_PRINTK(err, cli, "No supported MMU class\n"); 254 goto done; 255 } 256 257 ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu); 258 if (ret) { 259 NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret); 260 goto done; 261 } 262 263 ret = nvif_mclass(&cli->mmu.object, vmms); 264 if (ret < 0) { 265 NV_PRINTK(err, cli, "No supported VMM class\n"); 266 goto done; 267 } 268 269 ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm); 270 if (ret) { 271 NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret); 272 goto done; 273 } 274 275 ret = nvif_mclass(&cli->mmu.object, mems); 276 if (ret < 0) { 277 NV_PRINTK(err, cli, "No supported MEM class\n"); 278 goto done; 279 } 280 281 cli->mem = &mems[ret]; 282 return 0; 283 done: 284 if (ret) 285 nouveau_cli_fini(cli); 286 return ret; 287 } 288 289 static void 290 nouveau_accel_ce_fini(struct nouveau_drm *drm) 291 { 292 nouveau_channel_idle(drm->cechan); 293 nvif_object_fini(&drm->ttm.copy); 294 nouveau_channel_del(&drm->cechan); 295 } 296 297 static void 298 nouveau_accel_ce_init(struct nouveau_drm *drm) 299 { 300 struct nvif_device *device = &drm->client.device; 301 int ret = 0; 302 303 /* Allocate channel that has access to a (preferably async) copy 304 * engine, to use for TTM buffer moves. 305 */ 306 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { 307 ret = nouveau_channel_new(drm, device, 308 nvif_fifo_runlist_ce(device), 0, 309 true, &drm->cechan); 310 } else 311 if (device->info.chipset >= 0xa3 && 312 device->info.chipset != 0xaa && 313 device->info.chipset != 0xac) { 314 /* Prior to Kepler, there's only a single runlist, so all 315 * engines can be accessed from any channel. 316 * 317 * We still want to use a separate channel though. 318 */ 319 ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false, 320 &drm->cechan); 321 } 322 323 if (ret) 324 NV_ERROR(drm, "failed to create ce channel, %d\n", ret); 325 } 326 327 static void 328 nouveau_accel_gr_fini(struct nouveau_drm *drm) 329 { 330 nouveau_channel_idle(drm->channel); 331 nvif_object_fini(&drm->ntfy); 332 nvkm_gpuobj_del(&drm->notify); 333 nvif_object_fini(&drm->nvsw); 334 nouveau_channel_del(&drm->channel); 335 } 336 337 static void 338 nouveau_accel_gr_init(struct nouveau_drm *drm) 339 { 340 struct nvif_device *device = &drm->client.device; 341 u32 arg0, arg1; 342 int ret; 343 344 /* Allocate channel that has access to the graphics engine. */ 345 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { 346 arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR); 347 arg1 = 1; 348 } else { 349 arg0 = NvDmaFB; 350 arg1 = NvDmaTT; 351 } 352 353 ret = nouveau_channel_new(drm, device, arg0, arg1, false, 354 &drm->channel); 355 if (ret) { 356 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); 357 nouveau_accel_gr_fini(drm); 358 return; 359 } 360 361 /* A SW class is used on pre-NV50 HW to assist with handling the 362 * synchronisation of page flips, as well as to implement fences 363 * on TNT/TNT2 HW that lacks any kind of support in host. 364 */ 365 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 366 ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW, 367 nouveau_abi16_swclass(drm), NULL, 0, 368 &drm->nvsw); 369 if (ret == 0) { 370 ret = RING_SPACE(drm->channel, 2); 371 if (ret == 0) { 372 BEGIN_NV04(drm->channel, NvSubSw, 0, 1); 373 OUT_RING (drm->channel, drm->nvsw.handle); 374 } 375 } 376 377 if (ret) { 378 NV_ERROR(drm, "failed to allocate sw class, %d\n", ret); 379 nouveau_accel_gr_fini(drm); 380 return; 381 } 382 } 383 384 /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason, 385 * even if notification is never requested, so, allocate a ctxdma on 386 * any GPU where it's possible we'll end up using M2MF for BO moves. 387 */ 388 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 389 ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL, 390 &drm->notify); 391 if (ret) { 392 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); 393 nouveau_accel_gr_fini(drm); 394 return; 395 } 396 397 ret = nvif_object_init(&drm->channel->user, NvNotify0, 398 NV_DMA_IN_MEMORY, 399 &(struct nv_dma_v0) { 400 .target = NV_DMA_V0_TARGET_VRAM, 401 .access = NV_DMA_V0_ACCESS_RDWR, 402 .start = drm->notify->addr, 403 .limit = drm->notify->addr + 31 404 }, sizeof(struct nv_dma_v0), 405 &drm->ntfy); 406 if (ret) { 407 nouveau_accel_gr_fini(drm); 408 return; 409 } 410 } 411 } 412 413 static void 414 nouveau_accel_fini(struct nouveau_drm *drm) 415 { 416 nouveau_accel_ce_fini(drm); 417 nouveau_accel_gr_fini(drm); 418 if (drm->fence) 419 nouveau_fence(drm)->dtor(drm); 420 } 421 422 static void 423 nouveau_accel_init(struct nouveau_drm *drm) 424 { 425 struct nvif_device *device = &drm->client.device; 426 struct nvif_sclass *sclass; 427 int ret, i, n; 428 429 if (nouveau_noaccel) 430 return; 431 432 /* Initialise global support for channels, and synchronisation. */ 433 ret = nouveau_channels_init(drm); 434 if (ret) 435 return; 436 437 /*XXX: this is crap, but the fence/channel stuff is a little 438 * backwards in some places. this will be fixed. 439 */ 440 ret = n = nvif_object_sclass_get(&device->object, &sclass); 441 if (ret < 0) 442 return; 443 444 for (ret = -ENOSYS, i = 0; i < n; i++) { 445 switch (sclass[i].oclass) { 446 case NV03_CHANNEL_DMA: 447 ret = nv04_fence_create(drm); 448 break; 449 case NV10_CHANNEL_DMA: 450 ret = nv10_fence_create(drm); 451 break; 452 case NV17_CHANNEL_DMA: 453 case NV40_CHANNEL_DMA: 454 ret = nv17_fence_create(drm); 455 break; 456 case NV50_CHANNEL_GPFIFO: 457 ret = nv50_fence_create(drm); 458 break; 459 case G82_CHANNEL_GPFIFO: 460 ret = nv84_fence_create(drm); 461 break; 462 case FERMI_CHANNEL_GPFIFO: 463 case KEPLER_CHANNEL_GPFIFO_A: 464 case KEPLER_CHANNEL_GPFIFO_B: 465 case MAXWELL_CHANNEL_GPFIFO_A: 466 case PASCAL_CHANNEL_GPFIFO_A: 467 case VOLTA_CHANNEL_GPFIFO_A: 468 case TURING_CHANNEL_GPFIFO_A: 469 ret = nvc0_fence_create(drm); 470 break; 471 default: 472 break; 473 } 474 } 475 476 nvif_object_sclass_put(&sclass); 477 if (ret) { 478 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); 479 nouveau_accel_fini(drm); 480 return; 481 } 482 483 /* Volta requires access to a doorbell register for kickoff. */ 484 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { 485 ret = nvif_user_init(device); 486 if (ret) 487 return; 488 } 489 490 /* Allocate channels we need to support various functions. */ 491 nouveau_accel_gr_init(drm); 492 nouveau_accel_ce_init(drm); 493 494 /* Initialise accelerated TTM buffer moves. */ 495 nouveau_bo_move_init(drm); 496 } 497 498 static int 499 nouveau_drm_device_init(struct drm_device *dev) 500 { 501 struct nouveau_drm *drm; 502 int ret; 503 504 if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) 505 return -ENOMEM; 506 dev->dev_private = drm; 507 drm->dev = dev; 508 509 ret = nouveau_cli_init(drm, "DRM-master", &drm->master); 510 if (ret) 511 goto fail_alloc; 512 513 ret = nouveau_cli_init(drm, "DRM", &drm->client); 514 if (ret) 515 goto fail_master; 516 517 dev->irq_enabled = true; 518 519 nvxx_client(&drm->client.base)->debug = 520 nvkm_dbgopt(nouveau_debug, "DRM"); 521 522 INIT_LIST_HEAD(&drm->clients); 523 spin_lock_init(&drm->tile.lock); 524 525 /* workaround an odd issue on nvc1 by disabling the device's 526 * nosnoop capability. hopefully won't cause issues until a 527 * better fix is found - assuming there is one... 528 */ 529 if (drm->client.device.info.chipset == 0xc1) 530 nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); 531 532 nouveau_vga_init(drm); 533 534 ret = nouveau_ttm_init(drm); 535 if (ret) 536 goto fail_ttm; 537 538 ret = nouveau_bios_init(dev); 539 if (ret) 540 goto fail_bios; 541 542 nouveau_accel_init(drm); 543 544 ret = nouveau_display_create(dev); 545 if (ret) 546 goto fail_dispctor; 547 548 if (dev->mode_config.num_crtc) { 549 ret = nouveau_display_init(dev, false, false); 550 if (ret) 551 goto fail_dispinit; 552 } 553 554 nouveau_debugfs_init(drm); 555 nouveau_hwmon_init(dev); 556 nouveau_svm_init(drm); 557 nouveau_dmem_init(drm); 558 nouveau_fbcon_init(dev); 559 nouveau_led_init(dev); 560 561 if (nouveau_pmops_runtime()) { 562 pm_runtime_use_autosuspend(dev->dev); 563 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 564 pm_runtime_set_active(dev->dev); 565 pm_runtime_allow(dev->dev); 566 pm_runtime_mark_last_busy(dev->dev); 567 pm_runtime_put(dev->dev); 568 } 569 570 return 0; 571 572 fail_dispinit: 573 nouveau_display_destroy(dev); 574 fail_dispctor: 575 nouveau_accel_fini(drm); 576 nouveau_bios_takedown(dev); 577 fail_bios: 578 nouveau_ttm_fini(drm); 579 fail_ttm: 580 nouveau_vga_fini(drm); 581 nouveau_cli_fini(&drm->client); 582 fail_master: 583 nouveau_cli_fini(&drm->master); 584 fail_alloc: 585 kfree(drm); 586 return ret; 587 } 588 589 static void 590 nouveau_drm_device_fini(struct drm_device *dev) 591 { 592 struct nouveau_drm *drm = nouveau_drm(dev); 593 594 if (nouveau_pmops_runtime()) { 595 pm_runtime_get_sync(dev->dev); 596 pm_runtime_forbid(dev->dev); 597 } 598 599 nouveau_led_fini(dev); 600 nouveau_fbcon_fini(dev); 601 nouveau_dmem_fini(drm); 602 nouveau_svm_fini(drm); 603 nouveau_hwmon_fini(dev); 604 nouveau_debugfs_fini(drm); 605 606 if (dev->mode_config.num_crtc) 607 nouveau_display_fini(dev, false, false); 608 nouveau_display_destroy(dev); 609 610 nouveau_accel_fini(drm); 611 nouveau_bios_takedown(dev); 612 613 nouveau_ttm_fini(drm); 614 nouveau_vga_fini(drm); 615 616 nouveau_cli_fini(&drm->client); 617 nouveau_cli_fini(&drm->master); 618 kfree(drm); 619 } 620 621 /* 622 * On some Intel PCIe bridge controllers doing a 623 * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear. 624 * Skipping the intermediate D3hot step seems to make it work again. This is 625 * probably caused by not meeting the expectation the involved AML code has 626 * when the GPU is put into D3hot state before invoking it. 627 * 628 * This leads to various manifestations of this issue: 629 * - AML code execution to power on the GPU hits an infinite loop (as the 630 * code waits on device memory to change). 631 * - kernel crashes, as all PCI reads return -1, which most code isn't able 632 * to handle well enough. 633 * 634 * In all cases dmesg will contain at least one line like this: 635 * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3' 636 * followed by a lot of nouveau timeouts. 637 * 638 * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not 639 * documented PCI config space register 0x248 of the Intel PCIe bridge 640 * controller (0x1901) in order to change the state of the PCIe link between 641 * the PCIe port and the GPU. There are alternative code paths using other 642 * registers, which seem to work fine (executed pre Windows 8): 643 * - 0xbc bit 0x20 (publicly available documentation claims 'reserved') 644 * - 0xb0 bit 0x10 (link disable) 645 * Changing the conditions inside the firmware by poking into the relevant 646 * addresses does resolve the issue, but it seemed to be ACPI private memory 647 * and not any device accessible memory at all, so there is no portable way of 648 * changing the conditions. 649 * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared. 650 * 651 * The only systems where this behavior can be seen are hybrid graphics laptops 652 * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether 653 * this issue only occurs in combination with listed Intel PCIe bridge 654 * controllers and the mentioned GPUs or other devices as well. 655 * 656 * documentation on the PCIe bridge controller can be found in the 657 * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2" 658 * Section "12 PCI Express* Controller (x16) Registers" 659 */ 660 661 static void quirk_broken_nv_runpm(struct pci_dev *pdev) 662 { 663 struct drm_device *dev = pci_get_drvdata(pdev); 664 struct nouveau_drm *drm = nouveau_drm(dev); 665 struct pci_dev *bridge = pci_upstream_bridge(pdev); 666 667 if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL) 668 return; 669 670 switch (bridge->device) { 671 case 0x1901: 672 drm->old_pm_cap = pdev->pm_cap; 673 pdev->pm_cap = 0; 674 NV_INFO(drm, "Disabling PCI power management to avoid bug\n"); 675 break; 676 } 677 } 678 679 static int nouveau_drm_probe(struct pci_dev *pdev, 680 const struct pci_device_id *pent) 681 { 682 struct nvkm_device *device; 683 struct drm_device *drm_dev; 684 int ret; 685 686 if (vga_switcheroo_client_probe_defer(pdev)) 687 return -EPROBE_DEFER; 688 689 /* We need to check that the chipset is supported before booting 690 * fbdev off the hardware, as there's no way to put it back. 691 */ 692 ret = nvkm_device_pci_new(pdev, nouveau_config, "error", 693 true, false, 0, &device); 694 if (ret) 695 return ret; 696 697 nvkm_device_del(&device); 698 699 /* Remove conflicting drivers (vesafb, efifb etc). */ 700 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "nouveaufb"); 701 if (ret) 702 return ret; 703 704 ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug, 705 true, true, ~0ULL, &device); 706 if (ret) 707 return ret; 708 709 pci_set_master(pdev); 710 711 if (nouveau_atomic) 712 driver_pci.driver_features |= DRIVER_ATOMIC; 713 714 drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev); 715 if (IS_ERR(drm_dev)) { 716 ret = PTR_ERR(drm_dev); 717 goto fail_nvkm; 718 } 719 720 ret = pci_enable_device(pdev); 721 if (ret) 722 goto fail_drm; 723 724 drm_dev->pdev = pdev; 725 pci_set_drvdata(pdev, drm_dev); 726 727 ret = nouveau_drm_device_init(drm_dev); 728 if (ret) 729 goto fail_pci; 730 731 ret = drm_dev_register(drm_dev, pent->driver_data); 732 if (ret) 733 goto fail_drm_dev_init; 734 735 quirk_broken_nv_runpm(pdev); 736 return 0; 737 738 fail_drm_dev_init: 739 nouveau_drm_device_fini(drm_dev); 740 fail_pci: 741 pci_disable_device(pdev); 742 fail_drm: 743 drm_dev_put(drm_dev); 744 fail_nvkm: 745 nvkm_device_del(&device); 746 return ret; 747 } 748 749 void 750 nouveau_drm_device_remove(struct drm_device *dev) 751 { 752 struct nouveau_drm *drm = nouveau_drm(dev); 753 struct nvkm_client *client; 754 struct nvkm_device *device; 755 756 drm_dev_unregister(dev); 757 758 dev->irq_enabled = false; 759 client = nvxx_client(&drm->client.base); 760 device = nvkm_device_find(client->device); 761 762 nouveau_drm_device_fini(dev); 763 drm_dev_put(dev); 764 nvkm_device_del(&device); 765 } 766 767 static void 768 nouveau_drm_remove(struct pci_dev *pdev) 769 { 770 struct drm_device *dev = pci_get_drvdata(pdev); 771 struct nouveau_drm *drm = nouveau_drm(dev); 772 773 /* revert our workaround */ 774 if (drm->old_pm_cap) 775 pdev->pm_cap = drm->old_pm_cap; 776 nouveau_drm_device_remove(dev); 777 pci_disable_device(pdev); 778 } 779 780 static int 781 nouveau_do_suspend(struct drm_device *dev, bool runtime) 782 { 783 struct nouveau_drm *drm = nouveau_drm(dev); 784 int ret; 785 786 nouveau_svm_suspend(drm); 787 nouveau_dmem_suspend(drm); 788 nouveau_led_suspend(dev); 789 790 if (dev->mode_config.num_crtc) { 791 NV_DEBUG(drm, "suspending console...\n"); 792 nouveau_fbcon_set_suspend(dev, 1); 793 NV_DEBUG(drm, "suspending display...\n"); 794 ret = nouveau_display_suspend(dev, runtime); 795 if (ret) 796 return ret; 797 } 798 799 NV_DEBUG(drm, "evicting buffers...\n"); 800 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); 801 802 NV_DEBUG(drm, "waiting for kernel channels to go idle...\n"); 803 if (drm->cechan) { 804 ret = nouveau_channel_idle(drm->cechan); 805 if (ret) 806 goto fail_display; 807 } 808 809 if (drm->channel) { 810 ret = nouveau_channel_idle(drm->channel); 811 if (ret) 812 goto fail_display; 813 } 814 815 NV_DEBUG(drm, "suspending fence...\n"); 816 if (drm->fence && nouveau_fence(drm)->suspend) { 817 if (!nouveau_fence(drm)->suspend(drm)) { 818 ret = -ENOMEM; 819 goto fail_display; 820 } 821 } 822 823 NV_DEBUG(drm, "suspending object tree...\n"); 824 ret = nvif_client_suspend(&drm->master.base); 825 if (ret) 826 goto fail_client; 827 828 return 0; 829 830 fail_client: 831 if (drm->fence && nouveau_fence(drm)->resume) 832 nouveau_fence(drm)->resume(drm); 833 834 fail_display: 835 if (dev->mode_config.num_crtc) { 836 NV_DEBUG(drm, "resuming display...\n"); 837 nouveau_display_resume(dev, runtime); 838 } 839 return ret; 840 } 841 842 static int 843 nouveau_do_resume(struct drm_device *dev, bool runtime) 844 { 845 int ret = 0; 846 struct nouveau_drm *drm = nouveau_drm(dev); 847 848 NV_DEBUG(drm, "resuming object tree...\n"); 849 ret = nvif_client_resume(&drm->master.base); 850 if (ret) { 851 NV_ERROR(drm, "Client resume failed with error: %d\n", ret); 852 return ret; 853 } 854 855 NV_DEBUG(drm, "resuming fence...\n"); 856 if (drm->fence && nouveau_fence(drm)->resume) 857 nouveau_fence(drm)->resume(drm); 858 859 nouveau_run_vbios_init(dev); 860 861 if (dev->mode_config.num_crtc) { 862 NV_DEBUG(drm, "resuming display...\n"); 863 nouveau_display_resume(dev, runtime); 864 NV_DEBUG(drm, "resuming console...\n"); 865 nouveau_fbcon_set_suspend(dev, 0); 866 } 867 868 nouveau_led_resume(dev); 869 nouveau_dmem_resume(drm); 870 nouveau_svm_resume(drm); 871 return 0; 872 } 873 874 int 875 nouveau_pmops_suspend(struct device *dev) 876 { 877 struct pci_dev *pdev = to_pci_dev(dev); 878 struct drm_device *drm_dev = pci_get_drvdata(pdev); 879 int ret; 880 881 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || 882 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 883 return 0; 884 885 ret = nouveau_do_suspend(drm_dev, false); 886 if (ret) 887 return ret; 888 889 pci_save_state(pdev); 890 pci_disable_device(pdev); 891 pci_set_power_state(pdev, PCI_D3hot); 892 udelay(200); 893 return 0; 894 } 895 896 int 897 nouveau_pmops_resume(struct device *dev) 898 { 899 struct pci_dev *pdev = to_pci_dev(dev); 900 struct drm_device *drm_dev = pci_get_drvdata(pdev); 901 int ret; 902 903 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || 904 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) 905 return 0; 906 907 pci_set_power_state(pdev, PCI_D0); 908 pci_restore_state(pdev); 909 ret = pci_enable_device(pdev); 910 if (ret) 911 return ret; 912 pci_set_master(pdev); 913 914 ret = nouveau_do_resume(drm_dev, false); 915 916 /* Monitors may have been connected / disconnected during suspend */ 917 schedule_work(&nouveau_drm(drm_dev)->hpd_work); 918 919 return ret; 920 } 921 922 static int 923 nouveau_pmops_freeze(struct device *dev) 924 { 925 struct pci_dev *pdev = to_pci_dev(dev); 926 struct drm_device *drm_dev = pci_get_drvdata(pdev); 927 return nouveau_do_suspend(drm_dev, false); 928 } 929 930 static int 931 nouveau_pmops_thaw(struct device *dev) 932 { 933 struct pci_dev *pdev = to_pci_dev(dev); 934 struct drm_device *drm_dev = pci_get_drvdata(pdev); 935 return nouveau_do_resume(drm_dev, false); 936 } 937 938 bool 939 nouveau_pmops_runtime(void) 940 { 941 if (nouveau_runtime_pm == -1) 942 return nouveau_is_optimus() || nouveau_is_v1_dsm(); 943 return nouveau_runtime_pm == 1; 944 } 945 946 static int 947 nouveau_pmops_runtime_suspend(struct device *dev) 948 { 949 struct pci_dev *pdev = to_pci_dev(dev); 950 struct drm_device *drm_dev = pci_get_drvdata(pdev); 951 int ret; 952 953 if (!nouveau_pmops_runtime()) { 954 pm_runtime_forbid(dev); 955 return -EBUSY; 956 } 957 958 nouveau_switcheroo_optimus_dsm(); 959 ret = nouveau_do_suspend(drm_dev, true); 960 pci_save_state(pdev); 961 pci_disable_device(pdev); 962 pci_ignore_hotplug(pdev); 963 pci_set_power_state(pdev, PCI_D3cold); 964 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 965 return ret; 966 } 967 968 static int 969 nouveau_pmops_runtime_resume(struct device *dev) 970 { 971 struct pci_dev *pdev = to_pci_dev(dev); 972 struct drm_device *drm_dev = pci_get_drvdata(pdev); 973 struct nouveau_drm *drm = nouveau_drm(drm_dev); 974 struct nvif_device *device = &nouveau_drm(drm_dev)->client.device; 975 int ret; 976 977 if (!nouveau_pmops_runtime()) { 978 pm_runtime_forbid(dev); 979 return -EBUSY; 980 } 981 982 pci_set_power_state(pdev, PCI_D0); 983 pci_restore_state(pdev); 984 ret = pci_enable_device(pdev); 985 if (ret) 986 return ret; 987 pci_set_master(pdev); 988 989 ret = nouveau_do_resume(drm_dev, true); 990 if (ret) { 991 NV_ERROR(drm, "resume failed with: %d\n", ret); 992 return ret; 993 } 994 995 /* do magic */ 996 nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25)); 997 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 998 999 /* Monitors may have been connected / disconnected during suspend */ 1000 schedule_work(&nouveau_drm(drm_dev)->hpd_work); 1001 1002 return ret; 1003 } 1004 1005 static int 1006 nouveau_pmops_runtime_idle(struct device *dev) 1007 { 1008 if (!nouveau_pmops_runtime()) { 1009 pm_runtime_forbid(dev); 1010 return -EBUSY; 1011 } 1012 1013 pm_runtime_mark_last_busy(dev); 1014 pm_runtime_autosuspend(dev); 1015 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1016 return 1; 1017 } 1018 1019 static int 1020 nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) 1021 { 1022 struct nouveau_drm *drm = nouveau_drm(dev); 1023 struct nouveau_cli *cli; 1024 char name[32], tmpname[TASK_COMM_LEN]; 1025 int ret; 1026 1027 /* need to bring up power immediately if opening device */ 1028 ret = pm_runtime_get_sync(dev->dev); 1029 if (ret < 0 && ret != -EACCES) 1030 return ret; 1031 1032 get_task_comm(tmpname, current); 1033 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); 1034 1035 if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) { 1036 ret = -ENOMEM; 1037 goto done; 1038 } 1039 1040 ret = nouveau_cli_init(drm, name, cli); 1041 if (ret) 1042 goto done; 1043 1044 cli->base.super = false; 1045 1046 fpriv->driver_priv = cli; 1047 1048 mutex_lock(&drm->client.mutex); 1049 list_add(&cli->head, &drm->clients); 1050 mutex_unlock(&drm->client.mutex); 1051 1052 done: 1053 if (ret && cli) { 1054 nouveau_cli_fini(cli); 1055 kfree(cli); 1056 } 1057 1058 pm_runtime_mark_last_busy(dev->dev); 1059 pm_runtime_put_autosuspend(dev->dev); 1060 return ret; 1061 } 1062 1063 static void 1064 nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) 1065 { 1066 struct nouveau_cli *cli = nouveau_cli(fpriv); 1067 struct nouveau_drm *drm = nouveau_drm(dev); 1068 1069 pm_runtime_get_sync(dev->dev); 1070 1071 mutex_lock(&cli->mutex); 1072 if (cli->abi16) 1073 nouveau_abi16_fini(cli->abi16); 1074 mutex_unlock(&cli->mutex); 1075 1076 mutex_lock(&drm->client.mutex); 1077 list_del(&cli->head); 1078 mutex_unlock(&drm->client.mutex); 1079 1080 nouveau_cli_fini(cli); 1081 kfree(cli); 1082 pm_runtime_mark_last_busy(dev->dev); 1083 pm_runtime_put_autosuspend(dev->dev); 1084 } 1085 1086 static const struct drm_ioctl_desc 1087 nouveau_ioctls[] = { 1088 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW), 1089 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1090 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW), 1091 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW), 1092 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW), 1093 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW), 1094 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW), 1095 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW), 1096 DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW), 1097 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW), 1098 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW), 1099 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW), 1100 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW), 1101 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW), 1102 }; 1103 1104 long 1105 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1106 { 1107 struct drm_file *filp = file->private_data; 1108 struct drm_device *dev = filp->minor->dev; 1109 long ret; 1110 1111 ret = pm_runtime_get_sync(dev->dev); 1112 if (ret < 0 && ret != -EACCES) 1113 return ret; 1114 1115 switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { 1116 case DRM_NOUVEAU_NVIF: 1117 ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); 1118 break; 1119 default: 1120 ret = drm_ioctl(file, cmd, arg); 1121 break; 1122 } 1123 1124 pm_runtime_mark_last_busy(dev->dev); 1125 pm_runtime_put_autosuspend(dev->dev); 1126 return ret; 1127 } 1128 1129 static const struct file_operations 1130 nouveau_driver_fops = { 1131 .owner = THIS_MODULE, 1132 .open = drm_open, 1133 .release = drm_release, 1134 .unlocked_ioctl = nouveau_drm_ioctl, 1135 .mmap = nouveau_ttm_mmap, 1136 .poll = drm_poll, 1137 .read = drm_read, 1138 #if defined(CONFIG_COMPAT) 1139 .compat_ioctl = nouveau_compat_ioctl, 1140 #endif 1141 .llseek = noop_llseek, 1142 }; 1143 1144 static struct drm_driver 1145 driver_stub = { 1146 .driver_features = 1147 DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER 1148 #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT) 1149 | DRIVER_KMS_LEGACY_CONTEXT 1150 #endif 1151 , 1152 1153 .open = nouveau_drm_open, 1154 .postclose = nouveau_drm_postclose, 1155 .lastclose = nouveau_vga_lastclose, 1156 1157 #if defined(CONFIG_DEBUG_FS) 1158 .debugfs_init = nouveau_drm_debugfs_init, 1159 #endif 1160 1161 .ioctls = nouveau_ioctls, 1162 .num_ioctls = ARRAY_SIZE(nouveau_ioctls), 1163 .fops = &nouveau_driver_fops, 1164 1165 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1166 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1167 .gem_prime_pin = nouveau_gem_prime_pin, 1168 .gem_prime_unpin = nouveau_gem_prime_unpin, 1169 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, 1170 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, 1171 .gem_prime_vmap = nouveau_gem_prime_vmap, 1172 .gem_prime_vunmap = nouveau_gem_prime_vunmap, 1173 1174 .gem_free_object_unlocked = nouveau_gem_object_del, 1175 .gem_open_object = nouveau_gem_object_open, 1176 .gem_close_object = nouveau_gem_object_close, 1177 1178 .dumb_create = nouveau_display_dumb_create, 1179 .dumb_map_offset = nouveau_display_dumb_map_offset, 1180 1181 .name = DRIVER_NAME, 1182 .desc = DRIVER_DESC, 1183 #ifdef GIT_REVISION 1184 .date = GIT_REVISION, 1185 #else 1186 .date = DRIVER_DATE, 1187 #endif 1188 .major = DRIVER_MAJOR, 1189 .minor = DRIVER_MINOR, 1190 .patchlevel = DRIVER_PATCHLEVEL, 1191 }; 1192 1193 static struct pci_device_id 1194 nouveau_drm_pci_table[] = { 1195 { 1196 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 1197 .class = PCI_BASE_CLASS_DISPLAY << 16, 1198 .class_mask = 0xff << 16, 1199 }, 1200 { 1201 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), 1202 .class = PCI_BASE_CLASS_DISPLAY << 16, 1203 .class_mask = 0xff << 16, 1204 }, 1205 {} 1206 }; 1207 1208 static void nouveau_display_options(void) 1209 { 1210 DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); 1211 1212 DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); 1213 DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); 1214 DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); 1215 DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel); 1216 DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); 1217 DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); 1218 DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); 1219 DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); 1220 DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); 1221 DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); 1222 DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz); 1223 } 1224 1225 static const struct dev_pm_ops nouveau_pm_ops = { 1226 .suspend = nouveau_pmops_suspend, 1227 .resume = nouveau_pmops_resume, 1228 .freeze = nouveau_pmops_freeze, 1229 .thaw = nouveau_pmops_thaw, 1230 .poweroff = nouveau_pmops_freeze, 1231 .restore = nouveau_pmops_resume, 1232 .runtime_suspend = nouveau_pmops_runtime_suspend, 1233 .runtime_resume = nouveau_pmops_runtime_resume, 1234 .runtime_idle = nouveau_pmops_runtime_idle, 1235 }; 1236 1237 static struct pci_driver 1238 nouveau_drm_pci_driver = { 1239 .name = "nouveau", 1240 .id_table = nouveau_drm_pci_table, 1241 .probe = nouveau_drm_probe, 1242 .remove = nouveau_drm_remove, 1243 .driver.pm = &nouveau_pm_ops, 1244 }; 1245 1246 struct drm_device * 1247 nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, 1248 struct platform_device *pdev, 1249 struct nvkm_device **pdevice) 1250 { 1251 struct drm_device *drm; 1252 int err; 1253 1254 err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, 1255 true, true, ~0ULL, pdevice); 1256 if (err) 1257 goto err_free; 1258 1259 drm = drm_dev_alloc(&driver_platform, &pdev->dev); 1260 if (IS_ERR(drm)) { 1261 err = PTR_ERR(drm); 1262 goto err_free; 1263 } 1264 1265 err = nouveau_drm_device_init(drm); 1266 if (err) 1267 goto err_put; 1268 1269 platform_set_drvdata(pdev, drm); 1270 1271 return drm; 1272 1273 err_put: 1274 drm_dev_put(drm); 1275 err_free: 1276 nvkm_device_del(pdevice); 1277 1278 return ERR_PTR(err); 1279 } 1280 1281 static int __init 1282 nouveau_drm_init(void) 1283 { 1284 driver_pci = driver_stub; 1285 driver_platform = driver_stub; 1286 1287 nouveau_display_options(); 1288 1289 if (nouveau_modeset == -1) { 1290 if (vgacon_text_force()) 1291 nouveau_modeset = 0; 1292 } 1293 1294 if (!nouveau_modeset) 1295 return 0; 1296 1297 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1298 platform_driver_register(&nouveau_platform_driver); 1299 #endif 1300 1301 nouveau_register_dsm_handler(); 1302 nouveau_backlight_ctor(); 1303 1304 #ifdef CONFIG_PCI 1305 return pci_register_driver(&nouveau_drm_pci_driver); 1306 #else 1307 return 0; 1308 #endif 1309 } 1310 1311 static void __exit 1312 nouveau_drm_exit(void) 1313 { 1314 if (!nouveau_modeset) 1315 return; 1316 1317 #ifdef CONFIG_PCI 1318 pci_unregister_driver(&nouveau_drm_pci_driver); 1319 #endif 1320 nouveau_backlight_dtor(); 1321 nouveau_unregister_dsm_handler(); 1322 1323 #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER 1324 platform_driver_unregister(&nouveau_platform_driver); 1325 #endif 1326 if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM)) 1327 mmu_notifier_synchronize(); 1328 } 1329 1330 module_init(nouveau_drm_init); 1331 module_exit(nouveau_drm_exit); 1332 1333 MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); 1334 MODULE_AUTHOR(DRIVER_AUTHOR); 1335 MODULE_DESCRIPTION(DRIVER_DESC); 1336 MODULE_LICENSE("GPL and additional rights"); 1337