1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH Mobile I2C Controller 4 * 5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com> 6 * Copyright (C) 2008 Magnus Damm 7 * 8 * Portions of the code based on out-of-tree driver i2c-sh7343.c 9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/slab.h> 27 28 /* Transmit operation: */ 29 /* */ 30 /* 0 byte transmit */ 31 /* BUS: S A8 ACK P(*) */ 32 /* IRQ: DTE WAIT */ 33 /* ICIC: */ 34 /* ICCR: 0x94 0x90 */ 35 /* ICDR: A8 */ 36 /* */ 37 /* 1 byte transmit */ 38 /* BUS: S A8 ACK D8(1) ACK P(*) */ 39 /* IRQ: DTE WAIT WAIT */ 40 /* ICIC: -DTE */ 41 /* ICCR: 0x94 0x90 */ 42 /* ICDR: A8 D8(1) */ 43 /* */ 44 /* 2 byte transmit */ 45 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */ 46 /* IRQ: DTE WAIT WAIT WAIT */ 47 /* ICIC: -DTE */ 48 /* ICCR: 0x94 0x90 */ 49 /* ICDR: A8 D8(1) D8(2) */ 50 /* */ 51 /* 3 bytes or more, +---------+ gets repeated */ 52 /* */ 53 /* */ 54 /* Receive operation: */ 55 /* */ 56 /* 0 byte receive - not supported since slave may hold SDA low */ 57 /* */ 58 /* 1 byte receive [TX] | [RX] */ 59 /* BUS: S A8 ACK | D8(1) ACK P(*) */ 60 /* IRQ: DTE WAIT | WAIT DTE */ 61 /* ICIC: -DTE | +DTE */ 62 /* ICCR: 0x94 0x81 | 0xc0 */ 63 /* ICDR: A8 | D8(1) */ 64 /* */ 65 /* 2 byte receive [TX]| [RX] */ 66 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */ 67 /* IRQ: DTE WAIT | WAIT WAIT DTE */ 68 /* ICIC: -DTE | +DTE */ 69 /* ICCR: 0x94 0x81 | 0xc0 */ 70 /* ICDR: A8 | D8(1) D8(2) */ 71 /* */ 72 /* 3 byte receive [TX] | [RX] (*) */ 73 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */ 74 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */ 75 /* ICIC: -DTE | +DTE */ 76 /* ICCR: 0x94 0x81 | 0xc0 */ 77 /* ICDR: A8 | D8(1) D8(2) D8(3) */ 78 /* */ 79 /* 4 bytes or more, this part is repeated +---------+ */ 80 /* */ 81 /* */ 82 /* Interrupt order and BUSY flag */ 83 /* ___ _ */ 84 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */ 85 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */ 86 /* */ 87 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */ 88 /* ___ */ 89 /* WAIT IRQ ________________________________/ \___________ */ 90 /* TACK IRQ ____________________________________/ \_______ */ 91 /* DTE IRQ __________________________________________/ \_ */ 92 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 93 /* _______________________________________________ */ 94 /* BUSY __/ \_ */ 95 /* */ 96 /* (*) The STOP condition is only sent by the master at the end of the last */ 97 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */ 98 /* only cleared after the STOP condition, so, between messages we have to */ 99 /* poll for the DTE bit. */ 100 /* */ 101 102 enum sh_mobile_i2c_op { 103 OP_START = 0, 104 OP_TX_FIRST, 105 OP_TX, 106 OP_TX_STOP, 107 OP_TX_TO_RX, 108 OP_RX, 109 OP_RX_STOP, 110 OP_RX_STOP_DATA, 111 }; 112 113 struct sh_mobile_i2c_data { 114 struct device *dev; 115 void __iomem *reg; 116 struct i2c_adapter adap; 117 unsigned long bus_speed; 118 unsigned int clks_per_count; 119 struct clk *clk; 120 u_int8_t icic; 121 u_int8_t flags; 122 u_int16_t iccl; 123 u_int16_t icch; 124 125 spinlock_t lock; 126 wait_queue_head_t wait; 127 struct i2c_msg *msg; 128 int pos; 129 int sr; 130 bool send_stop; 131 bool stop_after_dma; 132 133 struct resource *res; 134 struct dma_chan *dma_tx; 135 struct dma_chan *dma_rx; 136 struct scatterlist sg; 137 enum dma_data_direction dma_direction; 138 u8 *dma_buf; 139 }; 140 141 struct sh_mobile_dt_config { 142 int clks_per_count; 143 int (*setup)(struct sh_mobile_i2c_data *pd); 144 }; 145 146 #define IIC_FLAG_HAS_ICIC67 (1 << 0) 147 148 /* Register offsets */ 149 #define ICDR 0x00 150 #define ICCR 0x04 151 #define ICSR 0x08 152 #define ICIC 0x0c 153 #define ICCL 0x10 154 #define ICCH 0x14 155 #define ICSTART 0x70 156 157 /* Register bits */ 158 #define ICCR_ICE 0x80 159 #define ICCR_RACK 0x40 160 #define ICCR_TRS 0x10 161 #define ICCR_BBSY 0x04 162 #define ICCR_SCP 0x01 163 164 #define ICSR_SCLM 0x80 165 #define ICSR_SDAM 0x40 166 #define SW_DONE 0x20 167 #define ICSR_BUSY 0x10 168 #define ICSR_AL 0x08 169 #define ICSR_TACK 0x04 170 #define ICSR_WAIT 0x02 171 #define ICSR_DTE 0x01 172 173 #define ICIC_ICCLB8 0x80 174 #define ICIC_ICCHB8 0x40 175 #define ICIC_TDMAE 0x20 176 #define ICIC_RDMAE 0x10 177 #define ICIC_ALE 0x08 178 #define ICIC_TACKE 0x04 179 #define ICIC_WAITE 0x02 180 #define ICIC_DTEE 0x01 181 182 #define ICSTART_ICSTART 0x10 183 184 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 185 { 186 if (offs == ICIC) 187 data |= pd->icic; 188 189 iowrite8(data, pd->reg + offs); 190 } 191 192 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs) 193 { 194 return ioread8(pd->reg + offs); 195 } 196 197 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs, 198 unsigned char set, unsigned char clr) 199 { 200 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 201 } 202 203 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf) 204 { 205 /* 206 * Conditional expression: 207 * ICCL >= COUNT_CLK * (tLOW + tf) 208 * 209 * SH-Mobile IIC hardware starts counting the LOW period of 210 * the SCL signal (tLOW) as soon as it pulls the SCL line. 211 * In order to meet the tLOW timing spec, we need to take into 212 * account the fall time of SCL signal (tf). Default tf value 213 * should be 0.3 us, for safety. 214 */ 215 return (((count_khz * (tLOW + tf)) + 5000) / 10000); 216 } 217 218 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf) 219 { 220 /* 221 * Conditional expression: 222 * ICCH >= COUNT_CLK * (tHIGH + tf) 223 * 224 * SH-Mobile IIC hardware is aware of SCL transition period 'tr', 225 * and can ignore it. SH-Mobile IIC controller starts counting 226 * the HIGH period of the SCL signal (tHIGH) after the SCL input 227 * voltage increases at VIH. 228 * 229 * Afterward it turned out calculating ICCH using only tHIGH spec 230 * will result in violation of the tHD;STA timing spec. We need 231 * to take into account the fall time of SDA signal (tf) at START 232 * condition, in order to meet both tHIGH and tHD;STA specs. 233 */ 234 return (((count_khz * (tHIGH + tf)) + 5000) / 10000); 235 } 236 237 static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd) 238 { 239 u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff; 240 241 if (pd->iccl > max_val || pd->icch > max_val) { 242 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n", 243 pd->iccl, pd->icch); 244 return -EINVAL; 245 } 246 247 /* one more bit of ICCL in ICIC */ 248 if (pd->iccl & 0x100) 249 pd->icic |= ICIC_ICCLB8; 250 else 251 pd->icic &= ~ICIC_ICCLB8; 252 253 /* one more bit of ICCH in ICIC */ 254 if (pd->icch & 0x100) 255 pd->icic |= ICIC_ICCHB8; 256 else 257 pd->icic &= ~ICIC_ICCHB8; 258 259 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch); 260 return 0; 261 } 262 263 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd) 264 { 265 unsigned long i2c_clk_khz; 266 u32 tHIGH, tLOW, tf; 267 268 i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count; 269 270 if (pd->bus_speed == I2C_MAX_STANDARD_MODE_FREQ) { 271 tLOW = 47; /* tLOW = 4.7 us */ 272 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */ 273 tf = 3; /* tf = 0.3 us */ 274 } else if (pd->bus_speed == I2C_MAX_FAST_MODE_FREQ) { 275 tLOW = 13; /* tLOW = 1.3 us */ 276 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */ 277 tf = 3; /* tf = 0.3 us */ 278 } else { 279 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n", 280 pd->bus_speed); 281 return -EINVAL; 282 } 283 284 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf); 285 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf); 286 287 return sh_mobile_i2c_check_timing(pd); 288 } 289 290 static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd) 291 { 292 unsigned long clks_per_cycle; 293 294 /* L = 5, H = 4, L + H = 9 */ 295 clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed; 296 pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count); 297 pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count); 298 299 return sh_mobile_i2c_check_timing(pd); 300 } 301 302 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op op) 303 { 304 unsigned char ret = 0; 305 unsigned long flags; 306 307 dev_dbg(pd->dev, "op %d\n", op); 308 309 spin_lock_irqsave(&pd->lock, flags); 310 311 switch (op) { 312 case OP_START: /* issue start and trigger DTE interrupt */ 313 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY); 314 break; 315 case OP_TX_FIRST: /* disable DTE interrupt and write client address */ 316 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 317 iic_wr(pd, ICDR, i2c_8bit_addr_from_msg(pd->msg)); 318 break; 319 case OP_TX: /* write data */ 320 iic_wr(pd, ICDR, pd->msg->buf[pd->pos]); 321 break; 322 case OP_TX_STOP: /* issue a stop (or rep_start) */ 323 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS 324 : ICCR_ICE | ICCR_TRS | ICCR_BBSY); 325 break; 326 case OP_TX_TO_RX: /* select read mode */ 327 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); 328 break; 329 case OP_RX: /* just read data */ 330 ret = iic_rd(pd, ICDR); 331 break; 332 case OP_RX_STOP: /* enable DTE interrupt, issue stop */ 333 iic_wr(pd, ICIC, 334 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 335 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 336 break; 337 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */ 338 iic_wr(pd, ICIC, 339 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 340 ret = iic_rd(pd, ICDR); 341 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK); 342 break; 343 } 344 345 spin_unlock_irqrestore(&pd->lock, flags); 346 347 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret); 348 return ret; 349 } 350 351 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd) 352 { 353 if (pd->pos == pd->msg->len) { 354 i2c_op(pd, OP_TX_STOP); 355 return 1; 356 } 357 358 if (pd->pos == -1) 359 i2c_op(pd, OP_TX_FIRST); 360 else 361 i2c_op(pd, OP_TX); 362 363 pd->pos++; 364 return 0; 365 } 366 367 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd) 368 { 369 int real_pos; 370 371 /* switch from TX (address) to RX (data) adds two interrupts */ 372 real_pos = pd->pos - 2; 373 374 if (pd->pos == -1) { 375 i2c_op(pd, OP_TX_FIRST); 376 } else if (pd->pos == 0) { 377 i2c_op(pd, OP_TX_TO_RX); 378 } else if (pd->pos == pd->msg->len) { 379 if (pd->stop_after_dma) { 380 /* Simulate PIO end condition after DMA transfer */ 381 i2c_op(pd, OP_RX_STOP); 382 pd->pos++; 383 goto done; 384 } 385 386 if (real_pos < 0) 387 i2c_op(pd, OP_RX_STOP); 388 else 389 pd->msg->buf[real_pos] = i2c_op(pd, OP_RX_STOP_DATA); 390 } else if (real_pos >= 0) { 391 pd->msg->buf[real_pos] = i2c_op(pd, OP_RX); 392 } 393 394 done: 395 pd->pos++; 396 return pd->pos == (pd->msg->len + 2); 397 } 398 399 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 400 { 401 struct sh_mobile_i2c_data *pd = dev_id; 402 unsigned char sr; 403 int wakeup = 0; 404 405 sr = iic_rd(pd, ICSR); 406 pd->sr |= sr; /* remember state */ 407 408 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 409 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 410 pd->pos, pd->msg->len); 411 412 /* Kick off TxDMA after preface was done */ 413 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0) 414 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0); 415 else if (sr & (ICSR_AL | ICSR_TACK)) 416 /* don't interrupt transaction - continue to issue stop */ 417 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 418 else if (pd->msg->flags & I2C_M_RD) 419 wakeup = sh_mobile_i2c_isr_rx(pd); 420 else 421 wakeup = sh_mobile_i2c_isr_tx(pd); 422 423 /* Kick off RxDMA after preface was done */ 424 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1) 425 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0); 426 427 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 428 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 429 430 if (wakeup) { 431 pd->sr |= SW_DONE; 432 wake_up(&pd->wait); 433 } 434 435 /* defeat write posting to avoid spurious WAIT interrupts */ 436 iic_rd(pd, ICSR); 437 438 return IRQ_HANDLED; 439 } 440 441 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd) 442 { 443 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE 444 ? pd->dma_rx : pd->dma_tx; 445 446 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg), 447 pd->msg->len, pd->dma_direction); 448 449 pd->dma_direction = DMA_NONE; 450 } 451 452 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd) 453 { 454 if (pd->dma_direction == DMA_NONE) 455 return; 456 else if (pd->dma_direction == DMA_FROM_DEVICE) 457 dmaengine_terminate_all(pd->dma_rx); 458 else if (pd->dma_direction == DMA_TO_DEVICE) 459 dmaengine_terminate_all(pd->dma_tx); 460 461 sh_mobile_i2c_dma_unmap(pd); 462 } 463 464 static void sh_mobile_i2c_dma_callback(void *data) 465 { 466 struct sh_mobile_i2c_data *pd = data; 467 468 sh_mobile_i2c_dma_unmap(pd); 469 pd->pos = pd->msg->len; 470 pd->stop_after_dma = true; 471 472 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE); 473 } 474 475 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev, 476 enum dma_transfer_direction dir, dma_addr_t port_addr) 477 { 478 struct dma_chan *chan; 479 struct dma_slave_config cfg; 480 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx"; 481 int ret; 482 483 chan = dma_request_chan(dev, chan_name); 484 if (IS_ERR(chan)) { 485 dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name, 486 PTR_ERR(chan)); 487 return chan; 488 } 489 490 memset(&cfg, 0, sizeof(cfg)); 491 cfg.direction = dir; 492 if (dir == DMA_MEM_TO_DEV) { 493 cfg.dst_addr = port_addr; 494 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 495 } else { 496 cfg.src_addr = port_addr; 497 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 498 } 499 500 ret = dmaengine_slave_config(chan, &cfg); 501 if (ret) { 502 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret); 503 dma_release_channel(chan); 504 return ERR_PTR(ret); 505 } 506 507 dev_dbg(dev, "got DMA channel for %s\n", chan_name); 508 return chan; 509 } 510 511 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd) 512 { 513 bool read = pd->msg->flags & I2C_M_RD; 514 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 515 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx; 516 struct dma_async_tx_descriptor *txdesc; 517 dma_addr_t dma_addr; 518 dma_cookie_t cookie; 519 520 if (PTR_ERR(chan) == -EPROBE_DEFER) { 521 if (read) 522 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM, 523 pd->res->start + ICDR); 524 else 525 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV, 526 pd->res->start + ICDR); 527 } 528 529 if (IS_ERR(chan)) 530 return; 531 532 dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir); 533 if (dma_mapping_error(chan->device->dev, dma_addr)) { 534 dev_dbg(pd->dev, "dma map failed, using PIO\n"); 535 return; 536 } 537 538 sg_dma_len(&pd->sg) = pd->msg->len; 539 sg_dma_address(&pd->sg) = dma_addr; 540 541 pd->dma_direction = dir; 542 543 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1, 544 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV, 545 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 546 if (!txdesc) { 547 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n"); 548 sh_mobile_i2c_cleanup_dma(pd); 549 return; 550 } 551 552 txdesc->callback = sh_mobile_i2c_dma_callback; 553 txdesc->callback_param = pd; 554 555 cookie = dmaengine_submit(txdesc); 556 if (dma_submit_error(cookie)) { 557 dev_dbg(pd->dev, "submitting dma failed, using PIO\n"); 558 sh_mobile_i2c_cleanup_dma(pd); 559 return; 560 } 561 562 dma_async_issue_pending(chan); 563 } 564 565 static void start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, 566 bool do_init) 567 { 568 if (do_init) { 569 /* Initialize channel registers */ 570 iic_wr(pd, ICCR, ICCR_SCP); 571 572 /* Enable channel and configure rx ack */ 573 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP); 574 575 /* Set the clock */ 576 iic_wr(pd, ICCL, pd->iccl & 0xff); 577 iic_wr(pd, ICCH, pd->icch & 0xff); 578 } 579 580 pd->msg = usr_msg; 581 pd->pos = -1; 582 pd->sr = 0; 583 584 pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8); 585 if (pd->dma_buf) 586 sh_mobile_i2c_xfer_dma(pd); 587 588 /* Enable all interrupts to begin with */ 589 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 590 } 591 592 static int poll_dte(struct sh_mobile_i2c_data *pd) 593 { 594 int i; 595 596 for (i = 1000; i; i--) { 597 u_int8_t val = iic_rd(pd, ICSR); 598 599 if (val & ICSR_DTE) 600 break; 601 602 if (val & ICSR_TACK) 603 return -ENXIO; 604 605 udelay(10); 606 } 607 608 return i ? 0 : -ETIMEDOUT; 609 } 610 611 static int poll_busy(struct sh_mobile_i2c_data *pd) 612 { 613 int i; 614 615 for (i = 1000; i; i--) { 616 u_int8_t val = iic_rd(pd, ICSR); 617 618 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 619 620 /* the interrupt handler may wake us up before the 621 * transfer is finished, so poll the hardware 622 * until we're done. 623 */ 624 if (!(val & ICSR_BUSY)) { 625 /* handle missing acknowledge and arbitration lost */ 626 val |= pd->sr; 627 if (val & ICSR_TACK) 628 return -ENXIO; 629 if (val & ICSR_AL) 630 return -EAGAIN; 631 break; 632 } 633 634 udelay(10); 635 } 636 637 return i ? 0 : -ETIMEDOUT; 638 } 639 640 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter, 641 struct i2c_msg *msgs, 642 int num) 643 { 644 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 645 struct i2c_msg *msg; 646 int err = 0; 647 int i; 648 long timeout; 649 650 /* Wake up device and enable clock */ 651 pm_runtime_get_sync(pd->dev); 652 653 /* Process all messages */ 654 for (i = 0; i < num; i++) { 655 bool do_start = pd->send_stop || !i; 656 msg = &msgs[i]; 657 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP; 658 pd->stop_after_dma = false; 659 660 start_ch(pd, msg, do_start); 661 662 if (do_start) 663 i2c_op(pd, OP_START); 664 665 /* The interrupt handler takes care of the rest... */ 666 timeout = wait_event_timeout(pd->wait, 667 pd->sr & (ICSR_TACK | SW_DONE), 668 adapter->timeout); 669 670 /* 'stop_after_dma' tells if DMA transfer was complete */ 671 i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, pd->stop_after_dma); 672 673 if (!timeout) { 674 dev_err(pd->dev, "Transfer request timed out\n"); 675 if (pd->dma_direction != DMA_NONE) 676 sh_mobile_i2c_cleanup_dma(pd); 677 678 err = -ETIMEDOUT; 679 break; 680 } 681 682 if (pd->send_stop) 683 err = poll_busy(pd); 684 else 685 err = poll_dte(pd); 686 if (err < 0) 687 break; 688 } 689 690 /* Disable channel */ 691 iic_wr(pd, ICCR, ICCR_SCP); 692 693 /* Disable clock and mark device as idle */ 694 pm_runtime_put_sync(pd->dev); 695 696 return err ?: num; 697 } 698 699 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter) 700 { 701 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 702 } 703 704 static const struct i2c_algorithm sh_mobile_i2c_algorithm = { 705 .functionality = sh_mobile_i2c_func, 706 .master_xfer = sh_mobile_i2c_xfer, 707 }; 708 709 static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = { 710 .flags = I2C_AQ_NO_ZERO_LEN_READ, 711 }; 712 713 /* 714 * r8a7740 has an errata regarding I2C I/O pad reset needing this workaround. 715 */ 716 static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd) 717 { 718 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 719 iic_rd(pd, ICCR); /* dummy read */ 720 721 iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0); 722 iic_rd(pd, ICSTART); /* dummy read */ 723 724 udelay(10); 725 726 iic_wr(pd, ICCR, ICCR_SCP); 727 iic_wr(pd, ICSTART, 0); 728 729 udelay(10); 730 731 iic_wr(pd, ICCR, ICCR_TRS); 732 udelay(10); 733 iic_wr(pd, ICCR, 0); 734 udelay(10); 735 iic_wr(pd, ICCR, ICCR_TRS); 736 udelay(10); 737 738 return sh_mobile_i2c_init(pd); 739 } 740 741 static const struct sh_mobile_dt_config default_dt_config = { 742 .clks_per_count = 1, 743 .setup = sh_mobile_i2c_init, 744 }; 745 746 static const struct sh_mobile_dt_config fast_clock_dt_config = { 747 .clks_per_count = 2, 748 .setup = sh_mobile_i2c_init, 749 }; 750 751 static const struct sh_mobile_dt_config v2_freq_calc_dt_config = { 752 .clks_per_count = 2, 753 .setup = sh_mobile_i2c_v2_init, 754 }; 755 756 static const struct sh_mobile_dt_config r8a7740_dt_config = { 757 .clks_per_count = 1, 758 .setup = sh_mobile_i2c_r8a7740_workaround, 759 }; 760 761 static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 762 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config }, 763 { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config }, 764 { .compatible = "renesas,iic-r8a774c0", .data = &fast_clock_dt_config }, 765 { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config }, 766 { .compatible = "renesas,iic-r8a7791", .data = &v2_freq_calc_dt_config }, 767 { .compatible = "renesas,iic-r8a7792", .data = &v2_freq_calc_dt_config }, 768 { .compatible = "renesas,iic-r8a7793", .data = &v2_freq_calc_dt_config }, 769 { .compatible = "renesas,iic-r8a7794", .data = &v2_freq_calc_dt_config }, 770 { .compatible = "renesas,iic-r8a7795", .data = &v2_freq_calc_dt_config }, 771 { .compatible = "renesas,iic-r8a77990", .data = &v2_freq_calc_dt_config }, 772 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config }, 773 { .compatible = "renesas,rcar-gen2-iic", .data = &v2_freq_calc_dt_config }, 774 { .compatible = "renesas,rcar-gen3-iic", .data = &v2_freq_calc_dt_config }, 775 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 776 {}, 777 }; 778 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 779 780 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd) 781 { 782 if (!IS_ERR(pd->dma_tx)) { 783 dma_release_channel(pd->dma_tx); 784 pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 785 } 786 787 if (!IS_ERR(pd->dma_rx)) { 788 dma_release_channel(pd->dma_rx); 789 pd->dma_rx = ERR_PTR(-EPROBE_DEFER); 790 } 791 } 792 793 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd) 794 { 795 struct resource *res; 796 resource_size_t n; 797 int k = 0, ret; 798 799 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 800 for (n = res->start; n <= res->end; n++) { 801 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, 802 0, dev_name(&dev->dev), pd); 803 if (ret) { 804 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); 805 return ret; 806 } 807 } 808 k++; 809 } 810 811 return k > 0 ? 0 : -ENOENT; 812 } 813 814 static int sh_mobile_i2c_probe(struct platform_device *dev) 815 { 816 struct sh_mobile_i2c_data *pd; 817 struct i2c_adapter *adap; 818 struct resource *res; 819 const struct sh_mobile_dt_config *config; 820 int ret; 821 u32 bus_speed; 822 823 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL); 824 if (!pd) 825 return -ENOMEM; 826 827 pd->clk = devm_clk_get(&dev->dev, NULL); 828 if (IS_ERR(pd->clk)) { 829 dev_err(&dev->dev, "cannot get clock\n"); 830 return PTR_ERR(pd->clk); 831 } 832 833 ret = sh_mobile_i2c_hook_irqs(dev, pd); 834 if (ret) 835 return ret; 836 837 pd->dev = &dev->dev; 838 platform_set_drvdata(dev, pd); 839 840 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 841 842 pd->res = res; 843 pd->reg = devm_ioremap_resource(&dev->dev, res); 844 if (IS_ERR(pd->reg)) 845 return PTR_ERR(pd->reg); 846 847 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed); 848 pd->bus_speed = (ret || !bus_speed) ? I2C_MAX_STANDARD_MODE_FREQ : bus_speed; 849 pd->clks_per_count = 1; 850 851 /* Newer variants come with two new bits in ICIC */ 852 if (resource_size(res) > 0x17) 853 pd->flags |= IIC_FLAG_HAS_ICIC67; 854 855 pm_runtime_enable(&dev->dev); 856 pm_runtime_get_sync(&dev->dev); 857 858 config = of_device_get_match_data(&dev->dev); 859 if (config) { 860 pd->clks_per_count = config->clks_per_count; 861 ret = config->setup(pd); 862 } else { 863 ret = sh_mobile_i2c_init(pd); 864 } 865 866 pm_runtime_put_sync(&dev->dev); 867 if (ret) 868 return ret; 869 870 /* Init DMA */ 871 sg_init_table(&pd->sg, 1); 872 pd->dma_direction = DMA_NONE; 873 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER); 874 875 /* setup the private data */ 876 adap = &pd->adap; 877 i2c_set_adapdata(adap, pd); 878 879 adap->owner = THIS_MODULE; 880 adap->algo = &sh_mobile_i2c_algorithm; 881 adap->quirks = &sh_mobile_i2c_quirks; 882 adap->dev.parent = &dev->dev; 883 adap->retries = 5; 884 adap->nr = dev->id; 885 adap->dev.of_node = dev->dev.of_node; 886 887 strlcpy(adap->name, dev->name, sizeof(adap->name)); 888 889 spin_lock_init(&pd->lock); 890 init_waitqueue_head(&pd->wait); 891 892 ret = i2c_add_numbered_adapter(adap); 893 if (ret < 0) { 894 sh_mobile_i2c_release_dma(pd); 895 return ret; 896 } 897 898 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed); 899 900 return 0; 901 } 902 903 static int sh_mobile_i2c_remove(struct platform_device *dev) 904 { 905 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 906 907 i2c_del_adapter(&pd->adap); 908 sh_mobile_i2c_release_dma(pd); 909 pm_runtime_disable(&dev->dev); 910 return 0; 911 } 912 913 static struct platform_driver sh_mobile_i2c_driver = { 914 .driver = { 915 .name = "i2c-sh_mobile", 916 .of_match_table = sh_mobile_i2c_dt_ids, 917 }, 918 .probe = sh_mobile_i2c_probe, 919 .remove = sh_mobile_i2c_remove, 920 }; 921 922 static int __init sh_mobile_i2c_adap_init(void) 923 { 924 return platform_driver_register(&sh_mobile_i2c_driver); 925 } 926 subsys_initcall(sh_mobile_i2c_adap_init); 927 928 static void __exit sh_mobile_i2c_adap_exit(void) 929 { 930 platform_driver_unregister(&sh_mobile_i2c_driver); 931 } 932 module_exit(sh_mobile_i2c_adap_exit); 933 934 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 935 MODULE_AUTHOR("Magnus Damm"); 936 MODULE_AUTHOR("Wolfram Sang"); 937 MODULE_LICENSE("GPL v2"); 938 MODULE_ALIAS("platform:i2c-sh_mobile"); 939