1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Device Tree Bindings for the Arasan SDHCI Controller
8
9maintainers:
10  - Adrian Hunter <adrian.hunter@intel.com>
11
12allOf:
13  - $ref: "mmc-controller.yaml#"
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: arasan,sdhci-5.1
19    then:
20      required:
21        - phys
22        - phy-names
23  - if:
24      properties:
25        compatible:
26          contains:
27            enum:
28              - xlnx,zynqmp-8.9a
29              - xlnx,versal-8.9a
30    then:
31      properties:
32        clock-output-names:
33          items:
34            - const: clk_out_sd0
35            - const: clk_in_sd0
36
37properties:
38  compatible:
39    oneOf:
40      - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
41      - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
42      - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
43      - items:
44          - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
45          - const: arasan,sdhci-5.1
46        description:
47          For this device it is strongly suggested to include
48          arasan,soc-ctl-syscon.
49      - items:
50          - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
51          - const: arasan,sdhci-8.9a
52        description:
53          For this device it is strongly suggested to include
54          clock-output-names and '#clock-cells'.
55      - items:
56          - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
57          - const: arasan,sdhci-8.9a
58        description:
59          For this device it is strongly suggested to include
60          clock-output-names and '#clock-cells'.
61      - items:
62          - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
63          - const: arasan,sdhci-5.1
64        description:
65          For this device it is strongly suggested to include
66          arasan,soc-ctl-syscon.
67      - items:
68          - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
69          - const: arasan,sdhci-5.1
70        description:
71          For this device it is strongly suggested to include
72          arasan,soc-ctl-syscon.
73      - items:
74          - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
75          - const: arasan,sdhci-5.1
76        description:
77          For this device it is strongly suggested to include
78          arasan,soc-ctl-syscon.
79      - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
80        description:
81          For this device it is strongly suggested to include
82          arasan,soc-ctl-syscon.
83      - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
84        description:
85          For this device it is strongly suggested to include
86          arasan,soc-ctl-syscon.
87
88  reg:
89    maxItems: 1
90
91  clocks:
92    minItems: 2
93    maxItems: 3
94
95  clock-names:
96    minItems: 2
97    items:
98      - const: clk_xin
99      - const: clk_ahb
100      - const: gate
101
102  interrupts:
103    maxItems: 1
104
105  phys:
106    maxItems: 1
107
108  phy-names:
109    const: phy_arasan
110
111  arasan,soc-ctl-syscon:
112    $ref: /schemas/types.yaml#/definitions/phandle
113    description:
114      A phandle to a syscon device (see ../mfd/syscon.txt) used to access
115      core corecfg registers. Offsets of registers in this syscon are
116      determined based on the main compatible string for the device.
117
118  clock-output-names:
119    minItems: 1
120    maxItems: 2
121    description:
122      Name of the card clock which will be exposed by this device.
123
124  '#clock-cells':
125    enum: [0, 1]
126    description:
127      With this property in place we will export one or two clocks
128      representing the Card Clock. These clocks are expected to be
129      consumed by our PHY.
130
131  xlnx,fails-without-test-cd:
132    $ref: /schemas/types.yaml#/definitions/flag
133    description:
134      When present, the controller doesn't work when the CD line is not
135      connected properly, and the line is not connected properly.
136      Test mode can be used to force the controller to function.
137
138  xlnx,int-clock-stable-broken:
139    $ref: /schemas/types.yaml#/definitions/flag
140    description:
141      When present, the controller always reports that the internal clock
142      is stable even when it is not.
143
144  xlnx,mio-bank:
145    $ref: /schemas/types.yaml#/definitions/uint32
146    enum: [0, 2]
147    default: 0
148    description:
149      The MIO bank number in which the command and data lines are configured.
150
151dependencies:
152  clock-output-names: [ '#clock-cells' ]
153  '#clock-cells': [ clock-output-names ]
154
155required:
156  - compatible
157  - reg
158  - interrupts
159  - clocks
160  - clock-names
161
162unevaluatedProperties: false
163
164examples:
165  - |
166    mmc@e0100000 {
167          compatible = "arasan,sdhci-8.9a";
168          reg = <0xe0100000 0x1000>;
169          clock-names = "clk_xin", "clk_ahb";
170          clocks = <&clkc 21>, <&clkc 32>;
171          interrupt-parent = <&gic>;
172          interrupts = <0 24 4>;
173    };
174
175  - |
176    mmc@e2800000 {
177          compatible = "arasan,sdhci-5.1";
178          reg = <0xe2800000 0x1000>;
179          clock-names = "clk_xin", "clk_ahb";
180          clocks = <&cru 8>, <&cru 18>;
181          interrupt-parent = <&gic>;
182          interrupts = <0 24 4>;
183          phys = <&emmc_phy>;
184          phy-names = "phy_arasan";
185    };
186
187  - |
188    #include <dt-bindings/clock/rk3399-cru.h>
189    #include <dt-bindings/interrupt-controller/arm-gic.h>
190    #include <dt-bindings/interrupt-controller/irq.h>
191    mmc@fe330000 {
192          compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
193          reg = <0xfe330000 0x10000>;
194          interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
195          clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
196          clock-names = "clk_xin", "clk_ahb";
197          arasan,soc-ctl-syscon = <&grf>;
198          assigned-clocks = <&cru SCLK_EMMC>;
199          assigned-clock-rates = <200000000>;
200          clock-output-names = "emmc_cardclock";
201          phys = <&emmc_phy>;
202          phy-names = "phy_arasan";
203          #clock-cells = <0>;
204    };
205
206  - |
207    mmc@ff160000 {
208          compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
209          interrupt-parent = <&gic>;
210          interrupts = <0 48 4>;
211          reg = <0xff160000 0x1000>;
212          clocks = <&clk200>, <&clk200>;
213          clock-names = "clk_xin", "clk_ahb";
214          clock-output-names = "clk_out_sd0", "clk_in_sd0";
215          #clock-cells = <1>;
216          clk-phase-sd-hs = <63>, <72>;
217    };
218
219  - |
220    mmc@f1040000 {
221          compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
222          interrupt-parent = <&gic>;
223          interrupts = <0 126 4>;
224          reg = <0xf1040000 0x10000>;
225          clocks = <&clk200>, <&clk200>;
226          clock-names = "clk_xin", "clk_ahb";
227          clock-output-names = "clk_out_sd0", "clk_in_sd0";
228          #clock-cells = <1>;
229          clk-phase-sd-hs = <132>, <60>;
230    };
231
232  - |
233    #define LGM_CLK_EMMC5
234    #define LGM_CLK_NGI
235    #define LGM_GCLK_EMMC
236    mmc@ec700000 {
237          compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
238          reg = <0xec700000 0x300>;
239          interrupt-parent = <&ioapic1>;
240          interrupts = <44 1>;
241          clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
242                   <&cgu0 LGM_GCLK_EMMC>;
243          clock-names = "clk_xin", "clk_ahb", "gate";
244          clock-output-names = "emmc_cardclock";
245          #clock-cells = <0>;
246          phys = <&emmc_phy>;
247          phy-names = "phy_arasan";
248          arasan,soc-ctl-syscon = <&sysconf>;
249    };
250
251  - |
252    #define LGM_CLK_SDIO
253    #define LGM_GCLK_SDXC
254    mmc@ec600000 {
255          compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
256          reg = <0xec600000 0x300>;
257          interrupt-parent = <&ioapic1>;
258          interrupts = <43 1>;
259          clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
260                   <&cgu0 LGM_GCLK_SDXC>;
261          clock-names = "clk_xin", "clk_ahb", "gate";
262          clock-output-names = "sdxc_cardclock";
263          #clock-cells = <0>;
264          phys = <&sdxc_phy>;
265          phy-names = "phy_arasan";
266          arasan,soc-ctl-syscon = <&sysconf>;
267    };
268
269  - |
270    #define KEEM_BAY_PSS_AUX_EMMC
271    #define KEEM_BAY_PSS_EMMC
272    mmc@33000000 {
273          compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
274          interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
275          reg = <0x33000000 0x300>;
276          clock-names = "clk_xin", "clk_ahb";
277          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
278                   <&scmi_clk KEEM_BAY_PSS_EMMC>;
279          phys = <&emmc_phy>;
280          phy-names = "phy_arasan";
281          assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
282          assigned-clock-rates = <200000000>;
283          clock-output-names = "emmc_cardclock";
284          #clock-cells = <0>;
285          arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
286    };
287
288  - |
289    #define KEEM_BAY_PSS_AUX_SD0
290    #define KEEM_BAY_PSS_SD0
291    mmc@31000000 {
292          compatible = "intel,keembay-sdhci-5.1-sd";
293          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
294          reg = <0x31000000 0x300>;
295          clock-names = "clk_xin", "clk_ahb";
296          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
297                   <&scmi_clk KEEM_BAY_PSS_SD0>;
298          arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
299    };
300