1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_ih.h" 30 #include "amdgpu_uvd.h" 31 #include "amdgpu_vce.h" 32 #include "amdgpu_ucode.h" 33 #include "atom.h" 34 #include "amd_pcie.h" 35 36 #include "gmc/gmc_8_1_d.h" 37 #include "gmc/gmc_8_1_sh_mask.h" 38 39 #include "oss/oss_3_0_d.h" 40 #include "oss/oss_3_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "gca/gfx_8_0_d.h" 46 #include "gca/gfx_8_0_sh_mask.h" 47 48 #include "smu/smu_7_1_1_d.h" 49 #include "smu/smu_7_1_1_sh_mask.h" 50 51 #include "uvd/uvd_5_0_d.h" 52 #include "uvd/uvd_5_0_sh_mask.h" 53 54 #include "vce/vce_3_0_d.h" 55 #include "vce/vce_3_0_sh_mask.h" 56 57 #include "dce/dce_10_0_d.h" 58 #include "dce/dce_10_0_sh_mask.h" 59 60 #include "vid.h" 61 #include "vi.h" 62 #include "gmc_v8_0.h" 63 #include "gmc_v7_0.h" 64 #include "gfx_v8_0.h" 65 #include "sdma_v2_4.h" 66 #include "sdma_v3_0.h" 67 #include "dce_v10_0.h" 68 #include "dce_v11_0.h" 69 #include "iceland_ih.h" 70 #include "tonga_ih.h" 71 #include "cz_ih.h" 72 #include "uvd_v5_0.h" 73 #include "uvd_v6_0.h" 74 #include "vce_v3_0.h" 75 #if defined(CONFIG_DRM_AMD_ACP) 76 #include "amdgpu_acp.h" 77 #endif 78 #include "dce_virtual.h" 79 #include "mxgpu_vi.h" 80 #include "amdgpu_dm.h" 81 82 /* 83 * Indirect registers accessor 84 */ 85 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) 86 { 87 unsigned long flags; 88 u32 r; 89 90 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 91 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 92 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 93 r = RREG32_NO_KIQ(mmPCIE_DATA); 94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 95 return r; 96 } 97 98 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 99 { 100 unsigned long flags; 101 102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 103 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 104 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 105 WREG32_NO_KIQ(mmPCIE_DATA, v); 106 (void)RREG32_NO_KIQ(mmPCIE_DATA); 107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 108 } 109 110 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 111 { 112 unsigned long flags; 113 u32 r; 114 115 spin_lock_irqsave(&adev->smc_idx_lock, flags); 116 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 117 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); 118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 119 return r; 120 } 121 122 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 123 { 124 unsigned long flags; 125 126 spin_lock_irqsave(&adev->smc_idx_lock, flags); 127 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 128 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); 129 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 130 } 131 132 /* smu_8_0_d.h */ 133 #define mmMP0PUB_IND_INDEX 0x180 134 #define mmMP0PUB_IND_DATA 0x181 135 136 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) 137 { 138 unsigned long flags; 139 u32 r; 140 141 spin_lock_irqsave(&adev->smc_idx_lock, flags); 142 WREG32(mmMP0PUB_IND_INDEX, (reg)); 143 r = RREG32(mmMP0PUB_IND_DATA); 144 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 145 return r; 146 } 147 148 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 149 { 150 unsigned long flags; 151 152 spin_lock_irqsave(&adev->smc_idx_lock, flags); 153 WREG32(mmMP0PUB_IND_INDEX, (reg)); 154 WREG32(mmMP0PUB_IND_DATA, (v)); 155 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 156 } 157 158 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 159 { 160 unsigned long flags; 161 u32 r; 162 163 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 164 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 165 r = RREG32(mmUVD_CTX_DATA); 166 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 167 return r; 168 } 169 170 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 171 { 172 unsigned long flags; 173 174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 175 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 176 WREG32(mmUVD_CTX_DATA, (v)); 177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 178 } 179 180 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) 181 { 182 unsigned long flags; 183 u32 r; 184 185 spin_lock_irqsave(&adev->didt_idx_lock, flags); 186 WREG32(mmDIDT_IND_INDEX, (reg)); 187 r = RREG32(mmDIDT_IND_DATA); 188 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 189 return r; 190 } 191 192 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 193 { 194 unsigned long flags; 195 196 spin_lock_irqsave(&adev->didt_idx_lock, flags); 197 WREG32(mmDIDT_IND_INDEX, (reg)); 198 WREG32(mmDIDT_IND_DATA, (v)); 199 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 200 } 201 202 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 203 { 204 unsigned long flags; 205 u32 r; 206 207 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 208 WREG32(mmGC_CAC_IND_INDEX, (reg)); 209 r = RREG32(mmGC_CAC_IND_DATA); 210 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 211 return r; 212 } 213 214 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 215 { 216 unsigned long flags; 217 218 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 219 WREG32(mmGC_CAC_IND_INDEX, (reg)); 220 WREG32(mmGC_CAC_IND_DATA, (v)); 221 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 222 } 223 224 225 static const u32 tonga_mgcg_cgcg_init[] = 226 { 227 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 228 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 229 mmPCIE_DATA, 0x000f0000, 0x00000000, 230 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 231 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 232 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 233 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 234 }; 235 236 static const u32 fiji_mgcg_cgcg_init[] = 237 { 238 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 239 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 240 mmPCIE_DATA, 0x000f0000, 0x00000000, 241 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 242 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 243 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 244 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 245 }; 246 247 static const u32 iceland_mgcg_cgcg_init[] = 248 { 249 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2, 250 mmPCIE_DATA, 0x000f0000, 0x00000000, 251 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0, 252 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 253 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 254 }; 255 256 static const u32 cz_mgcg_cgcg_init[] = 257 { 258 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 259 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 260 mmPCIE_DATA, 0x000f0000, 0x00000000, 261 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 262 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 263 }; 264 265 static const u32 stoney_mgcg_cgcg_init[] = 266 { 267 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, 268 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, 269 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, 270 }; 271 272 static void vi_init_golden_registers(struct amdgpu_device *adev) 273 { 274 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 275 mutex_lock(&adev->grbm_idx_mutex); 276 277 if (amdgpu_sriov_vf(adev)) { 278 xgpu_vi_init_golden_registers(adev); 279 mutex_unlock(&adev->grbm_idx_mutex); 280 return; 281 } 282 283 switch (adev->asic_type) { 284 case CHIP_TOPAZ: 285 amdgpu_device_program_register_sequence(adev, 286 iceland_mgcg_cgcg_init, 287 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 288 break; 289 case CHIP_FIJI: 290 amdgpu_device_program_register_sequence(adev, 291 fiji_mgcg_cgcg_init, 292 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 293 break; 294 case CHIP_TONGA: 295 amdgpu_device_program_register_sequence(adev, 296 tonga_mgcg_cgcg_init, 297 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 298 break; 299 case CHIP_CARRIZO: 300 amdgpu_device_program_register_sequence(adev, 301 cz_mgcg_cgcg_init, 302 ARRAY_SIZE(cz_mgcg_cgcg_init)); 303 break; 304 case CHIP_STONEY: 305 amdgpu_device_program_register_sequence(adev, 306 stoney_mgcg_cgcg_init, 307 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 308 break; 309 case CHIP_POLARIS10: 310 case CHIP_POLARIS11: 311 case CHIP_POLARIS12: 312 case CHIP_VEGAM: 313 default: 314 break; 315 } 316 mutex_unlock(&adev->grbm_idx_mutex); 317 } 318 319 /** 320 * vi_get_xclk - get the xclk 321 * 322 * @adev: amdgpu_device pointer 323 * 324 * Returns the reference clock used by the gfx engine 325 * (VI). 326 */ 327 static u32 vi_get_xclk(struct amdgpu_device *adev) 328 { 329 u32 reference_clock = adev->clock.spll.reference_freq; 330 u32 tmp; 331 332 if (adev->flags & AMD_IS_APU) 333 return reference_clock; 334 335 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) 337 return 1000; 338 339 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); 340 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) 341 return reference_clock / 4; 342 343 return reference_clock; 344 } 345 346 /** 347 * vi_srbm_select - select specific register instances 348 * 349 * @adev: amdgpu_device pointer 350 * @me: selected ME (micro engine) 351 * @pipe: pipe 352 * @queue: queue 353 * @vmid: VMID 354 * 355 * Switches the currently active registers instances. Some 356 * registers are instanced per VMID, others are instanced per 357 * me/pipe/queue combination. 358 */ 359 void vi_srbm_select(struct amdgpu_device *adev, 360 u32 me, u32 pipe, u32 queue, u32 vmid) 361 { 362 u32 srbm_gfx_cntl = 0; 363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe); 364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); 365 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid); 366 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue); 367 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 368 } 369 370 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) 371 { 372 /* todo */ 373 } 374 375 static bool vi_read_disabled_bios(struct amdgpu_device *adev) 376 { 377 u32 bus_cntl; 378 u32 d1vga_control = 0; 379 u32 d2vga_control = 0; 380 u32 vga_render_control = 0; 381 u32 rom_cntl; 382 bool r; 383 384 bus_cntl = RREG32(mmBUS_CNTL); 385 if (adev->mode_info.num_crtc) { 386 d1vga_control = RREG32(mmD1VGA_CONTROL); 387 d2vga_control = RREG32(mmD2VGA_CONTROL); 388 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 389 } 390 rom_cntl = RREG32_SMC(ixROM_CNTL); 391 392 /* enable the rom */ 393 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 394 if (adev->mode_info.num_crtc) { 395 /* Disable VGA mode */ 396 WREG32(mmD1VGA_CONTROL, 397 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 398 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 399 WREG32(mmD2VGA_CONTROL, 400 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK | 401 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK))); 402 WREG32(mmVGA_RENDER_CONTROL, 403 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 404 } 405 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 406 407 r = amdgpu_read_bios(adev); 408 409 /* restore regs */ 410 WREG32(mmBUS_CNTL, bus_cntl); 411 if (adev->mode_info.num_crtc) { 412 WREG32(mmD1VGA_CONTROL, d1vga_control); 413 WREG32(mmD2VGA_CONTROL, d2vga_control); 414 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 415 } 416 WREG32_SMC(ixROM_CNTL, rom_cntl); 417 return r; 418 } 419 420 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, 421 u8 *bios, u32 length_bytes) 422 { 423 u32 *dw_ptr; 424 unsigned long flags; 425 u32 i, length_dw; 426 427 if (bios == NULL) 428 return false; 429 if (length_bytes == 0) 430 return false; 431 /* APU vbios image is part of sbios image */ 432 if (adev->flags & AMD_IS_APU) 433 return false; 434 435 dw_ptr = (u32 *)bios; 436 length_dw = ALIGN(length_bytes, 4) / 4; 437 /* take the smc lock since we are using the smc index */ 438 spin_lock_irqsave(&adev->smc_idx_lock, flags); 439 /* set rom index to 0 */ 440 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); 441 WREG32(mmSMC_IND_DATA_11, 0); 442 /* set index to data for continous read */ 443 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); 444 for (i = 0; i < length_dw; i++) 445 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); 446 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 447 448 return true; 449 } 450 451 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { 452 {mmGRBM_STATUS}, 453 {mmGRBM_STATUS2}, 454 {mmGRBM_STATUS_SE0}, 455 {mmGRBM_STATUS_SE1}, 456 {mmGRBM_STATUS_SE2}, 457 {mmGRBM_STATUS_SE3}, 458 {mmSRBM_STATUS}, 459 {mmSRBM_STATUS2}, 460 {mmSRBM_STATUS3}, 461 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET}, 462 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET}, 463 {mmCP_STAT}, 464 {mmCP_STALLED_STAT1}, 465 {mmCP_STALLED_STAT2}, 466 {mmCP_STALLED_STAT3}, 467 {mmCP_CPF_BUSY_STAT}, 468 {mmCP_CPF_STALLED_STAT1}, 469 {mmCP_CPF_STATUS}, 470 {mmCP_CPC_BUSY_STAT}, 471 {mmCP_CPC_STALLED_STAT1}, 472 {mmCP_CPC_STATUS}, 473 {mmGB_ADDR_CONFIG}, 474 {mmMC_ARB_RAMCFG}, 475 {mmGB_TILE_MODE0}, 476 {mmGB_TILE_MODE1}, 477 {mmGB_TILE_MODE2}, 478 {mmGB_TILE_MODE3}, 479 {mmGB_TILE_MODE4}, 480 {mmGB_TILE_MODE5}, 481 {mmGB_TILE_MODE6}, 482 {mmGB_TILE_MODE7}, 483 {mmGB_TILE_MODE8}, 484 {mmGB_TILE_MODE9}, 485 {mmGB_TILE_MODE10}, 486 {mmGB_TILE_MODE11}, 487 {mmGB_TILE_MODE12}, 488 {mmGB_TILE_MODE13}, 489 {mmGB_TILE_MODE14}, 490 {mmGB_TILE_MODE15}, 491 {mmGB_TILE_MODE16}, 492 {mmGB_TILE_MODE17}, 493 {mmGB_TILE_MODE18}, 494 {mmGB_TILE_MODE19}, 495 {mmGB_TILE_MODE20}, 496 {mmGB_TILE_MODE21}, 497 {mmGB_TILE_MODE22}, 498 {mmGB_TILE_MODE23}, 499 {mmGB_TILE_MODE24}, 500 {mmGB_TILE_MODE25}, 501 {mmGB_TILE_MODE26}, 502 {mmGB_TILE_MODE27}, 503 {mmGB_TILE_MODE28}, 504 {mmGB_TILE_MODE29}, 505 {mmGB_TILE_MODE30}, 506 {mmGB_TILE_MODE31}, 507 {mmGB_MACROTILE_MODE0}, 508 {mmGB_MACROTILE_MODE1}, 509 {mmGB_MACROTILE_MODE2}, 510 {mmGB_MACROTILE_MODE3}, 511 {mmGB_MACROTILE_MODE4}, 512 {mmGB_MACROTILE_MODE5}, 513 {mmGB_MACROTILE_MODE6}, 514 {mmGB_MACROTILE_MODE7}, 515 {mmGB_MACROTILE_MODE8}, 516 {mmGB_MACROTILE_MODE9}, 517 {mmGB_MACROTILE_MODE10}, 518 {mmGB_MACROTILE_MODE11}, 519 {mmGB_MACROTILE_MODE12}, 520 {mmGB_MACROTILE_MODE13}, 521 {mmGB_MACROTILE_MODE14}, 522 {mmGB_MACROTILE_MODE15}, 523 {mmCC_RB_BACKEND_DISABLE, true}, 524 {mmGC_USER_RB_BACKEND_DISABLE, true}, 525 {mmGB_BACKEND_MAP, false}, 526 {mmPA_SC_RASTER_CONFIG, true}, 527 {mmPA_SC_RASTER_CONFIG_1, true}, 528 }; 529 530 static uint32_t vi_get_register_value(struct amdgpu_device *adev, 531 bool indexed, u32 se_num, 532 u32 sh_num, u32 reg_offset) 533 { 534 if (indexed) { 535 uint32_t val; 536 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 537 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 538 539 switch (reg_offset) { 540 case mmCC_RB_BACKEND_DISABLE: 541 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 542 case mmGC_USER_RB_BACKEND_DISABLE: 543 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 544 case mmPA_SC_RASTER_CONFIG: 545 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 546 case mmPA_SC_RASTER_CONFIG_1: 547 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; 548 } 549 550 mutex_lock(&adev->grbm_idx_mutex); 551 if (se_num != 0xffffffff || sh_num != 0xffffffff) 552 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 553 554 val = RREG32(reg_offset); 555 556 if (se_num != 0xffffffff || sh_num != 0xffffffff) 557 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 558 mutex_unlock(&adev->grbm_idx_mutex); 559 return val; 560 } else { 561 unsigned idx; 562 563 switch (reg_offset) { 564 case mmGB_ADDR_CONFIG: 565 return adev->gfx.config.gb_addr_config; 566 case mmMC_ARB_RAMCFG: 567 return adev->gfx.config.mc_arb_ramcfg; 568 case mmGB_TILE_MODE0: 569 case mmGB_TILE_MODE1: 570 case mmGB_TILE_MODE2: 571 case mmGB_TILE_MODE3: 572 case mmGB_TILE_MODE4: 573 case mmGB_TILE_MODE5: 574 case mmGB_TILE_MODE6: 575 case mmGB_TILE_MODE7: 576 case mmGB_TILE_MODE8: 577 case mmGB_TILE_MODE9: 578 case mmGB_TILE_MODE10: 579 case mmGB_TILE_MODE11: 580 case mmGB_TILE_MODE12: 581 case mmGB_TILE_MODE13: 582 case mmGB_TILE_MODE14: 583 case mmGB_TILE_MODE15: 584 case mmGB_TILE_MODE16: 585 case mmGB_TILE_MODE17: 586 case mmGB_TILE_MODE18: 587 case mmGB_TILE_MODE19: 588 case mmGB_TILE_MODE20: 589 case mmGB_TILE_MODE21: 590 case mmGB_TILE_MODE22: 591 case mmGB_TILE_MODE23: 592 case mmGB_TILE_MODE24: 593 case mmGB_TILE_MODE25: 594 case mmGB_TILE_MODE26: 595 case mmGB_TILE_MODE27: 596 case mmGB_TILE_MODE28: 597 case mmGB_TILE_MODE29: 598 case mmGB_TILE_MODE30: 599 case mmGB_TILE_MODE31: 600 idx = (reg_offset - mmGB_TILE_MODE0); 601 return adev->gfx.config.tile_mode_array[idx]; 602 case mmGB_MACROTILE_MODE0: 603 case mmGB_MACROTILE_MODE1: 604 case mmGB_MACROTILE_MODE2: 605 case mmGB_MACROTILE_MODE3: 606 case mmGB_MACROTILE_MODE4: 607 case mmGB_MACROTILE_MODE5: 608 case mmGB_MACROTILE_MODE6: 609 case mmGB_MACROTILE_MODE7: 610 case mmGB_MACROTILE_MODE8: 611 case mmGB_MACROTILE_MODE9: 612 case mmGB_MACROTILE_MODE10: 613 case mmGB_MACROTILE_MODE11: 614 case mmGB_MACROTILE_MODE12: 615 case mmGB_MACROTILE_MODE13: 616 case mmGB_MACROTILE_MODE14: 617 case mmGB_MACROTILE_MODE15: 618 idx = (reg_offset - mmGB_MACROTILE_MODE0); 619 return adev->gfx.config.macrotile_mode_array[idx]; 620 default: 621 return RREG32(reg_offset); 622 } 623 } 624 } 625 626 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, 627 u32 sh_num, u32 reg_offset, u32 *value) 628 { 629 uint32_t i; 630 631 *value = 0; 632 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { 633 bool indexed = vi_allowed_read_registers[i].grbm_indexed; 634 635 if (reg_offset != vi_allowed_read_registers[i].reg_offset) 636 continue; 637 638 *value = vi_get_register_value(adev, indexed, se_num, sh_num, 639 reg_offset); 640 return 0; 641 } 642 return -EINVAL; 643 } 644 645 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) 646 { 647 u32 i; 648 649 dev_info(adev->dev, "GPU pci config reset\n"); 650 651 /* disable BM */ 652 pci_clear_master(adev->pdev); 653 /* reset */ 654 amdgpu_device_pci_config_reset(adev); 655 656 udelay(100); 657 658 /* wait for asic to come out of reset */ 659 for (i = 0; i < adev->usec_timeout; i++) { 660 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { 661 /* enable BM */ 662 pci_set_master(adev->pdev); 663 adev->has_hw_reset = true; 664 return 0; 665 } 666 udelay(1); 667 } 668 return -EINVAL; 669 } 670 671 /** 672 * vi_asic_pci_config_reset - soft reset GPU 673 * 674 * @adev: amdgpu_device pointer 675 * 676 * Use PCI Config method to reset the GPU. 677 * 678 * Returns 0 for success. 679 */ 680 static int vi_asic_pci_config_reset(struct amdgpu_device *adev) 681 { 682 int r; 683 684 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 685 686 r = vi_gpu_pci_config_reset(adev); 687 688 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 689 690 return r; 691 } 692 693 static bool vi_asic_supports_baco(struct amdgpu_device *adev) 694 { 695 switch (adev->asic_type) { 696 case CHIP_FIJI: 697 case CHIP_TONGA: 698 case CHIP_POLARIS10: 699 case CHIP_POLARIS11: 700 case CHIP_POLARIS12: 701 case CHIP_TOPAZ: 702 return amdgpu_dpm_is_baco_supported(adev); 703 default: 704 return false; 705 } 706 } 707 708 static enum amd_reset_method 709 vi_asic_reset_method(struct amdgpu_device *adev) 710 { 711 bool baco_reset; 712 713 switch (adev->asic_type) { 714 case CHIP_FIJI: 715 case CHIP_TONGA: 716 case CHIP_POLARIS10: 717 case CHIP_POLARIS11: 718 case CHIP_POLARIS12: 719 case CHIP_TOPAZ: 720 baco_reset = amdgpu_dpm_is_baco_supported(adev); 721 break; 722 default: 723 baco_reset = false; 724 break; 725 } 726 727 if (baco_reset) 728 return AMD_RESET_METHOD_BACO; 729 else 730 return AMD_RESET_METHOD_LEGACY; 731 } 732 733 /** 734 * vi_asic_reset - soft reset GPU 735 * 736 * @adev: amdgpu_device pointer 737 * 738 * Look up which blocks are hung and attempt 739 * to reset them. 740 * Returns 0 for success. 741 */ 742 static int vi_asic_reset(struct amdgpu_device *adev) 743 { 744 int r; 745 746 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 747 r = amdgpu_dpm_baco_reset(adev); 748 } else { 749 r = vi_asic_pci_config_reset(adev); 750 } 751 752 return r; 753 } 754 755 static u32 vi_get_config_memsize(struct amdgpu_device *adev) 756 { 757 return RREG32(mmCONFIG_MEMSIZE); 758 } 759 760 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 761 u32 cntl_reg, u32 status_reg) 762 { 763 int r, i; 764 struct atom_clock_dividers dividers; 765 uint32_t tmp; 766 767 r = amdgpu_atombios_get_clock_dividers(adev, 768 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 769 clock, false, ÷rs); 770 if (r) 771 return r; 772 773 tmp = RREG32_SMC(cntl_reg); 774 775 if (adev->flags & AMD_IS_APU) 776 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK; 777 else 778 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 779 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 780 tmp |= dividers.post_divider; 781 WREG32_SMC(cntl_reg, tmp); 782 783 for (i = 0; i < 100; i++) { 784 tmp = RREG32_SMC(status_reg); 785 if (adev->flags & AMD_IS_APU) { 786 if (tmp & 0x10000) 787 break; 788 } else { 789 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK) 790 break; 791 } 792 mdelay(10); 793 } 794 if (i == 100) 795 return -ETIMEDOUT; 796 return 0; 797 } 798 799 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0 800 #define ixGNB_CLK1_STATUS 0xD822010C 801 #define ixGNB_CLK2_DFS_CNTL 0xD8220110 802 #define ixGNB_CLK2_STATUS 0xD822012C 803 #define ixGNB_CLK3_DFS_CNTL 0xD8220130 804 #define ixGNB_CLK3_STATUS 0xD822014C 805 806 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 807 { 808 int r; 809 810 if (adev->flags & AMD_IS_APU) { 811 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); 812 if (r) 813 return r; 814 815 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); 816 if (r) 817 return r; 818 } else { 819 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 820 if (r) 821 return r; 822 823 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 824 if (r) 825 return r; 826 } 827 828 return 0; 829 } 830 831 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 832 { 833 int r, i; 834 struct atom_clock_dividers dividers; 835 u32 tmp; 836 u32 reg_ctrl; 837 u32 reg_status; 838 u32 status_mask; 839 u32 reg_mask; 840 841 if (adev->flags & AMD_IS_APU) { 842 reg_ctrl = ixGNB_CLK3_DFS_CNTL; 843 reg_status = ixGNB_CLK3_STATUS; 844 status_mask = 0x00010000; 845 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK; 846 } else { 847 reg_ctrl = ixCG_ECLK_CNTL; 848 reg_status = ixCG_ECLK_STATUS; 849 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK; 850 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK; 851 } 852 853 r = amdgpu_atombios_get_clock_dividers(adev, 854 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 855 ecclk, false, ÷rs); 856 if (r) 857 return r; 858 859 for (i = 0; i < 100; i++) { 860 if (RREG32_SMC(reg_status) & status_mask) 861 break; 862 mdelay(10); 863 } 864 865 if (i == 100) 866 return -ETIMEDOUT; 867 868 tmp = RREG32_SMC(reg_ctrl); 869 tmp &= ~reg_mask; 870 tmp |= dividers.post_divider; 871 WREG32_SMC(reg_ctrl, tmp); 872 873 for (i = 0; i < 100; i++) { 874 if (RREG32_SMC(reg_status) & status_mask) 875 break; 876 mdelay(10); 877 } 878 879 if (i == 100) 880 return -ETIMEDOUT; 881 882 return 0; 883 } 884 885 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) 886 { 887 if (pci_is_root_bus(adev->pdev->bus)) 888 return; 889 890 if (amdgpu_pcie_gen2 == 0) 891 return; 892 893 if (adev->flags & AMD_IS_APU) 894 return; 895 896 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 897 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 898 return; 899 900 /* todo */ 901 } 902 903 static void vi_program_aspm(struct amdgpu_device *adev) 904 { 905 906 if (amdgpu_aspm == 0) 907 return; 908 909 /* todo */ 910 } 911 912 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, 913 bool enable) 914 { 915 u32 tmp; 916 917 /* not necessary on CZ */ 918 if (adev->flags & AMD_IS_APU) 919 return; 920 921 tmp = RREG32(mmBIF_DOORBELL_APER_EN); 922 if (enable) 923 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); 924 else 925 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); 926 927 WREG32(mmBIF_DOORBELL_APER_EN, tmp); 928 } 929 930 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 931 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9 932 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 933 934 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) 935 { 936 if (adev->flags & AMD_IS_APU) 937 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) 938 >> ATI_REV_ID_FUSE_MACRO__SHIFT; 939 else 940 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) 941 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; 942 } 943 944 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 945 { 946 if (!ring || !ring->funcs->emit_wreg) { 947 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 948 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 949 } else { 950 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 951 } 952 } 953 954 static void vi_invalidate_hdp(struct amdgpu_device *adev, 955 struct amdgpu_ring *ring) 956 { 957 if (!ring || !ring->funcs->emit_wreg) { 958 WREG32(mmHDP_DEBUG0, 1); 959 RREG32(mmHDP_DEBUG0); 960 } else { 961 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 962 } 963 } 964 965 static bool vi_need_full_reset(struct amdgpu_device *adev) 966 { 967 switch (adev->asic_type) { 968 case CHIP_CARRIZO: 969 case CHIP_STONEY: 970 /* CZ has hang issues with full reset at the moment */ 971 return false; 972 case CHIP_FIJI: 973 case CHIP_TONGA: 974 /* XXX: soft reset should work on fiji and tonga */ 975 return true; 976 case CHIP_POLARIS10: 977 case CHIP_POLARIS11: 978 case CHIP_POLARIS12: 979 case CHIP_TOPAZ: 980 default: 981 /* change this when we support soft reset */ 982 return true; 983 } 984 } 985 986 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 987 uint64_t *count1) 988 { 989 uint32_t perfctr = 0; 990 uint64_t cnt0_of, cnt1_of; 991 int tmp; 992 993 /* This reports 0 on APUs, so return to avoid writing/reading registers 994 * that may or may not be different from their GPU counterparts 995 */ 996 if (adev->flags & AMD_IS_APU) 997 return; 998 999 /* Set the 2 events that we wish to watch, defined above */ 1000 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1001 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1002 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1003 1004 /* Write to enable desired perf counters */ 1005 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1006 /* Zero out and enable the perf counters 1007 * Write 0x5: 1008 * Bit 0 = Start all counters(1) 1009 * Bit 2 = Global counter reset enable(1) 1010 */ 1011 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1012 1013 msleep(1000); 1014 1015 /* Load the shadow and disable the perf counters 1016 * Write 0x2: 1017 * Bit 0 = Stop counters(0) 1018 * Bit 1 = Load the shadow counters(1) 1019 */ 1020 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1021 1022 /* Read register values to get any >32bit overflow */ 1023 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1024 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1025 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1026 1027 /* Get the values and add the overflow */ 1028 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1029 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1030 } 1031 1032 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) 1033 { 1034 uint64_t nak_r, nak_g; 1035 1036 /* Get the number of NAKs received and generated */ 1037 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1038 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1039 1040 /* Add the total number of NAKs, i.e the number of replays */ 1041 return (nak_r + nak_g); 1042 } 1043 1044 static bool vi_need_reset_on_init(struct amdgpu_device *adev) 1045 { 1046 u32 clock_cntl, pc; 1047 1048 if (adev->flags & AMD_IS_APU) 1049 return false; 1050 1051 /* check if the SMC is already running */ 1052 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); 1053 pc = RREG32_SMC(ixSMC_PC_C); 1054 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && 1055 (0x20100 <= pc)) 1056 return true; 1057 1058 return false; 1059 } 1060 1061 static const struct amdgpu_asic_funcs vi_asic_funcs = 1062 { 1063 .read_disabled_bios = &vi_read_disabled_bios, 1064 .read_bios_from_rom = &vi_read_bios_from_rom, 1065 .read_register = &vi_read_register, 1066 .reset = &vi_asic_reset, 1067 .reset_method = &vi_asic_reset_method, 1068 .set_vga_state = &vi_vga_set_state, 1069 .get_xclk = &vi_get_xclk, 1070 .set_uvd_clocks = &vi_set_uvd_clocks, 1071 .set_vce_clocks = &vi_set_vce_clocks, 1072 .get_config_memsize = &vi_get_config_memsize, 1073 .flush_hdp = &vi_flush_hdp, 1074 .invalidate_hdp = &vi_invalidate_hdp, 1075 .need_full_reset = &vi_need_full_reset, 1076 .init_doorbell_index = &legacy_doorbell_index_init, 1077 .get_pcie_usage = &vi_get_pcie_usage, 1078 .need_reset_on_init = &vi_need_reset_on_init, 1079 .get_pcie_replay_count = &vi_get_pcie_replay_count, 1080 .supports_baco = &vi_asic_supports_baco, 1081 }; 1082 1083 #define CZ_REV_BRISTOL(rev) \ 1084 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6)) 1085 1086 static int vi_common_early_init(void *handle) 1087 { 1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1089 1090 if (adev->flags & AMD_IS_APU) { 1091 adev->smc_rreg = &cz_smc_rreg; 1092 adev->smc_wreg = &cz_smc_wreg; 1093 } else { 1094 adev->smc_rreg = &vi_smc_rreg; 1095 adev->smc_wreg = &vi_smc_wreg; 1096 } 1097 adev->pcie_rreg = &vi_pcie_rreg; 1098 adev->pcie_wreg = &vi_pcie_wreg; 1099 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 1100 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; 1101 adev->didt_rreg = &vi_didt_rreg; 1102 adev->didt_wreg = &vi_didt_wreg; 1103 adev->gc_cac_rreg = &vi_gc_cac_rreg; 1104 adev->gc_cac_wreg = &vi_gc_cac_wreg; 1105 1106 adev->asic_funcs = &vi_asic_funcs; 1107 1108 adev->rev_id = vi_get_rev_id(adev); 1109 adev->external_rev_id = 0xFF; 1110 switch (adev->asic_type) { 1111 case CHIP_TOPAZ: 1112 adev->cg_flags = 0; 1113 adev->pg_flags = 0; 1114 adev->external_rev_id = 0x1; 1115 break; 1116 case CHIP_FIJI: 1117 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1118 AMD_CG_SUPPORT_GFX_MGLS | 1119 AMD_CG_SUPPORT_GFX_RLC_LS | 1120 AMD_CG_SUPPORT_GFX_CP_LS | 1121 AMD_CG_SUPPORT_GFX_CGTS | 1122 AMD_CG_SUPPORT_GFX_CGTS_LS | 1123 AMD_CG_SUPPORT_GFX_CGCG | 1124 AMD_CG_SUPPORT_GFX_CGLS | 1125 AMD_CG_SUPPORT_SDMA_MGCG | 1126 AMD_CG_SUPPORT_SDMA_LS | 1127 AMD_CG_SUPPORT_BIF_LS | 1128 AMD_CG_SUPPORT_HDP_MGCG | 1129 AMD_CG_SUPPORT_HDP_LS | 1130 AMD_CG_SUPPORT_ROM_MGCG | 1131 AMD_CG_SUPPORT_MC_MGCG | 1132 AMD_CG_SUPPORT_MC_LS | 1133 AMD_CG_SUPPORT_UVD_MGCG; 1134 adev->pg_flags = 0; 1135 adev->external_rev_id = adev->rev_id + 0x3c; 1136 break; 1137 case CHIP_TONGA: 1138 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1139 AMD_CG_SUPPORT_GFX_CGCG | 1140 AMD_CG_SUPPORT_GFX_CGLS | 1141 AMD_CG_SUPPORT_SDMA_MGCG | 1142 AMD_CG_SUPPORT_SDMA_LS | 1143 AMD_CG_SUPPORT_BIF_LS | 1144 AMD_CG_SUPPORT_HDP_MGCG | 1145 AMD_CG_SUPPORT_HDP_LS | 1146 AMD_CG_SUPPORT_ROM_MGCG | 1147 AMD_CG_SUPPORT_MC_MGCG | 1148 AMD_CG_SUPPORT_MC_LS | 1149 AMD_CG_SUPPORT_DRM_LS | 1150 AMD_CG_SUPPORT_UVD_MGCG; 1151 adev->pg_flags = 0; 1152 adev->external_rev_id = adev->rev_id + 0x14; 1153 break; 1154 case CHIP_POLARIS11: 1155 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1156 AMD_CG_SUPPORT_GFX_RLC_LS | 1157 AMD_CG_SUPPORT_GFX_CP_LS | 1158 AMD_CG_SUPPORT_GFX_CGCG | 1159 AMD_CG_SUPPORT_GFX_CGLS | 1160 AMD_CG_SUPPORT_GFX_3D_CGCG | 1161 AMD_CG_SUPPORT_GFX_3D_CGLS | 1162 AMD_CG_SUPPORT_SDMA_MGCG | 1163 AMD_CG_SUPPORT_SDMA_LS | 1164 AMD_CG_SUPPORT_BIF_MGCG | 1165 AMD_CG_SUPPORT_BIF_LS | 1166 AMD_CG_SUPPORT_HDP_MGCG | 1167 AMD_CG_SUPPORT_HDP_LS | 1168 AMD_CG_SUPPORT_ROM_MGCG | 1169 AMD_CG_SUPPORT_MC_MGCG | 1170 AMD_CG_SUPPORT_MC_LS | 1171 AMD_CG_SUPPORT_DRM_LS | 1172 AMD_CG_SUPPORT_UVD_MGCG | 1173 AMD_CG_SUPPORT_VCE_MGCG; 1174 adev->pg_flags = 0; 1175 adev->external_rev_id = adev->rev_id + 0x5A; 1176 break; 1177 case CHIP_POLARIS10: 1178 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1179 AMD_CG_SUPPORT_GFX_RLC_LS | 1180 AMD_CG_SUPPORT_GFX_CP_LS | 1181 AMD_CG_SUPPORT_GFX_CGCG | 1182 AMD_CG_SUPPORT_GFX_CGLS | 1183 AMD_CG_SUPPORT_GFX_3D_CGCG | 1184 AMD_CG_SUPPORT_GFX_3D_CGLS | 1185 AMD_CG_SUPPORT_SDMA_MGCG | 1186 AMD_CG_SUPPORT_SDMA_LS | 1187 AMD_CG_SUPPORT_BIF_MGCG | 1188 AMD_CG_SUPPORT_BIF_LS | 1189 AMD_CG_SUPPORT_HDP_MGCG | 1190 AMD_CG_SUPPORT_HDP_LS | 1191 AMD_CG_SUPPORT_ROM_MGCG | 1192 AMD_CG_SUPPORT_MC_MGCG | 1193 AMD_CG_SUPPORT_MC_LS | 1194 AMD_CG_SUPPORT_DRM_LS | 1195 AMD_CG_SUPPORT_UVD_MGCG | 1196 AMD_CG_SUPPORT_VCE_MGCG; 1197 adev->pg_flags = 0; 1198 adev->external_rev_id = adev->rev_id + 0x50; 1199 break; 1200 case CHIP_POLARIS12: 1201 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1202 AMD_CG_SUPPORT_GFX_RLC_LS | 1203 AMD_CG_SUPPORT_GFX_CP_LS | 1204 AMD_CG_SUPPORT_GFX_CGCG | 1205 AMD_CG_SUPPORT_GFX_CGLS | 1206 AMD_CG_SUPPORT_GFX_3D_CGCG | 1207 AMD_CG_SUPPORT_GFX_3D_CGLS | 1208 AMD_CG_SUPPORT_SDMA_MGCG | 1209 AMD_CG_SUPPORT_SDMA_LS | 1210 AMD_CG_SUPPORT_BIF_MGCG | 1211 AMD_CG_SUPPORT_BIF_LS | 1212 AMD_CG_SUPPORT_HDP_MGCG | 1213 AMD_CG_SUPPORT_HDP_LS | 1214 AMD_CG_SUPPORT_ROM_MGCG | 1215 AMD_CG_SUPPORT_MC_MGCG | 1216 AMD_CG_SUPPORT_MC_LS | 1217 AMD_CG_SUPPORT_DRM_LS | 1218 AMD_CG_SUPPORT_UVD_MGCG | 1219 AMD_CG_SUPPORT_VCE_MGCG; 1220 adev->pg_flags = 0; 1221 adev->external_rev_id = adev->rev_id + 0x64; 1222 break; 1223 case CHIP_VEGAM: 1224 adev->cg_flags = 0; 1225 /*AMD_CG_SUPPORT_GFX_MGCG | 1226 AMD_CG_SUPPORT_GFX_RLC_LS | 1227 AMD_CG_SUPPORT_GFX_CP_LS | 1228 AMD_CG_SUPPORT_GFX_CGCG | 1229 AMD_CG_SUPPORT_GFX_CGLS | 1230 AMD_CG_SUPPORT_GFX_3D_CGCG | 1231 AMD_CG_SUPPORT_GFX_3D_CGLS | 1232 AMD_CG_SUPPORT_SDMA_MGCG | 1233 AMD_CG_SUPPORT_SDMA_LS | 1234 AMD_CG_SUPPORT_BIF_MGCG | 1235 AMD_CG_SUPPORT_BIF_LS | 1236 AMD_CG_SUPPORT_HDP_MGCG | 1237 AMD_CG_SUPPORT_HDP_LS | 1238 AMD_CG_SUPPORT_ROM_MGCG | 1239 AMD_CG_SUPPORT_MC_MGCG | 1240 AMD_CG_SUPPORT_MC_LS | 1241 AMD_CG_SUPPORT_DRM_LS | 1242 AMD_CG_SUPPORT_UVD_MGCG | 1243 AMD_CG_SUPPORT_VCE_MGCG;*/ 1244 adev->pg_flags = 0; 1245 adev->external_rev_id = adev->rev_id + 0x6E; 1246 break; 1247 case CHIP_CARRIZO: 1248 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1249 AMD_CG_SUPPORT_GFX_MGCG | 1250 AMD_CG_SUPPORT_GFX_MGLS | 1251 AMD_CG_SUPPORT_GFX_RLC_LS | 1252 AMD_CG_SUPPORT_GFX_CP_LS | 1253 AMD_CG_SUPPORT_GFX_CGTS | 1254 AMD_CG_SUPPORT_GFX_CGTS_LS | 1255 AMD_CG_SUPPORT_GFX_CGCG | 1256 AMD_CG_SUPPORT_GFX_CGLS | 1257 AMD_CG_SUPPORT_BIF_LS | 1258 AMD_CG_SUPPORT_HDP_MGCG | 1259 AMD_CG_SUPPORT_HDP_LS | 1260 AMD_CG_SUPPORT_SDMA_MGCG | 1261 AMD_CG_SUPPORT_SDMA_LS | 1262 AMD_CG_SUPPORT_VCE_MGCG; 1263 /* rev0 hardware requires workarounds to support PG */ 1264 adev->pg_flags = 0; 1265 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { 1266 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | 1267 AMD_PG_SUPPORT_GFX_PIPELINE | 1268 AMD_PG_SUPPORT_CP | 1269 AMD_PG_SUPPORT_UVD | 1270 AMD_PG_SUPPORT_VCE; 1271 } 1272 adev->external_rev_id = adev->rev_id + 0x1; 1273 break; 1274 case CHIP_STONEY: 1275 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1276 AMD_CG_SUPPORT_GFX_MGCG | 1277 AMD_CG_SUPPORT_GFX_MGLS | 1278 AMD_CG_SUPPORT_GFX_RLC_LS | 1279 AMD_CG_SUPPORT_GFX_CP_LS | 1280 AMD_CG_SUPPORT_GFX_CGTS | 1281 AMD_CG_SUPPORT_GFX_CGTS_LS | 1282 AMD_CG_SUPPORT_GFX_CGLS | 1283 AMD_CG_SUPPORT_BIF_LS | 1284 AMD_CG_SUPPORT_HDP_MGCG | 1285 AMD_CG_SUPPORT_HDP_LS | 1286 AMD_CG_SUPPORT_SDMA_MGCG | 1287 AMD_CG_SUPPORT_SDMA_LS | 1288 AMD_CG_SUPPORT_VCE_MGCG; 1289 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1290 AMD_PG_SUPPORT_GFX_SMG | 1291 AMD_PG_SUPPORT_GFX_PIPELINE | 1292 AMD_PG_SUPPORT_CP | 1293 AMD_PG_SUPPORT_UVD | 1294 AMD_PG_SUPPORT_VCE; 1295 adev->external_rev_id = adev->rev_id + 0x61; 1296 break; 1297 default: 1298 /* FIXME: not supported yet */ 1299 return -EINVAL; 1300 } 1301 1302 if (amdgpu_sriov_vf(adev)) { 1303 amdgpu_virt_init_setting(adev); 1304 xgpu_vi_mailbox_set_irq_funcs(adev); 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int vi_common_late_init(void *handle) 1311 { 1312 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1313 1314 if (amdgpu_sriov_vf(adev)) 1315 xgpu_vi_mailbox_get_irq(adev); 1316 1317 return 0; 1318 } 1319 1320 static int vi_common_sw_init(void *handle) 1321 { 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1323 1324 if (amdgpu_sriov_vf(adev)) 1325 xgpu_vi_mailbox_add_irq_id(adev); 1326 1327 return 0; 1328 } 1329 1330 static int vi_common_sw_fini(void *handle) 1331 { 1332 return 0; 1333 } 1334 1335 static int vi_common_hw_init(void *handle) 1336 { 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1338 1339 /* move the golden regs per IP block */ 1340 vi_init_golden_registers(adev); 1341 /* enable pcie gen2/3 link */ 1342 vi_pcie_gen3_enable(adev); 1343 /* enable aspm */ 1344 vi_program_aspm(adev); 1345 /* enable the doorbell aperture */ 1346 vi_enable_doorbell_aperture(adev, true); 1347 1348 return 0; 1349 } 1350 1351 static int vi_common_hw_fini(void *handle) 1352 { 1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1354 1355 /* enable the doorbell aperture */ 1356 vi_enable_doorbell_aperture(adev, false); 1357 1358 if (amdgpu_sriov_vf(adev)) 1359 xgpu_vi_mailbox_put_irq(adev); 1360 1361 return 0; 1362 } 1363 1364 static int vi_common_suspend(void *handle) 1365 { 1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1367 1368 return vi_common_hw_fini(adev); 1369 } 1370 1371 static int vi_common_resume(void *handle) 1372 { 1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1374 1375 return vi_common_hw_init(adev); 1376 } 1377 1378 static bool vi_common_is_idle(void *handle) 1379 { 1380 return true; 1381 } 1382 1383 static int vi_common_wait_for_idle(void *handle) 1384 { 1385 return 0; 1386 } 1387 1388 static int vi_common_soft_reset(void *handle) 1389 { 1390 return 0; 1391 } 1392 1393 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, 1394 bool enable) 1395 { 1396 uint32_t temp, data; 1397 1398 temp = data = RREG32_PCIE(ixPCIE_CNTL2); 1399 1400 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 1401 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1402 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1403 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1404 else 1405 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1406 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1407 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 1408 1409 if (temp != data) 1410 WREG32_PCIE(ixPCIE_CNTL2, data); 1411 } 1412 1413 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, 1414 bool enable) 1415 { 1416 uint32_t temp, data; 1417 1418 temp = data = RREG32(mmHDP_HOST_PATH_CNTL); 1419 1420 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1421 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1422 else 1423 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1424 1425 if (temp != data) 1426 WREG32(mmHDP_HOST_PATH_CNTL, data); 1427 } 1428 1429 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, 1430 bool enable) 1431 { 1432 uint32_t temp, data; 1433 1434 temp = data = RREG32(mmHDP_MEM_POWER_LS); 1435 1436 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1437 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1438 else 1439 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1440 1441 if (temp != data) 1442 WREG32(mmHDP_MEM_POWER_LS, data); 1443 } 1444 1445 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, 1446 bool enable) 1447 { 1448 uint32_t temp, data; 1449 1450 temp = data = RREG32(0x157a); 1451 1452 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1453 data |= 1; 1454 else 1455 data &= ~1; 1456 1457 if (temp != data) 1458 WREG32(0x157a, data); 1459 } 1460 1461 1462 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1463 bool enable) 1464 { 1465 uint32_t temp, data; 1466 1467 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 1468 1469 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1470 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1471 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1472 else 1473 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1474 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1475 1476 if (temp != data) 1477 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); 1478 } 1479 1480 static int vi_common_set_clockgating_state_by_smu(void *handle, 1481 enum amd_clockgating_state state) 1482 { 1483 uint32_t msg_id, pp_state = 0; 1484 uint32_t pp_support_state = 0; 1485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1486 1487 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { 1488 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { 1489 pp_support_state = PP_STATE_SUPPORT_LS; 1490 pp_state = PP_STATE_LS; 1491 } 1492 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { 1493 pp_support_state |= PP_STATE_SUPPORT_CG; 1494 pp_state |= PP_STATE_CG; 1495 } 1496 if (state == AMD_CG_STATE_UNGATE) 1497 pp_state = 0; 1498 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1499 PP_BLOCK_SYS_MC, 1500 pp_support_state, 1501 pp_state); 1502 if (adev->powerplay.pp_funcs->set_clockgating_by_smu) 1503 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1504 } 1505 1506 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { 1507 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { 1508 pp_support_state = PP_STATE_SUPPORT_LS; 1509 pp_state = PP_STATE_LS; 1510 } 1511 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { 1512 pp_support_state |= PP_STATE_SUPPORT_CG; 1513 pp_state |= PP_STATE_CG; 1514 } 1515 if (state == AMD_CG_STATE_UNGATE) 1516 pp_state = 0; 1517 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1518 PP_BLOCK_SYS_SDMA, 1519 pp_support_state, 1520 pp_state); 1521 if (adev->powerplay.pp_funcs->set_clockgating_by_smu) 1522 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1523 } 1524 1525 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { 1526 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1527 pp_support_state = PP_STATE_SUPPORT_LS; 1528 pp_state = PP_STATE_LS; 1529 } 1530 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { 1531 pp_support_state |= PP_STATE_SUPPORT_CG; 1532 pp_state |= PP_STATE_CG; 1533 } 1534 if (state == AMD_CG_STATE_UNGATE) 1535 pp_state = 0; 1536 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1537 PP_BLOCK_SYS_HDP, 1538 pp_support_state, 1539 pp_state); 1540 if (adev->powerplay.pp_funcs->set_clockgating_by_smu) 1541 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1542 } 1543 1544 1545 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { 1546 if (state == AMD_CG_STATE_UNGATE) 1547 pp_state = 0; 1548 else 1549 pp_state = PP_STATE_LS; 1550 1551 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1552 PP_BLOCK_SYS_BIF, 1553 PP_STATE_SUPPORT_LS, 1554 pp_state); 1555 if (adev->powerplay.pp_funcs->set_clockgating_by_smu) 1556 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1557 } 1558 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { 1559 if (state == AMD_CG_STATE_UNGATE) 1560 pp_state = 0; 1561 else 1562 pp_state = PP_STATE_CG; 1563 1564 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1565 PP_BLOCK_SYS_BIF, 1566 PP_STATE_SUPPORT_CG, 1567 pp_state); 1568 if (adev->powerplay.pp_funcs->set_clockgating_by_smu) 1569 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1570 } 1571 1572 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { 1573 1574 if (state == AMD_CG_STATE_UNGATE) 1575 pp_state = 0; 1576 else 1577 pp_state = PP_STATE_LS; 1578 1579 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1580 PP_BLOCK_SYS_DRM, 1581 PP_STATE_SUPPORT_LS, 1582 pp_state); 1583 if (adev->powerplay.pp_funcs->set_clockgating_by_smu) 1584 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1585 } 1586 1587 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { 1588 1589 if (state == AMD_CG_STATE_UNGATE) 1590 pp_state = 0; 1591 else 1592 pp_state = PP_STATE_CG; 1593 1594 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1595 PP_BLOCK_SYS_ROM, 1596 PP_STATE_SUPPORT_CG, 1597 pp_state); 1598 if (adev->powerplay.pp_funcs->set_clockgating_by_smu) 1599 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1600 } 1601 return 0; 1602 } 1603 1604 static int vi_common_set_clockgating_state(void *handle, 1605 enum amd_clockgating_state state) 1606 { 1607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1608 1609 if (amdgpu_sriov_vf(adev)) 1610 return 0; 1611 1612 switch (adev->asic_type) { 1613 case CHIP_FIJI: 1614 vi_update_bif_medium_grain_light_sleep(adev, 1615 state == AMD_CG_STATE_GATE); 1616 vi_update_hdp_medium_grain_clock_gating(adev, 1617 state == AMD_CG_STATE_GATE); 1618 vi_update_hdp_light_sleep(adev, 1619 state == AMD_CG_STATE_GATE); 1620 vi_update_rom_medium_grain_clock_gating(adev, 1621 state == AMD_CG_STATE_GATE); 1622 break; 1623 case CHIP_CARRIZO: 1624 case CHIP_STONEY: 1625 vi_update_bif_medium_grain_light_sleep(adev, 1626 state == AMD_CG_STATE_GATE); 1627 vi_update_hdp_medium_grain_clock_gating(adev, 1628 state == AMD_CG_STATE_GATE); 1629 vi_update_hdp_light_sleep(adev, 1630 state == AMD_CG_STATE_GATE); 1631 vi_update_drm_light_sleep(adev, 1632 state == AMD_CG_STATE_GATE); 1633 break; 1634 case CHIP_TONGA: 1635 case CHIP_POLARIS10: 1636 case CHIP_POLARIS11: 1637 case CHIP_POLARIS12: 1638 case CHIP_VEGAM: 1639 vi_common_set_clockgating_state_by_smu(adev, state); 1640 default: 1641 break; 1642 } 1643 return 0; 1644 } 1645 1646 static int vi_common_set_powergating_state(void *handle, 1647 enum amd_powergating_state state) 1648 { 1649 return 0; 1650 } 1651 1652 static void vi_common_get_clockgating_state(void *handle, u32 *flags) 1653 { 1654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1655 int data; 1656 1657 if (amdgpu_sriov_vf(adev)) 1658 *flags = 0; 1659 1660 /* AMD_CG_SUPPORT_BIF_LS */ 1661 data = RREG32_PCIE(ixPCIE_CNTL2); 1662 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 1663 *flags |= AMD_CG_SUPPORT_BIF_LS; 1664 1665 /* AMD_CG_SUPPORT_HDP_LS */ 1666 data = RREG32(mmHDP_MEM_POWER_LS); 1667 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1668 *flags |= AMD_CG_SUPPORT_HDP_LS; 1669 1670 /* AMD_CG_SUPPORT_HDP_MGCG */ 1671 data = RREG32(mmHDP_HOST_PATH_CNTL); 1672 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK)) 1673 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1674 1675 /* AMD_CG_SUPPORT_ROM_MGCG */ 1676 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 1677 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1678 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1679 } 1680 1681 static const struct amd_ip_funcs vi_common_ip_funcs = { 1682 .name = "vi_common", 1683 .early_init = vi_common_early_init, 1684 .late_init = vi_common_late_init, 1685 .sw_init = vi_common_sw_init, 1686 .sw_fini = vi_common_sw_fini, 1687 .hw_init = vi_common_hw_init, 1688 .hw_fini = vi_common_hw_fini, 1689 .suspend = vi_common_suspend, 1690 .resume = vi_common_resume, 1691 .is_idle = vi_common_is_idle, 1692 .wait_for_idle = vi_common_wait_for_idle, 1693 .soft_reset = vi_common_soft_reset, 1694 .set_clockgating_state = vi_common_set_clockgating_state, 1695 .set_powergating_state = vi_common_set_powergating_state, 1696 .get_clockgating_state = vi_common_get_clockgating_state, 1697 }; 1698 1699 static const struct amdgpu_ip_block_version vi_common_ip_block = 1700 { 1701 .type = AMD_IP_BLOCK_TYPE_COMMON, 1702 .major = 1, 1703 .minor = 0, 1704 .rev = 0, 1705 .funcs = &vi_common_ip_funcs, 1706 }; 1707 1708 int vi_set_ip_blocks(struct amdgpu_device *adev) 1709 { 1710 if (amdgpu_sriov_vf(adev)) 1711 adev->virt.ops = &xgpu_vi_virt_ops; 1712 1713 switch (adev->asic_type) { 1714 case CHIP_TOPAZ: 1715 /* topaz has no DCE, UVD, VCE */ 1716 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 1717 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); 1718 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); 1719 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 1720 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); 1721 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1722 if (adev->enable_virtual_display) 1723 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1724 break; 1725 case CHIP_FIJI: 1726 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 1727 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); 1728 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 1729 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 1730 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 1731 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1732 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1733 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1734 #if defined(CONFIG_DRM_AMD_DC) 1735 else if (amdgpu_device_has_dc_support(adev)) 1736 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1737 #endif 1738 else 1739 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); 1740 if (!amdgpu_sriov_vf(adev)) { 1741 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); 1742 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); 1743 } 1744 break; 1745 case CHIP_TONGA: 1746 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 1747 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 1748 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 1749 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 1750 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 1751 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1752 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1753 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1754 #if defined(CONFIG_DRM_AMD_DC) 1755 else if (amdgpu_device_has_dc_support(adev)) 1756 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1757 #endif 1758 else 1759 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); 1760 if (!amdgpu_sriov_vf(adev)) { 1761 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); 1762 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); 1763 } 1764 break; 1765 case CHIP_POLARIS10: 1766 case CHIP_POLARIS11: 1767 case CHIP_POLARIS12: 1768 case CHIP_VEGAM: 1769 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 1770 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); 1771 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 1772 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 1773 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); 1774 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1775 if (adev->enable_virtual_display) 1776 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1777 #if defined(CONFIG_DRM_AMD_DC) 1778 else if (amdgpu_device_has_dc_support(adev)) 1779 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1780 #endif 1781 else 1782 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); 1783 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); 1784 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); 1785 break; 1786 case CHIP_CARRIZO: 1787 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 1788 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 1789 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); 1790 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 1791 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 1792 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1793 if (adev->enable_virtual_display) 1794 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1795 #if defined(CONFIG_DRM_AMD_DC) 1796 else if (amdgpu_device_has_dc_support(adev)) 1797 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1798 #endif 1799 else 1800 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); 1801 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); 1802 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); 1803 #if defined(CONFIG_DRM_AMD_ACP) 1804 amdgpu_device_ip_block_add(adev, &acp_ip_block); 1805 #endif 1806 break; 1807 case CHIP_STONEY: 1808 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 1809 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 1810 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); 1811 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); 1812 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 1813 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1814 if (adev->enable_virtual_display) 1815 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1816 #if defined(CONFIG_DRM_AMD_DC) 1817 else if (amdgpu_device_has_dc_support(adev)) 1818 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1819 #endif 1820 else 1821 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); 1822 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); 1823 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); 1824 #if defined(CONFIG_DRM_AMD_ACP) 1825 amdgpu_device_ip_block_add(adev, &acp_ip_block); 1826 #endif 1827 break; 1828 default: 1829 /* FIXME: not supported yet */ 1830 return -EINVAL; 1831 } 1832 1833 return 0; 1834 } 1835 1836 void legacy_doorbell_index_init(struct amdgpu_device *adev) 1837 { 1838 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; 1839 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0; 1840 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1; 1841 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2; 1842 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3; 1843 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4; 1844 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5; 1845 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6; 1846 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7; 1847 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0; 1848 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0; 1849 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1; 1850 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH; 1851 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT; 1852 } 1853