1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <crypto/hash.h> 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "hal_tx.h" 10 #include "debug.h" 11 #include "dp_rx.h" 12 #include "peer.h" 13 14 static void ath11k_dp_htt_htc_tx_complete(struct ath11k_base *ab, 15 struct sk_buff *skb) 16 { 17 dev_kfree_skb_any(skb); 18 } 19 20 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr) 21 { 22 struct ath11k_base *ab = ar->ab; 23 struct ath11k_peer *peer; 24 25 /* TODO: Any other peer specific DP cleanup */ 26 27 spin_lock_bh(&ab->base_lock); 28 peer = ath11k_peer_find(ab, vdev_id, addr); 29 if (!peer) { 30 ath11k_warn(ab, "failed to lookup peer %pM on vdev %d\n", 31 addr, vdev_id); 32 spin_unlock_bh(&ab->base_lock); 33 return; 34 } 35 36 ath11k_peer_rx_tid_cleanup(ar, peer); 37 crypto_free_shash(peer->tfm_mmic); 38 spin_unlock_bh(&ab->base_lock); 39 } 40 41 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr) 42 { 43 struct ath11k_base *ab = ar->ab; 44 struct ath11k_peer *peer; 45 u32 reo_dest; 46 int ret = 0, tid; 47 48 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */ 49 reo_dest = ar->dp.mac_id + 1; 50 ret = ath11k_wmi_set_peer_param(ar, addr, vdev_id, 51 WMI_PEER_SET_DEFAULT_ROUTING, 52 DP_RX_HASH_ENABLE | (reo_dest << 1)); 53 54 if (ret) { 55 ath11k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n", 56 ret, addr, vdev_id); 57 return ret; 58 } 59 60 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 61 ret = ath11k_peer_rx_tid_setup(ar, addr, vdev_id, tid, 1, 0, 62 HAL_PN_TYPE_NONE); 63 if (ret) { 64 ath11k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n", 65 tid, ret); 66 goto peer_clean; 67 } 68 } 69 70 ret = ath11k_peer_rx_frag_setup(ar, addr, vdev_id); 71 if (ret) { 72 ath11k_warn(ab, "failed to setup rx defrag context\n"); 73 return ret; 74 } 75 76 /* TODO: Setup other peer specific resource used in data path */ 77 78 return 0; 79 80 peer_clean: 81 spin_lock_bh(&ab->base_lock); 82 83 peer = ath11k_peer_find(ab, vdev_id, addr); 84 if (!peer) { 85 ath11k_warn(ab, "failed to find the peer to del rx tid\n"); 86 spin_unlock_bh(&ab->base_lock); 87 return -ENOENT; 88 } 89 90 for (; tid >= 0; tid--) 91 ath11k_peer_rx_tid_delete(ar, peer, tid); 92 93 spin_unlock_bh(&ab->base_lock); 94 95 return ret; 96 } 97 98 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring) 99 { 100 if (!ring->vaddr_unaligned) 101 return; 102 103 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned, 104 ring->paddr_unaligned); 105 106 ring->vaddr_unaligned = NULL; 107 } 108 109 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 110 enum hal_ring_type type, int ring_num, 111 int mac_id, int num_entries) 112 { 113 struct hal_srng_params params = { 0 }; 114 int entry_sz = ath11k_hal_srng_get_entrysize(type); 115 int max_entries = ath11k_hal_srng_get_max_entries(type); 116 int ret; 117 118 if (max_entries < 0 || entry_sz < 0) 119 return -EINVAL; 120 121 if (num_entries > max_entries) 122 num_entries = max_entries; 123 124 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1; 125 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size, 126 &ring->paddr_unaligned, 127 GFP_KERNEL); 128 if (!ring->vaddr_unaligned) 129 return -ENOMEM; 130 131 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN); 132 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr - 133 (unsigned long)ring->vaddr_unaligned); 134 135 params.ring_base_vaddr = ring->vaddr; 136 params.ring_base_paddr = ring->paddr; 137 params.num_entries = num_entries; 138 139 switch (type) { 140 case HAL_REO_DST: 141 params.intr_batch_cntr_thres_entries = 142 HAL_SRNG_INT_BATCH_THRESHOLD_RX; 143 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 144 break; 145 case HAL_RXDMA_BUF: 146 case HAL_RXDMA_MONITOR_BUF: 147 case HAL_RXDMA_MONITOR_STATUS: 148 params.low_threshold = num_entries >> 3; 149 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 150 params.intr_batch_cntr_thres_entries = 0; 151 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 152 break; 153 case HAL_WBM2SW_RELEASE: 154 if (ring_num < 3) { 155 params.intr_batch_cntr_thres_entries = 156 HAL_SRNG_INT_BATCH_THRESHOLD_TX; 157 params.intr_timer_thres_us = 158 HAL_SRNG_INT_TIMER_THRESHOLD_TX; 159 break; 160 } 161 /* follow through when ring_num >= 3 */ 162 /* fall through */ 163 case HAL_REO_EXCEPTION: 164 case HAL_REO_REINJECT: 165 case HAL_REO_CMD: 166 case HAL_REO_STATUS: 167 case HAL_TCL_DATA: 168 case HAL_TCL_CMD: 169 case HAL_TCL_STATUS: 170 case HAL_WBM_IDLE_LINK: 171 case HAL_SW2WBM_RELEASE: 172 case HAL_RXDMA_DST: 173 case HAL_RXDMA_MONITOR_DST: 174 case HAL_RXDMA_MONITOR_DESC: 175 params.intr_batch_cntr_thres_entries = 176 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER; 177 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER; 178 break; 179 case HAL_RXDMA_DIR_BUF: 180 break; 181 default: 182 ath11k_warn(ab, "Not a valid ring type in dp :%d\n", type); 183 return -EINVAL; 184 } 185 186 ret = ath11k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms); 187 if (ret < 0) { 188 ath11k_warn(ab, "failed to setup srng: %d ring_id %d\n", 189 ret, ring_num); 190 return ret; 191 } 192 193 ring->ring_id = ret; 194 195 return 0; 196 } 197 198 static void ath11k_dp_srng_common_cleanup(struct ath11k_base *ab) 199 { 200 struct ath11k_dp *dp = &ab->dp; 201 int i; 202 203 ath11k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring); 204 ath11k_dp_srng_cleanup(ab, &dp->tcl_cmd_ring); 205 ath11k_dp_srng_cleanup(ab, &dp->tcl_status_ring); 206 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 207 ath11k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring); 208 ath11k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring); 209 } 210 ath11k_dp_srng_cleanup(ab, &dp->reo_reinject_ring); 211 ath11k_dp_srng_cleanup(ab, &dp->rx_rel_ring); 212 ath11k_dp_srng_cleanup(ab, &dp->reo_except_ring); 213 ath11k_dp_srng_cleanup(ab, &dp->reo_cmd_ring); 214 ath11k_dp_srng_cleanup(ab, &dp->reo_status_ring); 215 } 216 217 static int ath11k_dp_srng_common_setup(struct ath11k_base *ab) 218 { 219 struct ath11k_dp *dp = &ab->dp; 220 struct hal_srng *srng; 221 int i, ret; 222 u32 ring_hash_map; 223 224 ret = ath11k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring, 225 HAL_SW2WBM_RELEASE, 0, 0, 226 DP_WBM_RELEASE_RING_SIZE); 227 if (ret) { 228 ath11k_warn(ab, "failed to set up wbm2sw_release ring :%d\n", 229 ret); 230 goto err; 231 } 232 233 ret = ath11k_dp_srng_setup(ab, &dp->tcl_cmd_ring, HAL_TCL_CMD, 0, 0, 234 DP_TCL_CMD_RING_SIZE); 235 if (ret) { 236 ath11k_warn(ab, "failed to set up tcl_cmd ring :%d\n", ret); 237 goto err; 238 } 239 240 ret = ath11k_dp_srng_setup(ab, &dp->tcl_status_ring, HAL_TCL_STATUS, 241 0, 0, DP_TCL_STATUS_RING_SIZE); 242 if (ret) { 243 ath11k_warn(ab, "failed to set up tcl_status ring :%d\n", ret); 244 goto err; 245 } 246 247 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 248 ret = ath11k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring, 249 HAL_TCL_DATA, i, 0, 250 DP_TCL_DATA_RING_SIZE); 251 if (ret) { 252 ath11k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n", 253 i, ret); 254 goto err; 255 } 256 257 ret = ath11k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring, 258 HAL_WBM2SW_RELEASE, i, 0, 259 DP_TX_COMP_RING_SIZE); 260 if (ret) { 261 ath11k_warn(ab, "failed to set up tcl_comp ring ring (%d) :%d\n", 262 i, ret); 263 goto err; 264 } 265 266 srng = &ab->hal.srng_list[dp->tx_ring[i].tcl_data_ring.ring_id]; 267 ath11k_hal_tx_init_data_ring(ab, srng); 268 } 269 270 ret = ath11k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT, 271 0, 0, DP_REO_REINJECT_RING_SIZE); 272 if (ret) { 273 ath11k_warn(ab, "failed to set up reo_reinject ring :%d\n", 274 ret); 275 goto err; 276 } 277 278 ret = ath11k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE, 279 3, 0, DP_RX_RELEASE_RING_SIZE); 280 if (ret) { 281 ath11k_warn(ab, "failed to set up rx_rel ring :%d\n", ret); 282 goto err; 283 } 284 285 ret = ath11k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION, 286 0, 0, DP_REO_EXCEPTION_RING_SIZE); 287 if (ret) { 288 ath11k_warn(ab, "failed to set up reo_exception ring :%d\n", 289 ret); 290 goto err; 291 } 292 293 ret = ath11k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD, 294 0, 0, DP_REO_CMD_RING_SIZE); 295 if (ret) { 296 ath11k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret); 297 goto err; 298 } 299 300 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 301 ath11k_hal_reo_init_cmd_ring(ab, srng); 302 303 ret = ath11k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS, 304 0, 0, DP_REO_STATUS_RING_SIZE); 305 if (ret) { 306 ath11k_warn(ab, "failed to set up reo_status ring :%d\n", ret); 307 goto err; 308 } 309 310 /* When hash based routing of rx packet is enabled, 32 entries to map 311 * the hash values to the ring will be configured. Each hash entry uses 312 * three bits to map to a particular ring. The ring mapping will be 313 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:Not used. 314 */ 315 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 316 HAL_HASH_ROUTING_RING_SW2 << 3 | 317 HAL_HASH_ROUTING_RING_SW3 << 6 | 318 HAL_HASH_ROUTING_RING_SW4 << 9 | 319 HAL_HASH_ROUTING_RING_SW1 << 12 | 320 HAL_HASH_ROUTING_RING_SW2 << 15 | 321 HAL_HASH_ROUTING_RING_SW3 << 18 | 322 HAL_HASH_ROUTING_RING_SW4 << 21; 323 324 ath11k_hal_reo_hw_setup(ab, ring_hash_map); 325 326 return 0; 327 328 err: 329 ath11k_dp_srng_common_cleanup(ab); 330 331 return ret; 332 } 333 334 static void ath11k_dp_scatter_idle_link_desc_cleanup(struct ath11k_base *ab) 335 { 336 struct ath11k_dp *dp = &ab->dp; 337 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 338 int i; 339 340 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) { 341 if (!slist[i].vaddr) 342 continue; 343 344 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 345 slist[i].vaddr, slist[i].paddr); 346 slist[i].vaddr = NULL; 347 } 348 } 349 350 static int ath11k_dp_scatter_idle_link_desc_setup(struct ath11k_base *ab, 351 int size, 352 u32 n_link_desc_bank, 353 u32 n_link_desc, 354 u32 last_bank_sz) 355 { 356 struct ath11k_dp *dp = &ab->dp; 357 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks; 358 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 359 u32 n_entries_per_buf; 360 int num_scatter_buf, scatter_idx; 361 struct hal_wbm_link_desc *scatter_buf; 362 int align_bytes, n_entries; 363 dma_addr_t paddr; 364 int rem_entries; 365 int i; 366 int ret = 0; 367 u32 end_offset; 368 369 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 370 ath11k_hal_srng_get_entrysize(HAL_WBM_IDLE_LINK); 371 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE); 372 373 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX) 374 return -EINVAL; 375 376 for (i = 0; i < num_scatter_buf; i++) { 377 slist[i].vaddr = dma_alloc_coherent(ab->dev, 378 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 379 &slist[i].paddr, GFP_KERNEL); 380 if (!slist[i].vaddr) { 381 ret = -ENOMEM; 382 goto err; 383 } 384 } 385 386 scatter_idx = 0; 387 scatter_buf = slist[scatter_idx].vaddr; 388 rem_entries = n_entries_per_buf; 389 390 for (i = 0; i < n_link_desc_bank; i++) { 391 align_bytes = link_desc_banks[i].vaddr - 392 link_desc_banks[i].vaddr_unaligned; 393 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) / 394 HAL_LINK_DESC_SIZE; 395 paddr = link_desc_banks[i].paddr; 396 while (n_entries) { 397 ath11k_hal_set_link_desc_addr(scatter_buf, i, paddr); 398 n_entries--; 399 paddr += HAL_LINK_DESC_SIZE; 400 if (rem_entries) { 401 rem_entries--; 402 scatter_buf++; 403 continue; 404 } 405 406 rem_entries = n_entries_per_buf; 407 scatter_idx++; 408 scatter_buf = slist[scatter_idx].vaddr; 409 } 410 } 411 412 end_offset = (scatter_buf - slist[scatter_idx].vaddr) * 413 sizeof(struct hal_wbm_link_desc); 414 ath11k_hal_setup_link_idle_list(ab, slist, num_scatter_buf, 415 n_link_desc, end_offset); 416 417 return 0; 418 419 err: 420 ath11k_dp_scatter_idle_link_desc_cleanup(ab); 421 422 return ret; 423 } 424 425 static void 426 ath11k_dp_link_desc_bank_free(struct ath11k_base *ab, 427 struct dp_link_desc_bank *link_desc_banks) 428 { 429 int i; 430 431 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) { 432 if (link_desc_banks[i].vaddr_unaligned) { 433 dma_free_coherent(ab->dev, 434 link_desc_banks[i].size, 435 link_desc_banks[i].vaddr_unaligned, 436 link_desc_banks[i].paddr_unaligned); 437 link_desc_banks[i].vaddr_unaligned = NULL; 438 } 439 } 440 } 441 442 static int ath11k_dp_link_desc_bank_alloc(struct ath11k_base *ab, 443 struct dp_link_desc_bank *desc_bank, 444 int n_link_desc_bank, 445 int last_bank_sz) 446 { 447 struct ath11k_dp *dp = &ab->dp; 448 int i; 449 int ret = 0; 450 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH; 451 452 for (i = 0; i < n_link_desc_bank; i++) { 453 if (i == (n_link_desc_bank - 1) && last_bank_sz) 454 desc_sz = last_bank_sz; 455 456 desc_bank[i].vaddr_unaligned = 457 dma_alloc_coherent(ab->dev, desc_sz, 458 &desc_bank[i].paddr_unaligned, 459 GFP_KERNEL); 460 if (!desc_bank[i].vaddr_unaligned) { 461 ret = -ENOMEM; 462 goto err; 463 } 464 465 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned, 466 HAL_LINK_DESC_ALIGN); 467 desc_bank[i].paddr = desc_bank[i].paddr_unaligned + 468 ((unsigned long)desc_bank[i].vaddr - 469 (unsigned long)desc_bank[i].vaddr_unaligned); 470 desc_bank[i].size = desc_sz; 471 } 472 473 return 0; 474 475 err: 476 ath11k_dp_link_desc_bank_free(ab, dp->link_desc_banks); 477 478 return ret; 479 } 480 481 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 482 struct dp_link_desc_bank *desc_bank, 483 u32 ring_type, struct dp_srng *ring) 484 { 485 ath11k_dp_link_desc_bank_free(ab, desc_bank); 486 487 if (ring_type != HAL_RXDMA_MONITOR_DESC) { 488 ath11k_dp_srng_cleanup(ab, ring); 489 ath11k_dp_scatter_idle_link_desc_cleanup(ab); 490 } 491 } 492 493 static int ath11k_wbm_idle_ring_setup(struct ath11k_base *ab, u32 *n_link_desc) 494 { 495 struct ath11k_dp *dp = &ab->dp; 496 u32 n_mpdu_link_desc, n_mpdu_queue_desc; 497 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc; 498 int ret = 0; 499 500 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) / 501 HAL_NUM_MPDUS_PER_LINK_DESC; 502 503 n_mpdu_queue_desc = n_mpdu_link_desc / 504 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC; 505 506 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID * 507 DP_AVG_MSDUS_PER_FLOW) / 508 HAL_NUM_TX_MSDUS_PER_LINK_DESC; 509 510 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX * 511 DP_AVG_MSDUS_PER_MPDU) / 512 HAL_NUM_RX_MSDUS_PER_LINK_DESC; 513 514 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc + 515 n_tx_msdu_link_desc + n_rx_msdu_link_desc; 516 517 if (*n_link_desc & (*n_link_desc - 1)) 518 *n_link_desc = 1 << fls(*n_link_desc); 519 520 ret = ath11k_dp_srng_setup(ab, &dp->wbm_idle_ring, 521 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc); 522 if (ret) { 523 ath11k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 524 return ret; 525 } 526 return ret; 527 } 528 529 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 530 struct dp_link_desc_bank *link_desc_banks, 531 u32 ring_type, struct hal_srng *srng, 532 u32 n_link_desc) 533 { 534 u32 tot_mem_sz; 535 u32 n_link_desc_bank, last_bank_sz; 536 u32 entry_sz, align_bytes, n_entries; 537 u32 paddr; 538 u32 *desc; 539 int i, ret; 540 541 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE; 542 tot_mem_sz += HAL_LINK_DESC_ALIGN; 543 544 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) { 545 n_link_desc_bank = 1; 546 last_bank_sz = tot_mem_sz; 547 } else { 548 n_link_desc_bank = tot_mem_sz / 549 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 550 HAL_LINK_DESC_ALIGN); 551 last_bank_sz = tot_mem_sz % 552 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 553 HAL_LINK_DESC_ALIGN); 554 555 if (last_bank_sz) 556 n_link_desc_bank += 1; 557 } 558 559 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX) 560 return -EINVAL; 561 562 ret = ath11k_dp_link_desc_bank_alloc(ab, link_desc_banks, 563 n_link_desc_bank, last_bank_sz); 564 if (ret) 565 return ret; 566 567 /* Setup link desc idle list for HW internal usage */ 568 entry_sz = ath11k_hal_srng_get_entrysize(ring_type); 569 tot_mem_sz = entry_sz * n_link_desc; 570 571 /* Setup scatter desc list when the total memory requirement is more */ 572 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH && 573 ring_type != HAL_RXDMA_MONITOR_DESC) { 574 ret = ath11k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz, 575 n_link_desc_bank, 576 n_link_desc, 577 last_bank_sz); 578 if (ret) { 579 ath11k_warn(ab, "failed to setup scatting idle list descriptor :%d\n", 580 ret); 581 goto fail_desc_bank_free; 582 } 583 584 return 0; 585 } 586 587 spin_lock_bh(&srng->lock); 588 589 ath11k_hal_srng_access_begin(ab, srng); 590 591 for (i = 0; i < n_link_desc_bank; i++) { 592 align_bytes = link_desc_banks[i].vaddr - 593 link_desc_banks[i].vaddr_unaligned; 594 n_entries = (link_desc_banks[i].size - align_bytes) / 595 HAL_LINK_DESC_SIZE; 596 paddr = link_desc_banks[i].paddr; 597 while (n_entries && 598 (desc = ath11k_hal_srng_src_get_next_entry(ab, srng))) { 599 ath11k_hal_set_link_desc_addr((struct hal_wbm_link_desc *)desc, 600 i, paddr); 601 n_entries--; 602 paddr += HAL_LINK_DESC_SIZE; 603 } 604 } 605 606 ath11k_hal_srng_access_end(ab, srng); 607 608 spin_unlock_bh(&srng->lock); 609 610 return 0; 611 612 fail_desc_bank_free: 613 ath11k_dp_link_desc_bank_free(ab, link_desc_banks); 614 615 return ret; 616 } 617 618 int ath11k_dp_service_srng(struct ath11k_base *ab, 619 struct ath11k_ext_irq_grp *irq_grp, 620 int budget) 621 { 622 struct napi_struct *napi = &irq_grp->napi; 623 int grp_id = irq_grp->grp_id; 624 int work_done = 0; 625 int i = 0; 626 int tot_work_done = 0; 627 628 while (ath11k_tx_ring_mask[grp_id] >> i) { 629 if (ath11k_tx_ring_mask[grp_id] & BIT(i)) 630 ath11k_dp_tx_completion_handler(ab, i); 631 i++; 632 } 633 634 if (ath11k_rx_err_ring_mask[grp_id]) { 635 work_done = ath11k_dp_process_rx_err(ab, napi, budget); 636 budget -= work_done; 637 tot_work_done += work_done; 638 if (budget <= 0) 639 goto done; 640 } 641 642 if (ath11k_rx_wbm_rel_ring_mask[grp_id]) { 643 work_done = ath11k_dp_rx_process_wbm_err(ab, 644 napi, 645 budget); 646 budget -= work_done; 647 tot_work_done += work_done; 648 649 if (budget <= 0) 650 goto done; 651 } 652 653 if (ath11k_rx_ring_mask[grp_id]) { 654 i = fls(ath11k_rx_ring_mask[grp_id]) - 1; 655 work_done = ath11k_dp_process_rx(ab, i, napi, 656 budget); 657 budget -= work_done; 658 tot_work_done += work_done; 659 if (budget <= 0) 660 goto done; 661 } 662 663 if (rx_mon_status_ring_mask[grp_id]) { 664 for (i = 0; i < ab->num_radios; i++) { 665 if (rx_mon_status_ring_mask[grp_id] & BIT(i)) { 666 work_done = 667 ath11k_dp_rx_process_mon_rings(ab, 668 i, napi, 669 budget); 670 budget -= work_done; 671 tot_work_done += work_done; 672 } 673 if (budget <= 0) 674 goto done; 675 } 676 } 677 678 if (ath11k_reo_status_ring_mask[grp_id]) 679 ath11k_dp_process_reo_status(ab); 680 681 for (i = 0; i < ab->num_radios; i++) { 682 if (ath11k_rxdma2host_ring_mask[grp_id] & BIT(i)) { 683 work_done = ath11k_dp_process_rxdma_err(ab, i, budget); 684 budget -= work_done; 685 tot_work_done += work_done; 686 } 687 688 if (budget <= 0) 689 goto done; 690 691 if (ath11k_host2rxdma_ring_mask[grp_id] & BIT(i)) { 692 struct ath11k_pdev_dp *dp = &ab->pdevs[i].ar->dp; 693 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 694 695 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, 0, 696 HAL_RX_BUF_RBM_SW3_BM, 697 GFP_ATOMIC); 698 } 699 } 700 /* TODO: Implement handler for other interrupts */ 701 702 done: 703 return tot_work_done; 704 } 705 EXPORT_SYMBOL(ath11k_dp_service_srng); 706 707 void ath11k_dp_pdev_free(struct ath11k_base *ab) 708 { 709 struct ath11k *ar; 710 int i; 711 712 for (i = 0; i < ab->num_radios; i++) { 713 ar = ab->pdevs[i].ar; 714 ath11k_dp_rx_pdev_free(ab, i); 715 ath11k_debug_unregister(ar); 716 ath11k_dp_rx_pdev_mon_detach(ar); 717 } 718 } 719 720 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab) 721 { 722 struct ath11k *ar; 723 struct ath11k_pdev_dp *dp; 724 int i; 725 726 for (i = 0; i < ab->num_radios; i++) { 727 ar = ab->pdevs[i].ar; 728 dp = &ar->dp; 729 dp->mac_id = i; 730 idr_init(&dp->rx_refill_buf_ring.bufs_idr); 731 spin_lock_init(&dp->rx_refill_buf_ring.idr_lock); 732 atomic_set(&dp->num_tx_pending, 0); 733 init_waitqueue_head(&dp->tx_empty_waitq); 734 idr_init(&dp->rx_mon_status_refill_ring.bufs_idr); 735 spin_lock_init(&dp->rx_mon_status_refill_ring.idr_lock); 736 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 737 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 738 } 739 } 740 741 int ath11k_dp_pdev_alloc(struct ath11k_base *ab) 742 { 743 struct ath11k *ar; 744 int ret; 745 int i; 746 747 /* TODO:Per-pdev rx ring unlike tx ring which is mapped to different AC's */ 748 for (i = 0; i < ab->num_radios; i++) { 749 ar = ab->pdevs[i].ar; 750 ret = ath11k_dp_rx_pdev_alloc(ab, i); 751 if (ret) { 752 ath11k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n", 753 i); 754 goto err; 755 } 756 ret = ath11k_dp_rx_pdev_mon_attach(ar); 757 if (ret) { 758 ath11k_warn(ab, "failed to initialize mon pdev %d\n", 759 i); 760 goto err; 761 } 762 } 763 764 return 0; 765 766 err: 767 ath11k_dp_pdev_free(ab); 768 769 return ret; 770 } 771 772 int ath11k_dp_htt_connect(struct ath11k_dp *dp) 773 { 774 struct ath11k_htc_svc_conn_req conn_req; 775 struct ath11k_htc_svc_conn_resp conn_resp; 776 int status; 777 778 memset(&conn_req, 0, sizeof(conn_req)); 779 memset(&conn_resp, 0, sizeof(conn_resp)); 780 781 conn_req.ep_ops.ep_tx_complete = ath11k_dp_htt_htc_tx_complete; 782 conn_req.ep_ops.ep_rx_complete = ath11k_dp_htt_htc_t2h_msg_handler; 783 784 /* connect to control service */ 785 conn_req.service_id = ATH11K_HTC_SVC_ID_HTT_DATA_MSG; 786 787 status = ath11k_htc_connect_service(&dp->ab->htc, &conn_req, 788 &conn_resp); 789 790 if (status) 791 return status; 792 793 dp->eid = conn_resp.eid; 794 795 return 0; 796 } 797 798 static void ath11k_dp_update_vdev_search(struct ath11k_vif *arvif) 799 { 800 /* For STA mode, enable address search index, 801 * tcl uses ast_hash value in the descriptor. 802 */ 803 switch (arvif->vdev_type) { 804 case WMI_VDEV_TYPE_STA: 805 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN; 806 arvif->search_type = HAL_TX_ADDR_SEARCH_INDEX; 807 break; 808 case WMI_VDEV_TYPE_AP: 809 case WMI_VDEV_TYPE_IBSS: 810 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN; 811 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 812 break; 813 case WMI_VDEV_TYPE_MONITOR: 814 default: 815 return; 816 } 817 } 818 819 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif) 820 { 821 arvif->tcl_metadata |= FIELD_PREP(HTT_TCL_META_DATA_TYPE, 1) | 822 FIELD_PREP(HTT_TCL_META_DATA_VDEV_ID, 823 arvif->vdev_id) | 824 FIELD_PREP(HTT_TCL_META_DATA_PDEV_ID, 825 ar->pdev->pdev_id); 826 827 /* set HTT extension valid bit to 0 by default */ 828 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT; 829 830 ath11k_dp_update_vdev_search(arvif); 831 } 832 833 static int ath11k_dp_tx_pending_cleanup(int buf_id, void *skb, void *ctx) 834 { 835 struct ath11k_base *ab = (struct ath11k_base *)ctx; 836 struct sk_buff *msdu = skb; 837 838 dma_unmap_single(ab->dev, ATH11K_SKB_CB(msdu)->paddr, msdu->len, 839 DMA_TO_DEVICE); 840 841 dev_kfree_skb_any(msdu); 842 843 return 0; 844 } 845 846 void ath11k_dp_free(struct ath11k_base *ab) 847 { 848 struct ath11k_dp *dp = &ab->dp; 849 int i; 850 851 ath11k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 852 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 853 854 ath11k_dp_srng_common_cleanup(ab); 855 856 ath11k_dp_reo_cmd_list_cleanup(ab); 857 858 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 859 spin_lock_bh(&dp->tx_ring[i].tx_idr_lock); 860 idr_for_each(&dp->tx_ring[i].txbuf_idr, 861 ath11k_dp_tx_pending_cleanup, ab); 862 idr_destroy(&dp->tx_ring[i].txbuf_idr); 863 spin_unlock_bh(&dp->tx_ring[i].tx_idr_lock); 864 kfree(dp->tx_ring[i].tx_status); 865 } 866 867 /* Deinit any SOC level resource */ 868 } 869 870 int ath11k_dp_alloc(struct ath11k_base *ab) 871 { 872 struct ath11k_dp *dp = &ab->dp; 873 struct hal_srng *srng = NULL; 874 size_t size = 0; 875 u32 n_link_desc = 0; 876 int ret; 877 int i; 878 879 dp->ab = ab; 880 881 INIT_LIST_HEAD(&dp->reo_cmd_list); 882 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list); 883 spin_lock_init(&dp->reo_cmd_lock); 884 885 dp->reo_cmd_cache_flush_count = 0; 886 887 ret = ath11k_wbm_idle_ring_setup(ab, &n_link_desc); 888 if (ret) { 889 ath11k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 890 return ret; 891 } 892 893 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id]; 894 895 ret = ath11k_dp_link_desc_setup(ab, dp->link_desc_banks, 896 HAL_WBM_IDLE_LINK, srng, n_link_desc); 897 if (ret) { 898 ath11k_warn(ab, "failed to setup link desc: %d\n", ret); 899 return ret; 900 } 901 902 ret = ath11k_dp_srng_common_setup(ab); 903 if (ret) 904 goto fail_link_desc_cleanup; 905 906 size = sizeof(struct hal_wbm_release_ring) * DP_TX_COMP_RING_SIZE; 907 908 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 909 idr_init(&dp->tx_ring[i].txbuf_idr); 910 spin_lock_init(&dp->tx_ring[i].tx_idr_lock); 911 dp->tx_ring[i].tcl_data_ring_id = i; 912 913 dp->tx_ring[i].tx_status_head = 0; 914 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1; 915 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL); 916 if (!dp->tx_ring[i].tx_status) { 917 ret = -ENOMEM; 918 goto fail_cmn_srng_cleanup; 919 } 920 } 921 922 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++) 923 ath11k_hal_tx_set_dscp_tid_map(ab, i); 924 925 /* Init any SOC level resource for DP */ 926 927 return 0; 928 929 fail_cmn_srng_cleanup: 930 ath11k_dp_srng_common_cleanup(ab); 931 932 fail_link_desc_cleanup: 933 ath11k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 934 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 935 936 return ret; 937 } 938