1 /* 2 * linux/arch/arm/mach-omap1/timer32k.c 3 * 4 * OMAP 32K Timer 5 * 6 * Copyright (C) 2004 - 2005 Nokia Corporation 7 * Partial timer rewrite and additional dynamic tick timer support by 8 * Tony Lindgen <tony@atomide.com> and 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 10 * OMAP Dual-mode timer framework support by Timo Teras 11 * 12 * MPU timer code based on the older MPU timer code for OMAP 13 * Copyright (C) 2000 RidgeRun, Inc. 14 * Author: Greg Lonnon <glonnon@ridgerun.com> 15 * 16 * This program is free software; you can redistribute it and/or modify it 17 * under the terms of the GNU General Public License as published by the 18 * Free Software Foundation; either version 2 of the License, or (at your 19 * option) any later version. 20 * 21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * You should have received a copy of the GNU General Public License along 33 * with this program; if not, write to the Free Software Foundation, Inc., 34 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/sched.h> 42 #include <linux/spinlock.h> 43 #include <linux/err.h> 44 #include <linux/clk.h> 45 #include <linux/clocksource.h> 46 #include <linux/clockchips.h> 47 #include <linux/io.h> 48 49 #include <asm/irq.h> 50 #include <asm/mach/irq.h> 51 #include <asm/mach/time.h> 52 53 #include <plat/counter-32k.h> 54 55 #include <mach/hardware.h> 56 57 #include "common.h" 58 59 /* 60 * --------------------------------------------------------------------------- 61 * 32KHz OS timer 62 * 63 * This currently works only on 16xx, as 1510 does not have the continuous 64 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track 65 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer 66 * on 1510 would be possible, but the timer would not be as accurate as 67 * with the 32KHz synchronized timer. 68 * --------------------------------------------------------------------------- 69 */ 70 71 /* 16xx specific defines */ 72 #define OMAP1_32K_TIMER_BASE 0xfffb9000 73 #define OMAP1_32KSYNC_TIMER_BASE 0xfffbc400 74 #define OMAP1_32K_TIMER_CR 0x08 75 #define OMAP1_32K_TIMER_TVR 0x00 76 #define OMAP1_32K_TIMER_TCR 0x04 77 78 #define OMAP_32K_TICKS_PER_SEC (32768) 79 80 /* 81 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 82 * so with HZ = 128, TVR = 255. 83 */ 84 #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1) 85 86 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 87 (((nr_jiffies) * (clock_rate)) / HZ) 88 89 static inline void omap_32k_timer_write(int val, int reg) 90 { 91 omap_writew(val, OMAP1_32K_TIMER_BASE + reg); 92 } 93 94 static inline void omap_32k_timer_start(unsigned long load_val) 95 { 96 if (!load_val) 97 load_val = 1; 98 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR); 99 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR); 100 } 101 102 static inline void omap_32k_timer_stop(void) 103 { 104 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR); 105 } 106 107 #define omap_32k_timer_ack_irq() 108 109 static int omap_32k_timer_set_next_event(unsigned long delta, 110 struct clock_event_device *dev) 111 { 112 omap_32k_timer_start(delta); 113 114 return 0; 115 } 116 117 static int omap_32k_timer_shutdown(struct clock_event_device *evt) 118 { 119 omap_32k_timer_stop(); 120 return 0; 121 } 122 123 static int omap_32k_timer_set_periodic(struct clock_event_device *evt) 124 { 125 omap_32k_timer_stop(); 126 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); 127 return 0; 128 } 129 130 static struct clock_event_device clockevent_32k_timer = { 131 .name = "32k-timer", 132 .features = CLOCK_EVT_FEAT_PERIODIC | 133 CLOCK_EVT_FEAT_ONESHOT, 134 .set_next_event = omap_32k_timer_set_next_event, 135 .set_state_shutdown = omap_32k_timer_shutdown, 136 .set_state_periodic = omap_32k_timer_set_periodic, 137 .set_state_oneshot = omap_32k_timer_shutdown, 138 .tick_resume = omap_32k_timer_shutdown, 139 }; 140 141 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) 142 { 143 struct clock_event_device *evt = &clockevent_32k_timer; 144 omap_32k_timer_ack_irq(); 145 146 evt->event_handler(evt); 147 148 return IRQ_HANDLED; 149 } 150 151 static __init void omap_init_32k_timer(void) 152 { 153 if (request_irq(INT_OS_TIMER, omap_32k_timer_interrupt, 154 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) 155 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); 156 157 clockevent_32k_timer.cpumask = cpumask_of(0); 158 clockevents_config_and_register(&clockevent_32k_timer, 159 OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe); 160 } 161 162 /* 163 * --------------------------------------------------------------------------- 164 * Timer initialization 165 * --------------------------------------------------------------------------- 166 */ 167 int __init omap_32k_timer_init(void) 168 { 169 int ret = -ENODEV; 170 171 if (cpu_is_omap16xx()) { 172 void __iomem *base; 173 struct clk *sync32k_ick; 174 175 base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K); 176 if (!base) { 177 pr_err("32k_counter: failed to map base addr\n"); 178 return -ENODEV; 179 } 180 181 sync32k_ick = clk_get(NULL, "omap_32ksync_ick"); 182 if (!IS_ERR(sync32k_ick)) 183 clk_enable(sync32k_ick); 184 185 ret = omap_init_clocksource_32k(base); 186 } 187 188 if (!ret) 189 omap_init_32k_timer(); 190 191 return ret; 192 } 193