1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/core.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/sd.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #define MAX_BD_NUM 1024 35 36 /*--------------------------------------------------------------------------*/ 37 /* Common Definition */ 38 /*--------------------------------------------------------------------------*/ 39 #define MSDC_BUS_1BITS 0x0 40 #define MSDC_BUS_4BITS 0x1 41 #define MSDC_BUS_8BITS 0x2 42 43 #define MSDC_BURST_64B 0x6 44 45 /*--------------------------------------------------------------------------*/ 46 /* Register Offset */ 47 /*--------------------------------------------------------------------------*/ 48 #define MSDC_CFG 0x0 49 #define MSDC_IOCON 0x04 50 #define MSDC_PS 0x08 51 #define MSDC_INT 0x0c 52 #define MSDC_INTEN 0x10 53 #define MSDC_FIFOCS 0x14 54 #define SDC_CFG 0x30 55 #define SDC_CMD 0x34 56 #define SDC_ARG 0x38 57 #define SDC_STS 0x3c 58 #define SDC_RESP0 0x40 59 #define SDC_RESP1 0x44 60 #define SDC_RESP2 0x48 61 #define SDC_RESP3 0x4c 62 #define SDC_BLK_NUM 0x50 63 #define SDC_ADV_CFG0 0x64 64 #define EMMC_IOCON 0x7c 65 #define SDC_ACMD_RESP 0x80 66 #define DMA_SA_H4BIT 0x8c 67 #define MSDC_DMA_SA 0x90 68 #define MSDC_DMA_CTRL 0x98 69 #define MSDC_DMA_CFG 0x9c 70 #define MSDC_PATCH_BIT 0xb0 71 #define MSDC_PATCH_BIT1 0xb4 72 #define MSDC_PATCH_BIT2 0xb8 73 #define MSDC_PAD_TUNE 0xec 74 #define MSDC_PAD_TUNE0 0xf0 75 #define PAD_DS_TUNE 0x188 76 #define PAD_CMD_TUNE 0x18c 77 #define EMMC50_CFG0 0x208 78 #define EMMC50_CFG3 0x220 79 #define SDC_FIFO_CFG 0x228 80 81 /*--------------------------------------------------------------------------*/ 82 /* Top Pad Register Offset */ 83 /*--------------------------------------------------------------------------*/ 84 #define EMMC_TOP_CONTROL 0x00 85 #define EMMC_TOP_CMD 0x04 86 #define EMMC50_PAD_DS_TUNE 0x0c 87 88 /*--------------------------------------------------------------------------*/ 89 /* Register Mask */ 90 /*--------------------------------------------------------------------------*/ 91 92 /* MSDC_CFG mask */ 93 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 94 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 95 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 96 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 97 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 98 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 99 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 100 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 101 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 102 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 103 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 104 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 105 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 106 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 107 108 /* MSDC_IOCON mask */ 109 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 110 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 111 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 112 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 113 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 114 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 115 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 116 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 117 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 118 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 119 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 120 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 121 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 122 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 123 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 124 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 125 126 /* MSDC_PS mask */ 127 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 128 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 129 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 130 #define MSDC_PS_DAT (0xff << 16) /* R */ 131 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 132 #define MSDC_PS_CMD (0x1 << 24) /* R */ 133 #define MSDC_PS_WP (0x1 << 31) /* R */ 134 135 /* MSDC_INT mask */ 136 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 137 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 138 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 139 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 140 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 141 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 142 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 143 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 144 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 145 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 146 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 147 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 148 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 149 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 150 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 151 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 152 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 153 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 154 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 155 156 /* MSDC_INTEN mask */ 157 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 158 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 159 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 160 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 161 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 162 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 163 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 164 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 165 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 166 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 167 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 168 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 169 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 170 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 171 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 172 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 173 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 174 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 175 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 176 177 /* MSDC_FIFOCS mask */ 178 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 179 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 180 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 181 182 /* SDC_CFG mask */ 183 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 184 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 185 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 186 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 187 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 188 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 189 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 190 191 /* SDC_STS mask */ 192 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 193 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 194 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 195 196 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 197 /* SDC_ADV_CFG0 mask */ 198 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 199 200 /* DMA_SA_H4BIT mask */ 201 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 202 203 /* MSDC_DMA_CTRL mask */ 204 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 205 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 206 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 207 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 208 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 209 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 210 211 /* MSDC_DMA_CFG mask */ 212 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 213 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 214 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 215 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 216 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 217 218 /* MSDC_PATCH_BIT mask */ 219 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 220 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 221 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 222 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 223 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 224 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 225 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 226 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 227 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 228 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 229 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 230 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 231 232 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 233 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 234 235 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 236 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 237 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 238 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 239 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 240 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 241 242 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 243 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 244 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 245 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 246 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 247 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 248 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 249 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 250 251 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 252 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 253 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 254 255 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 256 257 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 258 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 259 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 260 261 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 262 263 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 264 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 265 266 /* EMMC_TOP_CONTROL mask */ 267 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 268 #define DELAY_EN (0x1 << 1) /* RW */ 269 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 270 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 271 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 272 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 273 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 274 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 275 276 /* EMMC_TOP_CMD mask */ 277 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 278 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 279 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 280 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 281 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 282 283 #define REQ_CMD_EIO (0x1 << 0) 284 #define REQ_CMD_TMO (0x1 << 1) 285 #define REQ_DAT_ERR (0x1 << 2) 286 #define REQ_STOP_EIO (0x1 << 3) 287 #define REQ_STOP_TMO (0x1 << 4) 288 #define REQ_CMD_BUSY (0x1 << 5) 289 290 #define MSDC_PREPARE_FLAG (0x1 << 0) 291 #define MSDC_ASYNC_FLAG (0x1 << 1) 292 #define MSDC_MMAP_FLAG (0x1 << 2) 293 294 #define MTK_MMC_AUTOSUSPEND_DELAY 50 295 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 296 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 297 298 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 299 300 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 301 /*--------------------------------------------------------------------------*/ 302 /* Descriptor Structure */ 303 /*--------------------------------------------------------------------------*/ 304 struct mt_gpdma_desc { 305 u32 gpd_info; 306 #define GPDMA_DESC_HWO (0x1 << 0) 307 #define GPDMA_DESC_BDP (0x1 << 1) 308 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 309 #define GPDMA_DESC_INT (0x1 << 16) 310 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 311 #define GPDMA_DESC_PTR_H4 (0xf << 28) 312 u32 next; 313 u32 ptr; 314 u32 gpd_data_len; 315 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 316 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 317 u32 arg; 318 u32 blknum; 319 u32 cmd; 320 }; 321 322 struct mt_bdma_desc { 323 u32 bd_info; 324 #define BDMA_DESC_EOL (0x1 << 0) 325 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 326 #define BDMA_DESC_BLKPAD (0x1 << 17) 327 #define BDMA_DESC_DWPAD (0x1 << 18) 328 #define BDMA_DESC_NEXT_H4 (0xf << 24) 329 #define BDMA_DESC_PTR_H4 (0xf << 28) 330 u32 next; 331 u32 ptr; 332 u32 bd_data_len; 333 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 334 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 335 }; 336 337 struct msdc_dma { 338 struct scatterlist *sg; /* I/O scatter list */ 339 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 340 struct mt_bdma_desc *bd; /* pointer to bd array */ 341 dma_addr_t gpd_addr; /* the physical address of gpd array */ 342 dma_addr_t bd_addr; /* the physical address of bd array */ 343 }; 344 345 struct msdc_save_para { 346 u32 msdc_cfg; 347 u32 iocon; 348 u32 sdc_cfg; 349 u32 pad_tune; 350 u32 patch_bit0; 351 u32 patch_bit1; 352 u32 patch_bit2; 353 u32 pad_ds_tune; 354 u32 pad_cmd_tune; 355 u32 emmc50_cfg0; 356 u32 emmc50_cfg3; 357 u32 sdc_fifo_cfg; 358 u32 emmc_top_control; 359 u32 emmc_top_cmd; 360 u32 emmc50_pad_ds_tune; 361 }; 362 363 struct mtk_mmc_compatible { 364 u8 clk_div_bits; 365 bool recheck_sdio_irq; 366 bool hs400_tune; /* only used for MT8173 */ 367 u32 pad_tune_reg; 368 bool async_fifo; 369 bool data_tune; 370 bool busy_check; 371 bool stop_clk_fix; 372 bool enhance_rx; 373 bool support_64g; 374 bool use_internal_cd; 375 }; 376 377 struct msdc_tune_para { 378 u32 iocon; 379 u32 pad_tune; 380 u32 pad_cmd_tune; 381 u32 emmc_top_control; 382 u32 emmc_top_cmd; 383 }; 384 385 struct msdc_delay_phase { 386 u8 maxlen; 387 u8 start; 388 u8 final_phase; 389 }; 390 391 struct msdc_host { 392 struct device *dev; 393 const struct mtk_mmc_compatible *dev_comp; 394 struct mmc_host *mmc; /* mmc structure */ 395 int cmd_rsp; 396 397 spinlock_t lock; 398 struct mmc_request *mrq; 399 struct mmc_command *cmd; 400 struct mmc_data *data; 401 int error; 402 403 void __iomem *base; /* host base address */ 404 void __iomem *top_base; /* host top register base address */ 405 406 struct msdc_dma dma; /* dma channel */ 407 u64 dma_mask; 408 409 u32 timeout_ns; /* data timeout ns */ 410 u32 timeout_clks; /* data timeout clks */ 411 412 struct pinctrl *pinctrl; 413 struct pinctrl_state *pins_default; 414 struct pinctrl_state *pins_uhs; 415 struct delayed_work req_timeout; 416 int irq; /* host interrupt */ 417 418 struct clk *src_clk; /* msdc source clock */ 419 struct clk *h_clk; /* msdc h_clk */ 420 struct clk *bus_clk; /* bus clock which used to access register */ 421 struct clk *src_clk_cg; /* msdc source clock control gate */ 422 u32 mclk; /* mmc subsystem clock frequency */ 423 u32 src_clk_freq; /* source clock frequency */ 424 unsigned char timing; 425 bool vqmmc_enabled; 426 u32 latch_ck; 427 u32 hs400_ds_delay; 428 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 429 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 430 bool hs400_cmd_resp_sel_rising; 431 /* cmd response sample selection for HS400 */ 432 bool hs400_mode; /* current eMMC will run at hs400 mode */ 433 bool internal_cd; /* Use internal card-detect logic */ 434 struct msdc_save_para save_para; /* used when gate HCLK */ 435 struct msdc_tune_para def_tune_para; /* default tune setting */ 436 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 437 }; 438 439 static const struct mtk_mmc_compatible mt8135_compat = { 440 .clk_div_bits = 8, 441 .recheck_sdio_irq = false, 442 .hs400_tune = false, 443 .pad_tune_reg = MSDC_PAD_TUNE, 444 .async_fifo = false, 445 .data_tune = false, 446 .busy_check = false, 447 .stop_clk_fix = false, 448 .enhance_rx = false, 449 .support_64g = false, 450 }; 451 452 static const struct mtk_mmc_compatible mt8173_compat = { 453 .clk_div_bits = 8, 454 .recheck_sdio_irq = true, 455 .hs400_tune = true, 456 .pad_tune_reg = MSDC_PAD_TUNE, 457 .async_fifo = false, 458 .data_tune = false, 459 .busy_check = false, 460 .stop_clk_fix = false, 461 .enhance_rx = false, 462 .support_64g = false, 463 }; 464 465 static const struct mtk_mmc_compatible mt8183_compat = { 466 .clk_div_bits = 12, 467 .recheck_sdio_irq = false, 468 .hs400_tune = false, 469 .pad_tune_reg = MSDC_PAD_TUNE0, 470 .async_fifo = true, 471 .data_tune = true, 472 .busy_check = true, 473 .stop_clk_fix = true, 474 .enhance_rx = true, 475 .support_64g = true, 476 }; 477 478 static const struct mtk_mmc_compatible mt2701_compat = { 479 .clk_div_bits = 12, 480 .recheck_sdio_irq = false, 481 .hs400_tune = false, 482 .pad_tune_reg = MSDC_PAD_TUNE0, 483 .async_fifo = true, 484 .data_tune = true, 485 .busy_check = false, 486 .stop_clk_fix = false, 487 .enhance_rx = false, 488 .support_64g = false, 489 }; 490 491 static const struct mtk_mmc_compatible mt2712_compat = { 492 .clk_div_bits = 12, 493 .recheck_sdio_irq = false, 494 .hs400_tune = false, 495 .pad_tune_reg = MSDC_PAD_TUNE0, 496 .async_fifo = true, 497 .data_tune = true, 498 .busy_check = true, 499 .stop_clk_fix = true, 500 .enhance_rx = true, 501 .support_64g = true, 502 }; 503 504 static const struct mtk_mmc_compatible mt7622_compat = { 505 .clk_div_bits = 12, 506 .recheck_sdio_irq = false, 507 .hs400_tune = false, 508 .pad_tune_reg = MSDC_PAD_TUNE0, 509 .async_fifo = true, 510 .data_tune = true, 511 .busy_check = true, 512 .stop_clk_fix = true, 513 .enhance_rx = true, 514 .support_64g = false, 515 }; 516 517 static const struct mtk_mmc_compatible mt8516_compat = { 518 .clk_div_bits = 12, 519 .recheck_sdio_irq = false, 520 .hs400_tune = false, 521 .pad_tune_reg = MSDC_PAD_TUNE0, 522 .async_fifo = true, 523 .data_tune = true, 524 .busy_check = true, 525 .stop_clk_fix = true, 526 }; 527 528 static const struct mtk_mmc_compatible mt7620_compat = { 529 .clk_div_bits = 8, 530 .recheck_sdio_irq = false, 531 .hs400_tune = false, 532 .pad_tune_reg = MSDC_PAD_TUNE, 533 .async_fifo = false, 534 .data_tune = false, 535 .busy_check = false, 536 .stop_clk_fix = false, 537 .enhance_rx = false, 538 .use_internal_cd = true, 539 }; 540 541 static const struct of_device_id msdc_of_ids[] = { 542 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 543 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 544 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 545 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 546 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 547 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 548 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 549 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 550 {} 551 }; 552 MODULE_DEVICE_TABLE(of, msdc_of_ids); 553 554 static void sdr_set_bits(void __iomem *reg, u32 bs) 555 { 556 u32 val = readl(reg); 557 558 val |= bs; 559 writel(val, reg); 560 } 561 562 static void sdr_clr_bits(void __iomem *reg, u32 bs) 563 { 564 u32 val = readl(reg); 565 566 val &= ~bs; 567 writel(val, reg); 568 } 569 570 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 571 { 572 unsigned int tv = readl(reg); 573 574 tv &= ~field; 575 tv |= ((val) << (ffs((unsigned int)field) - 1)); 576 writel(tv, reg); 577 } 578 579 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 580 { 581 unsigned int tv = readl(reg); 582 583 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 584 } 585 586 static void msdc_reset_hw(struct msdc_host *host) 587 { 588 u32 val; 589 590 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 591 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 592 cpu_relax(); 593 594 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 595 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 596 cpu_relax(); 597 598 val = readl(host->base + MSDC_INT); 599 writel(val, host->base + MSDC_INT); 600 } 601 602 static void msdc_cmd_next(struct msdc_host *host, 603 struct mmc_request *mrq, struct mmc_command *cmd); 604 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 605 606 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 607 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 608 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 609 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 610 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 611 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 612 613 static u8 msdc_dma_calcs(u8 *buf, u32 len) 614 { 615 u32 i, sum = 0; 616 617 for (i = 0; i < len; i++) 618 sum += buf[i]; 619 return 0xff - (u8) sum; 620 } 621 622 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 623 struct mmc_data *data) 624 { 625 unsigned int j, dma_len; 626 dma_addr_t dma_address; 627 u32 dma_ctrl; 628 struct scatterlist *sg; 629 struct mt_gpdma_desc *gpd; 630 struct mt_bdma_desc *bd; 631 632 sg = data->sg; 633 634 gpd = dma->gpd; 635 bd = dma->bd; 636 637 /* modify gpd */ 638 gpd->gpd_info |= GPDMA_DESC_HWO; 639 gpd->gpd_info |= GPDMA_DESC_BDP; 640 /* need to clear first. use these bits to calc checksum */ 641 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 642 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 643 644 /* modify bd */ 645 for_each_sg(data->sg, sg, data->sg_count, j) { 646 dma_address = sg_dma_address(sg); 647 dma_len = sg_dma_len(sg); 648 649 /* init bd */ 650 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 651 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 652 bd[j].ptr = lower_32_bits(dma_address); 653 if (host->dev_comp->support_64g) { 654 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 655 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 656 << 28; 657 } 658 659 if (host->dev_comp->support_64g) { 660 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 661 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 662 } else { 663 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 664 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 665 } 666 667 if (j == data->sg_count - 1) /* the last bd */ 668 bd[j].bd_info |= BDMA_DESC_EOL; 669 else 670 bd[j].bd_info &= ~BDMA_DESC_EOL; 671 672 /* checksume need to clear first */ 673 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 674 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 675 } 676 677 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 678 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 679 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 680 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 681 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 682 if (host->dev_comp->support_64g) 683 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 684 upper_32_bits(dma->gpd_addr) & 0xf); 685 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 686 } 687 688 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 689 { 690 struct mmc_data *data = mrq->data; 691 692 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 693 data->host_cookie |= MSDC_PREPARE_FLAG; 694 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 695 mmc_get_dma_dir(data)); 696 } 697 } 698 699 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 700 { 701 struct mmc_data *data = mrq->data; 702 703 if (data->host_cookie & MSDC_ASYNC_FLAG) 704 return; 705 706 if (data->host_cookie & MSDC_PREPARE_FLAG) { 707 dma_unmap_sg(host->dev, data->sg, data->sg_len, 708 mmc_get_dma_dir(data)); 709 data->host_cookie &= ~MSDC_PREPARE_FLAG; 710 } 711 } 712 713 /* clock control primitives */ 714 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 715 { 716 u32 timeout, clk_ns; 717 u32 mode = 0; 718 719 host->timeout_ns = ns; 720 host->timeout_clks = clks; 721 if (host->mmc->actual_clock == 0) { 722 timeout = 0; 723 } else { 724 clk_ns = 1000000000UL / host->mmc->actual_clock; 725 timeout = (ns + clk_ns - 1) / clk_ns + clks; 726 /* in 1048576 sclk cycle unit */ 727 timeout = (timeout + (0x1 << 20) - 1) >> 20; 728 if (host->dev_comp->clk_div_bits == 8) 729 sdr_get_field(host->base + MSDC_CFG, 730 MSDC_CFG_CKMOD, &mode); 731 else 732 sdr_get_field(host->base + MSDC_CFG, 733 MSDC_CFG_CKMOD_EXTRA, &mode); 734 /*DDR mode will double the clk cycles for data timeout */ 735 timeout = mode >= 2 ? timeout * 2 : timeout; 736 timeout = timeout > 1 ? timeout - 1 : 0; 737 timeout = timeout > 255 ? 255 : timeout; 738 } 739 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 740 } 741 742 static void msdc_gate_clock(struct msdc_host *host) 743 { 744 clk_disable_unprepare(host->src_clk_cg); 745 clk_disable_unprepare(host->src_clk); 746 clk_disable_unprepare(host->bus_clk); 747 clk_disable_unprepare(host->h_clk); 748 } 749 750 static void msdc_ungate_clock(struct msdc_host *host) 751 { 752 clk_prepare_enable(host->h_clk); 753 clk_prepare_enable(host->bus_clk); 754 clk_prepare_enable(host->src_clk); 755 clk_prepare_enable(host->src_clk_cg); 756 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 757 cpu_relax(); 758 } 759 760 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 761 { 762 u32 mode; 763 u32 flags; 764 u32 div; 765 u32 sclk; 766 u32 tune_reg = host->dev_comp->pad_tune_reg; 767 768 if (!hz) { 769 dev_dbg(host->dev, "set mclk to 0\n"); 770 host->mclk = 0; 771 host->mmc->actual_clock = 0; 772 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 773 return; 774 } 775 776 flags = readl(host->base + MSDC_INTEN); 777 sdr_clr_bits(host->base + MSDC_INTEN, flags); 778 if (host->dev_comp->clk_div_bits == 8) 779 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 780 else 781 sdr_clr_bits(host->base + MSDC_CFG, 782 MSDC_CFG_HS400_CK_MODE_EXTRA); 783 if (timing == MMC_TIMING_UHS_DDR50 || 784 timing == MMC_TIMING_MMC_DDR52 || 785 timing == MMC_TIMING_MMC_HS400) { 786 if (timing == MMC_TIMING_MMC_HS400) 787 mode = 0x3; 788 else 789 mode = 0x2; /* ddr mode and use divisor */ 790 791 if (hz >= (host->src_clk_freq >> 2)) { 792 div = 0; /* mean div = 1/4 */ 793 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 794 } else { 795 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 796 sclk = (host->src_clk_freq >> 2) / div; 797 div = (div >> 1); 798 } 799 800 if (timing == MMC_TIMING_MMC_HS400 && 801 hz >= (host->src_clk_freq >> 1)) { 802 if (host->dev_comp->clk_div_bits == 8) 803 sdr_set_bits(host->base + MSDC_CFG, 804 MSDC_CFG_HS400_CK_MODE); 805 else 806 sdr_set_bits(host->base + MSDC_CFG, 807 MSDC_CFG_HS400_CK_MODE_EXTRA); 808 sclk = host->src_clk_freq >> 1; 809 div = 0; /* div is ignore when bit18 is set */ 810 } 811 } else if (hz >= host->src_clk_freq) { 812 mode = 0x1; /* no divisor */ 813 div = 0; 814 sclk = host->src_clk_freq; 815 } else { 816 mode = 0x0; /* use divisor */ 817 if (hz >= (host->src_clk_freq >> 1)) { 818 div = 0; /* mean div = 1/2 */ 819 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 820 } else { 821 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 822 sclk = (host->src_clk_freq >> 2) / div; 823 } 824 } 825 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 826 /* 827 * As src_clk/HCLK use the same bit to gate/ungate, 828 * So if want to only gate src_clk, need gate its parent(mux). 829 */ 830 if (host->src_clk_cg) 831 clk_disable_unprepare(host->src_clk_cg); 832 else 833 clk_disable_unprepare(clk_get_parent(host->src_clk)); 834 if (host->dev_comp->clk_div_bits == 8) 835 sdr_set_field(host->base + MSDC_CFG, 836 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 837 (mode << 8) | div); 838 else 839 sdr_set_field(host->base + MSDC_CFG, 840 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 841 (mode << 12) | div); 842 if (host->src_clk_cg) 843 clk_prepare_enable(host->src_clk_cg); 844 else 845 clk_prepare_enable(clk_get_parent(host->src_clk)); 846 847 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 848 cpu_relax(); 849 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 850 host->mmc->actual_clock = sclk; 851 host->mclk = hz; 852 host->timing = timing; 853 /* need because clk changed. */ 854 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 855 sdr_set_bits(host->base + MSDC_INTEN, flags); 856 857 /* 858 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 859 * tune result of hs200/200Mhz is not suitable for 50Mhz 860 */ 861 if (host->mmc->actual_clock <= 52000000) { 862 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 863 if (host->top_base) { 864 writel(host->def_tune_para.emmc_top_control, 865 host->top_base + EMMC_TOP_CONTROL); 866 writel(host->def_tune_para.emmc_top_cmd, 867 host->top_base + EMMC_TOP_CMD); 868 } else { 869 writel(host->def_tune_para.pad_tune, 870 host->base + tune_reg); 871 } 872 } else { 873 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 874 writel(host->saved_tune_para.pad_cmd_tune, 875 host->base + PAD_CMD_TUNE); 876 if (host->top_base) { 877 writel(host->saved_tune_para.emmc_top_control, 878 host->top_base + EMMC_TOP_CONTROL); 879 writel(host->saved_tune_para.emmc_top_cmd, 880 host->top_base + EMMC_TOP_CMD); 881 } else { 882 writel(host->saved_tune_para.pad_tune, 883 host->base + tune_reg); 884 } 885 } 886 887 if (timing == MMC_TIMING_MMC_HS400 && 888 host->dev_comp->hs400_tune) 889 sdr_set_field(host->base + tune_reg, 890 MSDC_PAD_TUNE_CMDRRDLY, 891 host->hs400_cmd_int_delay); 892 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, 893 timing); 894 } 895 896 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 897 struct mmc_request *mrq, struct mmc_command *cmd) 898 { 899 u32 resp; 900 901 switch (mmc_resp_type(cmd)) { 902 /* Actually, R1, R5, R6, R7 are the same */ 903 case MMC_RSP_R1: 904 resp = 0x1; 905 break; 906 case MMC_RSP_R1B: 907 resp = 0x7; 908 break; 909 case MMC_RSP_R2: 910 resp = 0x2; 911 break; 912 case MMC_RSP_R3: 913 resp = 0x3; 914 break; 915 case MMC_RSP_NONE: 916 default: 917 resp = 0x0; 918 break; 919 } 920 921 return resp; 922 } 923 924 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 925 struct mmc_request *mrq, struct mmc_command *cmd) 926 { 927 /* rawcmd : 928 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 929 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 930 */ 931 u32 opcode = cmd->opcode; 932 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 933 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 934 935 host->cmd_rsp = resp; 936 937 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 938 opcode == MMC_STOP_TRANSMISSION) 939 rawcmd |= (0x1 << 14); 940 else if (opcode == SD_SWITCH_VOLTAGE) 941 rawcmd |= (0x1 << 30); 942 else if (opcode == SD_APP_SEND_SCR || 943 opcode == SD_APP_SEND_NUM_WR_BLKS || 944 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 945 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 946 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 947 rawcmd |= (0x1 << 11); 948 949 if (cmd->data) { 950 struct mmc_data *data = cmd->data; 951 952 if (mmc_op_multi(opcode)) { 953 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 954 !(mrq->sbc->arg & 0xFFFF0000)) 955 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 956 } 957 958 rawcmd |= ((data->blksz & 0xFFF) << 16); 959 if (data->flags & MMC_DATA_WRITE) 960 rawcmd |= (0x1 << 13); 961 if (data->blocks > 1) 962 rawcmd |= (0x2 << 11); 963 else 964 rawcmd |= (0x1 << 11); 965 /* Always use dma mode */ 966 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 967 968 if (host->timeout_ns != data->timeout_ns || 969 host->timeout_clks != data->timeout_clks) 970 msdc_set_timeout(host, data->timeout_ns, 971 data->timeout_clks); 972 973 writel(data->blocks, host->base + SDC_BLK_NUM); 974 } 975 return rawcmd; 976 } 977 978 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 979 struct mmc_command *cmd, struct mmc_data *data) 980 { 981 bool read; 982 983 WARN_ON(host->data); 984 host->data = data; 985 read = data->flags & MMC_DATA_READ; 986 987 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 988 msdc_dma_setup(host, &host->dma, data); 989 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 990 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 991 dev_dbg(host->dev, "DMA start\n"); 992 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 993 __func__, cmd->opcode, data->blocks, read); 994 } 995 996 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 997 struct mmc_command *cmd) 998 { 999 u32 *rsp = cmd->resp; 1000 1001 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1002 1003 if (events & MSDC_INT_ACMDRDY) { 1004 cmd->error = 0; 1005 } else { 1006 msdc_reset_hw(host); 1007 if (events & MSDC_INT_ACMDCRCERR) { 1008 cmd->error = -EILSEQ; 1009 host->error |= REQ_STOP_EIO; 1010 } else if (events & MSDC_INT_ACMDTMO) { 1011 cmd->error = -ETIMEDOUT; 1012 host->error |= REQ_STOP_TMO; 1013 } 1014 dev_err(host->dev, 1015 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1016 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1017 } 1018 return cmd->error; 1019 } 1020 1021 /** 1022 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1023 * 1024 * Host controller may lost interrupt in some special case. 1025 * Add SDIO irq recheck mechanism to make sure all interrupts 1026 * can be processed immediately 1027 * 1028 */ 1029 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1030 { 1031 u32 reg_int, reg_inten, reg_ps; 1032 1033 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 1034 reg_inten = readl(host->base + MSDC_INTEN); 1035 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1036 reg_int = readl(host->base + MSDC_INT); 1037 reg_ps = readl(host->base + MSDC_PS); 1038 if (!(reg_int & MSDC_INT_SDIOIRQ || 1039 reg_ps & MSDC_PS_DATA1)) { 1040 __msdc_enable_sdio_irq(host, 0); 1041 sdio_signal_irq(host->mmc); 1042 } 1043 } 1044 } 1045 } 1046 1047 static void msdc_track_cmd_data(struct msdc_host *host, 1048 struct mmc_command *cmd, struct mmc_data *data) 1049 { 1050 if (host->error) 1051 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1052 __func__, cmd->opcode, cmd->arg, host->error); 1053 } 1054 1055 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1056 { 1057 unsigned long flags; 1058 bool ret; 1059 1060 ret = cancel_delayed_work(&host->req_timeout); 1061 if (!ret) { 1062 /* delay work already running */ 1063 return; 1064 } 1065 spin_lock_irqsave(&host->lock, flags); 1066 host->mrq = NULL; 1067 spin_unlock_irqrestore(&host->lock, flags); 1068 1069 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1070 if (mrq->data) 1071 msdc_unprepare_data(host, mrq); 1072 if (host->error) 1073 msdc_reset_hw(host); 1074 mmc_request_done(host->mmc, mrq); 1075 if (host->dev_comp->recheck_sdio_irq) 1076 msdc_recheck_sdio_irq(host); 1077 } 1078 1079 /* returns true if command is fully handled; returns false otherwise */ 1080 static bool msdc_cmd_done(struct msdc_host *host, int events, 1081 struct mmc_request *mrq, struct mmc_command *cmd) 1082 { 1083 bool done = false; 1084 bool sbc_error; 1085 unsigned long flags; 1086 u32 *rsp = cmd->resp; 1087 1088 if (mrq->sbc && cmd == mrq->cmd && 1089 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1090 | MSDC_INT_ACMDTMO))) 1091 msdc_auto_cmd_done(host, events, mrq->sbc); 1092 1093 sbc_error = mrq->sbc && mrq->sbc->error; 1094 1095 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1096 | MSDC_INT_RSPCRCERR 1097 | MSDC_INT_CMDTMO))) 1098 return done; 1099 1100 spin_lock_irqsave(&host->lock, flags); 1101 done = !host->cmd; 1102 host->cmd = NULL; 1103 spin_unlock_irqrestore(&host->lock, flags); 1104 1105 if (done) 1106 return true; 1107 1108 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1109 1110 if (cmd->flags & MMC_RSP_PRESENT) { 1111 if (cmd->flags & MMC_RSP_136) { 1112 rsp[0] = readl(host->base + SDC_RESP3); 1113 rsp[1] = readl(host->base + SDC_RESP2); 1114 rsp[2] = readl(host->base + SDC_RESP1); 1115 rsp[3] = readl(host->base + SDC_RESP0); 1116 } else { 1117 rsp[0] = readl(host->base + SDC_RESP0); 1118 } 1119 } 1120 1121 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1122 if (events & MSDC_INT_CMDTMO || 1123 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1124 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1125 /* 1126 * should not clear fifo/interrupt as the tune data 1127 * may have alreay come when cmd19/cmd21 gets response 1128 * CRC error. 1129 */ 1130 msdc_reset_hw(host); 1131 if (events & MSDC_INT_RSPCRCERR) { 1132 cmd->error = -EILSEQ; 1133 host->error |= REQ_CMD_EIO; 1134 } else if (events & MSDC_INT_CMDTMO) { 1135 cmd->error = -ETIMEDOUT; 1136 host->error |= REQ_CMD_TMO; 1137 } 1138 } 1139 if (cmd->error) 1140 dev_dbg(host->dev, 1141 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1142 __func__, cmd->opcode, cmd->arg, rsp[0], 1143 cmd->error); 1144 1145 msdc_cmd_next(host, mrq, cmd); 1146 return true; 1147 } 1148 1149 /* It is the core layer's responsibility to ensure card status 1150 * is correct before issue a request. but host design do below 1151 * checks recommended. 1152 */ 1153 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1154 struct mmc_request *mrq, struct mmc_command *cmd) 1155 { 1156 /* The max busy time we can endure is 20ms */ 1157 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1158 1159 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1160 time_before(jiffies, tmo)) 1161 cpu_relax(); 1162 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1163 dev_err(host->dev, "CMD bus busy detected\n"); 1164 host->error |= REQ_CMD_BUSY; 1165 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1166 return false; 1167 } 1168 1169 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1170 tmo = jiffies + msecs_to_jiffies(20); 1171 /* R1B or with data, should check SDCBUSY */ 1172 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1173 time_before(jiffies, tmo)) 1174 cpu_relax(); 1175 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1176 dev_err(host->dev, "Controller busy detected\n"); 1177 host->error |= REQ_CMD_BUSY; 1178 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1179 return false; 1180 } 1181 } 1182 return true; 1183 } 1184 1185 static void msdc_start_command(struct msdc_host *host, 1186 struct mmc_request *mrq, struct mmc_command *cmd) 1187 { 1188 u32 rawcmd; 1189 unsigned long flags; 1190 1191 WARN_ON(host->cmd); 1192 host->cmd = cmd; 1193 1194 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1195 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1196 return; 1197 1198 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1199 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1200 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1201 msdc_reset_hw(host); 1202 } 1203 1204 cmd->error = 0; 1205 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1206 1207 spin_lock_irqsave(&host->lock, flags); 1208 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1209 spin_unlock_irqrestore(&host->lock, flags); 1210 1211 writel(cmd->arg, host->base + SDC_ARG); 1212 writel(rawcmd, host->base + SDC_CMD); 1213 } 1214 1215 static void msdc_cmd_next(struct msdc_host *host, 1216 struct mmc_request *mrq, struct mmc_command *cmd) 1217 { 1218 if ((cmd->error && 1219 !(cmd->error == -EILSEQ && 1220 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1221 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1222 (mrq->sbc && mrq->sbc->error)) 1223 msdc_request_done(host, mrq); 1224 else if (cmd == mrq->sbc) 1225 msdc_start_command(host, mrq, mrq->cmd); 1226 else if (!cmd->data) 1227 msdc_request_done(host, mrq); 1228 else 1229 msdc_start_data(host, mrq, cmd, cmd->data); 1230 } 1231 1232 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1233 { 1234 struct msdc_host *host = mmc_priv(mmc); 1235 1236 host->error = 0; 1237 WARN_ON(host->mrq); 1238 host->mrq = mrq; 1239 1240 if (mrq->data) 1241 msdc_prepare_data(host, mrq); 1242 1243 /* if SBC is required, we have HW option and SW option. 1244 * if HW option is enabled, and SBC does not have "special" flags, 1245 * use HW option, otherwise use SW option 1246 */ 1247 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1248 (mrq->sbc->arg & 0xFFFF0000))) 1249 msdc_start_command(host, mrq, mrq->sbc); 1250 else 1251 msdc_start_command(host, mrq, mrq->cmd); 1252 } 1253 1254 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1255 { 1256 struct msdc_host *host = mmc_priv(mmc); 1257 struct mmc_data *data = mrq->data; 1258 1259 if (!data) 1260 return; 1261 1262 msdc_prepare_data(host, mrq); 1263 data->host_cookie |= MSDC_ASYNC_FLAG; 1264 } 1265 1266 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1267 int err) 1268 { 1269 struct msdc_host *host = mmc_priv(mmc); 1270 struct mmc_data *data; 1271 1272 data = mrq->data; 1273 if (!data) 1274 return; 1275 if (data->host_cookie) { 1276 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1277 msdc_unprepare_data(host, mrq); 1278 } 1279 } 1280 1281 static void msdc_data_xfer_next(struct msdc_host *host, 1282 struct mmc_request *mrq, struct mmc_data *data) 1283 { 1284 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1285 !mrq->sbc) 1286 msdc_start_command(host, mrq, mrq->stop); 1287 else 1288 msdc_request_done(host, mrq); 1289 } 1290 1291 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1292 struct mmc_request *mrq, struct mmc_data *data) 1293 { 1294 struct mmc_command *stop = data->stop; 1295 unsigned long flags; 1296 bool done; 1297 unsigned int check_data = events & 1298 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1299 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1300 | MSDC_INT_DMA_PROTECT); 1301 1302 spin_lock_irqsave(&host->lock, flags); 1303 done = !host->data; 1304 if (check_data) 1305 host->data = NULL; 1306 spin_unlock_irqrestore(&host->lock, flags); 1307 1308 if (done) 1309 return true; 1310 1311 if (check_data || (stop && stop->error)) { 1312 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1313 readl(host->base + MSDC_DMA_CFG)); 1314 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1315 1); 1316 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1317 cpu_relax(); 1318 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1319 dev_dbg(host->dev, "DMA stop\n"); 1320 1321 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1322 data->bytes_xfered = data->blocks * data->blksz; 1323 } else { 1324 dev_dbg(host->dev, "interrupt events: %x\n", events); 1325 msdc_reset_hw(host); 1326 host->error |= REQ_DAT_ERR; 1327 data->bytes_xfered = 0; 1328 1329 if (events & MSDC_INT_DATTMO) 1330 data->error = -ETIMEDOUT; 1331 else if (events & MSDC_INT_DATCRCERR) 1332 data->error = -EILSEQ; 1333 1334 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1335 __func__, mrq->cmd->opcode, data->blocks); 1336 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1337 (int)data->error, data->bytes_xfered); 1338 } 1339 1340 msdc_data_xfer_next(host, mrq, data); 1341 done = true; 1342 } 1343 return done; 1344 } 1345 1346 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1347 { 1348 u32 val = readl(host->base + SDC_CFG); 1349 1350 val &= ~SDC_CFG_BUSWIDTH; 1351 1352 switch (width) { 1353 default: 1354 case MMC_BUS_WIDTH_1: 1355 val |= (MSDC_BUS_1BITS << 16); 1356 break; 1357 case MMC_BUS_WIDTH_4: 1358 val |= (MSDC_BUS_4BITS << 16); 1359 break; 1360 case MMC_BUS_WIDTH_8: 1361 val |= (MSDC_BUS_8BITS << 16); 1362 break; 1363 } 1364 1365 writel(val, host->base + SDC_CFG); 1366 dev_dbg(host->dev, "Bus Width = %d", width); 1367 } 1368 1369 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1370 { 1371 struct msdc_host *host = mmc_priv(mmc); 1372 int ret; 1373 1374 if (!IS_ERR(mmc->supply.vqmmc)) { 1375 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1376 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1377 dev_err(host->dev, "Unsupported signal voltage!\n"); 1378 return -EINVAL; 1379 } 1380 1381 ret = mmc_regulator_set_vqmmc(mmc, ios); 1382 if (ret < 0) { 1383 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1384 ret, ios->signal_voltage); 1385 return ret; 1386 } 1387 1388 /* Apply different pinctrl settings for different signal voltage */ 1389 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1390 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1391 else 1392 pinctrl_select_state(host->pinctrl, host->pins_default); 1393 } 1394 return 0; 1395 } 1396 1397 static int msdc_card_busy(struct mmc_host *mmc) 1398 { 1399 struct msdc_host *host = mmc_priv(mmc); 1400 u32 status = readl(host->base + MSDC_PS); 1401 1402 /* only check if data0 is low */ 1403 return !(status & BIT(16)); 1404 } 1405 1406 static void msdc_request_timeout(struct work_struct *work) 1407 { 1408 struct msdc_host *host = container_of(work, struct msdc_host, 1409 req_timeout.work); 1410 1411 /* simulate HW timeout status */ 1412 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1413 if (host->mrq) { 1414 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1415 host->mrq, host->mrq->cmd->opcode); 1416 if (host->cmd) { 1417 dev_err(host->dev, "%s: aborting cmd=%d\n", 1418 __func__, host->cmd->opcode); 1419 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1420 host->cmd); 1421 } else if (host->data) { 1422 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1423 __func__, host->mrq->cmd->opcode, 1424 host->data->blocks); 1425 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1426 host->data); 1427 } 1428 } 1429 } 1430 1431 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1432 { 1433 if (enb) { 1434 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1435 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1436 if (host->dev_comp->recheck_sdio_irq) 1437 msdc_recheck_sdio_irq(host); 1438 } else { 1439 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1440 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1441 } 1442 } 1443 1444 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1445 { 1446 unsigned long flags; 1447 struct msdc_host *host = mmc_priv(mmc); 1448 1449 spin_lock_irqsave(&host->lock, flags); 1450 __msdc_enable_sdio_irq(host, enb); 1451 spin_unlock_irqrestore(&host->lock, flags); 1452 1453 if (enb) 1454 pm_runtime_get_noresume(host->dev); 1455 else 1456 pm_runtime_put_noidle(host->dev); 1457 } 1458 1459 static irqreturn_t msdc_irq(int irq, void *dev_id) 1460 { 1461 struct msdc_host *host = (struct msdc_host *) dev_id; 1462 1463 while (true) { 1464 unsigned long flags; 1465 struct mmc_request *mrq; 1466 struct mmc_command *cmd; 1467 struct mmc_data *data; 1468 u32 events, event_mask; 1469 1470 spin_lock_irqsave(&host->lock, flags); 1471 events = readl(host->base + MSDC_INT); 1472 event_mask = readl(host->base + MSDC_INTEN); 1473 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1474 __msdc_enable_sdio_irq(host, 0); 1475 /* clear interrupts */ 1476 writel(events & event_mask, host->base + MSDC_INT); 1477 1478 mrq = host->mrq; 1479 cmd = host->cmd; 1480 data = host->data; 1481 spin_unlock_irqrestore(&host->lock, flags); 1482 1483 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1484 sdio_signal_irq(host->mmc); 1485 1486 if ((events & event_mask) & MSDC_INT_CDSC) { 1487 if (host->internal_cd) 1488 mmc_detect_change(host->mmc, msecs_to_jiffies(20)); 1489 events &= ~MSDC_INT_CDSC; 1490 } 1491 1492 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1493 break; 1494 1495 if (!mrq) { 1496 dev_err(host->dev, 1497 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1498 __func__, events, event_mask); 1499 WARN_ON(1); 1500 break; 1501 } 1502 1503 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1504 1505 if (cmd) 1506 msdc_cmd_done(host, events, mrq, cmd); 1507 else if (data) 1508 msdc_data_xfer_done(host, events, mrq, data); 1509 } 1510 1511 return IRQ_HANDLED; 1512 } 1513 1514 static void msdc_init_hw(struct msdc_host *host) 1515 { 1516 u32 val; 1517 u32 tune_reg = host->dev_comp->pad_tune_reg; 1518 1519 /* Configure to MMC/SD mode, clock free running */ 1520 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1521 1522 /* Reset */ 1523 msdc_reset_hw(host); 1524 1525 /* Disable and clear all interrupts */ 1526 writel(0, host->base + MSDC_INTEN); 1527 val = readl(host->base + MSDC_INT); 1528 writel(val, host->base + MSDC_INT); 1529 1530 /* Configure card detection */ 1531 if (host->internal_cd) { 1532 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1533 DEFAULT_DEBOUNCE); 1534 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1535 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1536 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1537 } else { 1538 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1539 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1540 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1541 } 1542 1543 if (host->top_base) { 1544 writel(0, host->top_base + EMMC_TOP_CONTROL); 1545 writel(0, host->top_base + EMMC_TOP_CMD); 1546 } else { 1547 writel(0, host->base + tune_reg); 1548 } 1549 writel(0, host->base + MSDC_IOCON); 1550 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1551 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1552 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1553 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1554 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1555 1556 if (host->dev_comp->stop_clk_fix) { 1557 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1558 MSDC_PATCH_BIT1_STOP_DLY, 3); 1559 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1560 SDC_FIFO_CFG_WRVALIDSEL); 1561 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1562 SDC_FIFO_CFG_RDVALIDSEL); 1563 } 1564 1565 if (host->dev_comp->busy_check) 1566 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1567 1568 if (host->dev_comp->async_fifo) { 1569 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1570 MSDC_PB2_RESPWAIT, 3); 1571 if (host->dev_comp->enhance_rx) { 1572 if (host->top_base) 1573 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1574 SDC_RX_ENH_EN); 1575 else 1576 sdr_set_bits(host->base + SDC_ADV_CFG0, 1577 SDC_RX_ENHANCE_EN); 1578 } else { 1579 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1580 MSDC_PB2_RESPSTSENSEL, 2); 1581 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1582 MSDC_PB2_CRCSTSENSEL, 2); 1583 } 1584 /* use async fifo, then no need tune internal delay */ 1585 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1586 MSDC_PATCH_BIT2_CFGRESP); 1587 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1588 MSDC_PATCH_BIT2_CFGCRCSTS); 1589 } 1590 1591 if (host->dev_comp->support_64g) 1592 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1593 MSDC_PB2_SUPPORT_64G); 1594 if (host->dev_comp->data_tune) { 1595 if (host->top_base) { 1596 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1597 PAD_DAT_RD_RXDLY_SEL); 1598 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1599 DATA_K_VALUE_SEL); 1600 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1601 PAD_CMD_RD_RXDLY_SEL); 1602 } else { 1603 sdr_set_bits(host->base + tune_reg, 1604 MSDC_PAD_TUNE_RD_SEL | 1605 MSDC_PAD_TUNE_CMD_SEL); 1606 } 1607 } else { 1608 /* choose clock tune */ 1609 if (host->top_base) 1610 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1611 PAD_RXDLY_SEL); 1612 else 1613 sdr_set_bits(host->base + tune_reg, 1614 MSDC_PAD_TUNE_RXDLYSEL); 1615 } 1616 1617 /* Configure to enable SDIO mode. 1618 * it's must otherwise sdio cmd5 failed 1619 */ 1620 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1621 1622 /* Config SDIO device detect interrupt function */ 1623 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1624 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1625 1626 /* Configure to default data timeout */ 1627 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1628 1629 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1630 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1631 if (host->top_base) { 1632 host->def_tune_para.emmc_top_control = 1633 readl(host->top_base + EMMC_TOP_CONTROL); 1634 host->def_tune_para.emmc_top_cmd = 1635 readl(host->top_base + EMMC_TOP_CMD); 1636 host->saved_tune_para.emmc_top_control = 1637 readl(host->top_base + EMMC_TOP_CONTROL); 1638 host->saved_tune_para.emmc_top_cmd = 1639 readl(host->top_base + EMMC_TOP_CMD); 1640 } else { 1641 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1642 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1643 } 1644 dev_dbg(host->dev, "init hardware done!"); 1645 } 1646 1647 static void msdc_deinit_hw(struct msdc_host *host) 1648 { 1649 u32 val; 1650 1651 if (host->internal_cd) { 1652 /* Disabled card-detect */ 1653 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1654 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1655 } 1656 1657 /* Disable and clear all interrupts */ 1658 writel(0, host->base + MSDC_INTEN); 1659 1660 val = readl(host->base + MSDC_INT); 1661 writel(val, host->base + MSDC_INT); 1662 } 1663 1664 /* init gpd and bd list in msdc_drv_probe */ 1665 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1666 { 1667 struct mt_gpdma_desc *gpd = dma->gpd; 1668 struct mt_bdma_desc *bd = dma->bd; 1669 dma_addr_t dma_addr; 1670 int i; 1671 1672 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1673 1674 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1675 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1676 /* gpd->next is must set for desc DMA 1677 * That's why must alloc 2 gpd structure. 1678 */ 1679 gpd->next = lower_32_bits(dma_addr); 1680 if (host->dev_comp->support_64g) 1681 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1682 1683 dma_addr = dma->bd_addr; 1684 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1685 if (host->dev_comp->support_64g) 1686 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1687 1688 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1689 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1690 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1691 bd[i].next = lower_32_bits(dma_addr); 1692 if (host->dev_comp->support_64g) 1693 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1694 } 1695 } 1696 1697 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1698 { 1699 struct msdc_host *host = mmc_priv(mmc); 1700 int ret; 1701 1702 msdc_set_buswidth(host, ios->bus_width); 1703 1704 /* Suspend/Resume will do power off/on */ 1705 switch (ios->power_mode) { 1706 case MMC_POWER_UP: 1707 if (!IS_ERR(mmc->supply.vmmc)) { 1708 msdc_init_hw(host); 1709 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1710 ios->vdd); 1711 if (ret) { 1712 dev_err(host->dev, "Failed to set vmmc power!\n"); 1713 return; 1714 } 1715 } 1716 break; 1717 case MMC_POWER_ON: 1718 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1719 ret = regulator_enable(mmc->supply.vqmmc); 1720 if (ret) 1721 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1722 else 1723 host->vqmmc_enabled = true; 1724 } 1725 break; 1726 case MMC_POWER_OFF: 1727 if (!IS_ERR(mmc->supply.vmmc)) 1728 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1729 1730 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1731 regulator_disable(mmc->supply.vqmmc); 1732 host->vqmmc_enabled = false; 1733 } 1734 break; 1735 default: 1736 break; 1737 } 1738 1739 if (host->mclk != ios->clock || host->timing != ios->timing) 1740 msdc_set_mclk(host, ios->timing, ios->clock); 1741 } 1742 1743 static u32 test_delay_bit(u32 delay, u32 bit) 1744 { 1745 bit %= PAD_DELAY_MAX; 1746 return delay & (1 << bit); 1747 } 1748 1749 static int get_delay_len(u32 delay, u32 start_bit) 1750 { 1751 int i; 1752 1753 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1754 if (test_delay_bit(delay, start_bit + i) == 0) 1755 return i; 1756 } 1757 return PAD_DELAY_MAX - start_bit; 1758 } 1759 1760 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1761 { 1762 int start = 0, len = 0; 1763 int start_final = 0, len_final = 0; 1764 u8 final_phase = 0xff; 1765 struct msdc_delay_phase delay_phase = { 0, }; 1766 1767 if (delay == 0) { 1768 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1769 delay_phase.final_phase = final_phase; 1770 return delay_phase; 1771 } 1772 1773 while (start < PAD_DELAY_MAX) { 1774 len = get_delay_len(delay, start); 1775 if (len_final < len) { 1776 start_final = start; 1777 len_final = len; 1778 } 1779 start += len ? len : 1; 1780 if (len >= 12 && start_final < 4) 1781 break; 1782 } 1783 1784 /* The rule is that to find the smallest delay cell */ 1785 if (start_final == 0) 1786 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1787 else 1788 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1789 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1790 delay, len_final, final_phase); 1791 1792 delay_phase.maxlen = len_final; 1793 delay_phase.start = start_final; 1794 delay_phase.final_phase = final_phase; 1795 return delay_phase; 1796 } 1797 1798 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1799 { 1800 u32 tune_reg = host->dev_comp->pad_tune_reg; 1801 1802 if (host->top_base) 1803 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1804 value); 1805 else 1806 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1807 value); 1808 } 1809 1810 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1811 { 1812 u32 tune_reg = host->dev_comp->pad_tune_reg; 1813 1814 if (host->top_base) 1815 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1816 PAD_DAT_RD_RXDLY, value); 1817 else 1818 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1819 value); 1820 } 1821 1822 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1823 { 1824 struct msdc_host *host = mmc_priv(mmc); 1825 u32 rise_delay = 0, fall_delay = 0; 1826 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1827 struct msdc_delay_phase internal_delay_phase; 1828 u8 final_delay, final_maxlen; 1829 u32 internal_delay = 0; 1830 u32 tune_reg = host->dev_comp->pad_tune_reg; 1831 int cmd_err; 1832 int i, j; 1833 1834 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1835 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1836 sdr_set_field(host->base + tune_reg, 1837 MSDC_PAD_TUNE_CMDRRDLY, 1838 host->hs200_cmd_int_delay); 1839 1840 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1841 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1842 msdc_set_cmd_delay(host, i); 1843 /* 1844 * Using the same parameters, it may sometimes pass the test, 1845 * but sometimes it may fail. To make sure the parameters are 1846 * more stable, we test each set of parameters 3 times. 1847 */ 1848 for (j = 0; j < 3; j++) { 1849 mmc_send_tuning(mmc, opcode, &cmd_err); 1850 if (!cmd_err) { 1851 rise_delay |= (1 << i); 1852 } else { 1853 rise_delay &= ~(1 << i); 1854 break; 1855 } 1856 } 1857 } 1858 final_rise_delay = get_best_delay(host, rise_delay); 1859 /* if rising edge has enough margin, then do not scan falling edge */ 1860 if (final_rise_delay.maxlen >= 12 || 1861 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1862 goto skip_fall; 1863 1864 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1865 for (i = 0; i < PAD_DELAY_MAX; i++) { 1866 msdc_set_cmd_delay(host, i); 1867 /* 1868 * Using the same parameters, it may sometimes pass the test, 1869 * but sometimes it may fail. To make sure the parameters are 1870 * more stable, we test each set of parameters 3 times. 1871 */ 1872 for (j = 0; j < 3; j++) { 1873 mmc_send_tuning(mmc, opcode, &cmd_err); 1874 if (!cmd_err) { 1875 fall_delay |= (1 << i); 1876 } else { 1877 fall_delay &= ~(1 << i); 1878 break; 1879 } 1880 } 1881 } 1882 final_fall_delay = get_best_delay(host, fall_delay); 1883 1884 skip_fall: 1885 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1886 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1887 final_maxlen = final_fall_delay.maxlen; 1888 if (final_maxlen == final_rise_delay.maxlen) { 1889 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1890 final_delay = final_rise_delay.final_phase; 1891 } else { 1892 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1893 final_delay = final_fall_delay.final_phase; 1894 } 1895 msdc_set_cmd_delay(host, final_delay); 1896 1897 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1898 goto skip_internal; 1899 1900 for (i = 0; i < PAD_DELAY_MAX; i++) { 1901 sdr_set_field(host->base + tune_reg, 1902 MSDC_PAD_TUNE_CMDRRDLY, i); 1903 mmc_send_tuning(mmc, opcode, &cmd_err); 1904 if (!cmd_err) 1905 internal_delay |= (1 << i); 1906 } 1907 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1908 internal_delay_phase = get_best_delay(host, internal_delay); 1909 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1910 internal_delay_phase.final_phase); 1911 skip_internal: 1912 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1913 return final_delay == 0xff ? -EIO : 0; 1914 } 1915 1916 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1917 { 1918 struct msdc_host *host = mmc_priv(mmc); 1919 u32 cmd_delay = 0; 1920 struct msdc_delay_phase final_cmd_delay = { 0,}; 1921 u8 final_delay; 1922 int cmd_err; 1923 int i, j; 1924 1925 /* select EMMC50 PAD CMD tune */ 1926 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 1927 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 1928 1929 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1930 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1931 sdr_set_field(host->base + MSDC_PAD_TUNE, 1932 MSDC_PAD_TUNE_CMDRRDLY, 1933 host->hs200_cmd_int_delay); 1934 1935 if (host->hs400_cmd_resp_sel_rising) 1936 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1937 else 1938 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1939 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1940 sdr_set_field(host->base + PAD_CMD_TUNE, 1941 PAD_CMD_TUNE_RX_DLY3, i); 1942 /* 1943 * Using the same parameters, it may sometimes pass the test, 1944 * but sometimes it may fail. To make sure the parameters are 1945 * more stable, we test each set of parameters 3 times. 1946 */ 1947 for (j = 0; j < 3; j++) { 1948 mmc_send_tuning(mmc, opcode, &cmd_err); 1949 if (!cmd_err) { 1950 cmd_delay |= (1 << i); 1951 } else { 1952 cmd_delay &= ~(1 << i); 1953 break; 1954 } 1955 } 1956 } 1957 final_cmd_delay = get_best_delay(host, cmd_delay); 1958 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 1959 final_cmd_delay.final_phase); 1960 final_delay = final_cmd_delay.final_phase; 1961 1962 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1963 return final_delay == 0xff ? -EIO : 0; 1964 } 1965 1966 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1967 { 1968 struct msdc_host *host = mmc_priv(mmc); 1969 u32 rise_delay = 0, fall_delay = 0; 1970 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1971 u8 final_delay, final_maxlen; 1972 int i, ret; 1973 1974 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1975 host->latch_ck); 1976 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1977 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1978 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1979 msdc_set_data_delay(host, i); 1980 ret = mmc_send_tuning(mmc, opcode, NULL); 1981 if (!ret) 1982 rise_delay |= (1 << i); 1983 } 1984 final_rise_delay = get_best_delay(host, rise_delay); 1985 /* if rising edge has enough margin, then do not scan falling edge */ 1986 if (final_rise_delay.maxlen >= 12 || 1987 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1988 goto skip_fall; 1989 1990 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1991 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1992 for (i = 0; i < PAD_DELAY_MAX; i++) { 1993 msdc_set_data_delay(host, i); 1994 ret = mmc_send_tuning(mmc, opcode, NULL); 1995 if (!ret) 1996 fall_delay |= (1 << i); 1997 } 1998 final_fall_delay = get_best_delay(host, fall_delay); 1999 2000 skip_fall: 2001 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2002 if (final_maxlen == final_rise_delay.maxlen) { 2003 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2004 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2005 final_delay = final_rise_delay.final_phase; 2006 } else { 2007 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2008 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2009 final_delay = final_fall_delay.final_phase; 2010 } 2011 msdc_set_data_delay(host, final_delay); 2012 2013 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2014 return final_delay == 0xff ? -EIO : 0; 2015 } 2016 2017 /* 2018 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2019 * together, which can save the tuning time. 2020 */ 2021 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2022 { 2023 struct msdc_host *host = mmc_priv(mmc); 2024 u32 rise_delay = 0, fall_delay = 0; 2025 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2026 u8 final_delay, final_maxlen; 2027 int i, ret; 2028 2029 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2030 host->latch_ck); 2031 2032 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2033 sdr_clr_bits(host->base + MSDC_IOCON, 2034 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2035 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2036 msdc_set_cmd_delay(host, i); 2037 msdc_set_data_delay(host, i); 2038 ret = mmc_send_tuning(mmc, opcode, NULL); 2039 if (!ret) 2040 rise_delay |= (1 << i); 2041 } 2042 final_rise_delay = get_best_delay(host, rise_delay); 2043 /* if rising edge has enough margin, then do not scan falling edge */ 2044 if (final_rise_delay.maxlen >= 12 || 2045 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2046 goto skip_fall; 2047 2048 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2049 sdr_set_bits(host->base + MSDC_IOCON, 2050 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2051 for (i = 0; i < PAD_DELAY_MAX; i++) { 2052 msdc_set_cmd_delay(host, i); 2053 msdc_set_data_delay(host, i); 2054 ret = mmc_send_tuning(mmc, opcode, NULL); 2055 if (!ret) 2056 fall_delay |= (1 << i); 2057 } 2058 final_fall_delay = get_best_delay(host, fall_delay); 2059 2060 skip_fall: 2061 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2062 if (final_maxlen == final_rise_delay.maxlen) { 2063 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2064 sdr_clr_bits(host->base + MSDC_IOCON, 2065 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2066 final_delay = final_rise_delay.final_phase; 2067 } else { 2068 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2069 sdr_set_bits(host->base + MSDC_IOCON, 2070 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2071 final_delay = final_fall_delay.final_phase; 2072 } 2073 2074 msdc_set_cmd_delay(host, final_delay); 2075 msdc_set_data_delay(host, final_delay); 2076 2077 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2078 return final_delay == 0xff ? -EIO : 0; 2079 } 2080 2081 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2082 { 2083 struct msdc_host *host = mmc_priv(mmc); 2084 int ret; 2085 u32 tune_reg = host->dev_comp->pad_tune_reg; 2086 2087 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2088 ret = msdc_tune_together(mmc, opcode); 2089 if (host->hs400_mode) { 2090 sdr_clr_bits(host->base + MSDC_IOCON, 2091 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2092 msdc_set_data_delay(host, 0); 2093 } 2094 goto tune_done; 2095 } 2096 if (host->hs400_mode && 2097 host->dev_comp->hs400_tune) 2098 ret = hs400_tune_response(mmc, opcode); 2099 else 2100 ret = msdc_tune_response(mmc, opcode); 2101 if (ret == -EIO) { 2102 dev_err(host->dev, "Tune response fail!\n"); 2103 return ret; 2104 } 2105 if (host->hs400_mode == false) { 2106 ret = msdc_tune_data(mmc, opcode); 2107 if (ret == -EIO) 2108 dev_err(host->dev, "Tune data fail!\n"); 2109 } 2110 2111 tune_done: 2112 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2113 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2114 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2115 if (host->top_base) { 2116 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2117 EMMC_TOP_CONTROL); 2118 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2119 EMMC_TOP_CMD); 2120 } 2121 return ret; 2122 } 2123 2124 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2125 { 2126 struct msdc_host *host = mmc_priv(mmc); 2127 host->hs400_mode = true; 2128 2129 if (host->top_base) 2130 writel(host->hs400_ds_delay, 2131 host->top_base + EMMC50_PAD_DS_TUNE); 2132 else 2133 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2134 /* hs400 mode must set it to 0 */ 2135 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2136 /* to improve read performance, set outstanding to 2 */ 2137 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2138 2139 return 0; 2140 } 2141 2142 static void msdc_hw_reset(struct mmc_host *mmc) 2143 { 2144 struct msdc_host *host = mmc_priv(mmc); 2145 2146 sdr_set_bits(host->base + EMMC_IOCON, 1); 2147 udelay(10); /* 10us is enough */ 2148 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2149 } 2150 2151 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2152 { 2153 unsigned long flags; 2154 struct msdc_host *host = mmc_priv(mmc); 2155 2156 spin_lock_irqsave(&host->lock, flags); 2157 __msdc_enable_sdio_irq(host, 1); 2158 spin_unlock_irqrestore(&host->lock, flags); 2159 } 2160 2161 static int msdc_get_cd(struct mmc_host *mmc) 2162 { 2163 struct msdc_host *host = mmc_priv(mmc); 2164 int val; 2165 2166 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2167 return 1; 2168 2169 if (!host->internal_cd) 2170 return mmc_gpio_get_cd(mmc); 2171 2172 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2173 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2174 return !!val; 2175 else 2176 return !val; 2177 } 2178 2179 static const struct mmc_host_ops mt_msdc_ops = { 2180 .post_req = msdc_post_req, 2181 .pre_req = msdc_pre_req, 2182 .request = msdc_ops_request, 2183 .set_ios = msdc_ops_set_ios, 2184 .get_ro = mmc_gpio_get_ro, 2185 .get_cd = msdc_get_cd, 2186 .enable_sdio_irq = msdc_enable_sdio_irq, 2187 .ack_sdio_irq = msdc_ack_sdio_irq, 2188 .start_signal_voltage_switch = msdc_ops_switch_volt, 2189 .card_busy = msdc_card_busy, 2190 .execute_tuning = msdc_execute_tuning, 2191 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2192 .hw_reset = msdc_hw_reset, 2193 }; 2194 2195 static void msdc_of_property_parse(struct platform_device *pdev, 2196 struct msdc_host *host) 2197 { 2198 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2199 &host->latch_ck); 2200 2201 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2202 &host->hs400_ds_delay); 2203 2204 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2205 &host->hs200_cmd_int_delay); 2206 2207 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2208 &host->hs400_cmd_int_delay); 2209 2210 if (of_property_read_bool(pdev->dev.of_node, 2211 "mediatek,hs400-cmd-resp-sel-rising")) 2212 host->hs400_cmd_resp_sel_rising = true; 2213 else 2214 host->hs400_cmd_resp_sel_rising = false; 2215 } 2216 2217 static int msdc_drv_probe(struct platform_device *pdev) 2218 { 2219 struct mmc_host *mmc; 2220 struct msdc_host *host; 2221 struct resource *res; 2222 int ret; 2223 2224 if (!pdev->dev.of_node) { 2225 dev_err(&pdev->dev, "No DT found\n"); 2226 return -EINVAL; 2227 } 2228 2229 /* Allocate MMC host for this device */ 2230 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2231 if (!mmc) 2232 return -ENOMEM; 2233 2234 host = mmc_priv(mmc); 2235 ret = mmc_of_parse(mmc); 2236 if (ret) 2237 goto host_free; 2238 2239 host->base = devm_platform_ioremap_resource(pdev, 0); 2240 if (IS_ERR(host->base)) { 2241 ret = PTR_ERR(host->base); 2242 goto host_free; 2243 } 2244 2245 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2246 if (res) { 2247 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2248 if (IS_ERR(host->top_base)) 2249 host->top_base = NULL; 2250 } 2251 2252 ret = mmc_regulator_get_supply(mmc); 2253 if (ret) 2254 goto host_free; 2255 2256 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2257 if (IS_ERR(host->src_clk)) { 2258 ret = PTR_ERR(host->src_clk); 2259 goto host_free; 2260 } 2261 2262 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2263 if (IS_ERR(host->h_clk)) { 2264 ret = PTR_ERR(host->h_clk); 2265 goto host_free; 2266 } 2267 2268 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2269 if (IS_ERR(host->bus_clk)) 2270 host->bus_clk = NULL; 2271 /*source clock control gate is optional clock*/ 2272 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 2273 if (IS_ERR(host->src_clk_cg)) 2274 host->src_clk_cg = NULL; 2275 2276 host->irq = platform_get_irq(pdev, 0); 2277 if (host->irq < 0) { 2278 ret = -EINVAL; 2279 goto host_free; 2280 } 2281 2282 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2283 if (IS_ERR(host->pinctrl)) { 2284 ret = PTR_ERR(host->pinctrl); 2285 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2286 goto host_free; 2287 } 2288 2289 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2290 if (IS_ERR(host->pins_default)) { 2291 ret = PTR_ERR(host->pins_default); 2292 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2293 goto host_free; 2294 } 2295 2296 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2297 if (IS_ERR(host->pins_uhs)) { 2298 ret = PTR_ERR(host->pins_uhs); 2299 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2300 goto host_free; 2301 } 2302 2303 msdc_of_property_parse(pdev, host); 2304 2305 host->dev = &pdev->dev; 2306 host->dev_comp = of_device_get_match_data(&pdev->dev); 2307 host->mmc = mmc; 2308 host->src_clk_freq = clk_get_rate(host->src_clk); 2309 /* Set host parameters to mmc */ 2310 mmc->ops = &mt_msdc_ops; 2311 if (host->dev_comp->clk_div_bits == 8) 2312 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2313 else 2314 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2315 2316 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2317 !mmc_can_gpio_cd(mmc) && 2318 host->dev_comp->use_internal_cd) { 2319 /* 2320 * Is removable but no GPIO declared, so 2321 * use internal functionality. 2322 */ 2323 host->internal_cd = true; 2324 } 2325 2326 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2327 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2328 2329 mmc->caps |= MMC_CAP_CMD23; 2330 /* MMC core transfer sizes tunable parameters */ 2331 mmc->max_segs = MAX_BD_NUM; 2332 if (host->dev_comp->support_64g) 2333 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2334 else 2335 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2336 mmc->max_blk_size = 2048; 2337 mmc->max_req_size = 512 * 1024; 2338 mmc->max_blk_count = mmc->max_req_size / 512; 2339 if (host->dev_comp->support_64g) 2340 host->dma_mask = DMA_BIT_MASK(36); 2341 else 2342 host->dma_mask = DMA_BIT_MASK(32); 2343 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2344 2345 host->timeout_clks = 3 * 1048576; 2346 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2347 2 * sizeof(struct mt_gpdma_desc), 2348 &host->dma.gpd_addr, GFP_KERNEL); 2349 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2350 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2351 &host->dma.bd_addr, GFP_KERNEL); 2352 if (!host->dma.gpd || !host->dma.bd) { 2353 ret = -ENOMEM; 2354 goto release_mem; 2355 } 2356 msdc_init_gpd_bd(host, &host->dma); 2357 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2358 spin_lock_init(&host->lock); 2359 2360 platform_set_drvdata(pdev, mmc); 2361 msdc_ungate_clock(host); 2362 msdc_init_hw(host); 2363 2364 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2365 IRQF_TRIGGER_NONE, pdev->name, host); 2366 if (ret) 2367 goto release; 2368 2369 pm_runtime_set_active(host->dev); 2370 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2371 pm_runtime_use_autosuspend(host->dev); 2372 pm_runtime_enable(host->dev); 2373 ret = mmc_add_host(mmc); 2374 2375 if (ret) 2376 goto end; 2377 2378 return 0; 2379 end: 2380 pm_runtime_disable(host->dev); 2381 release: 2382 platform_set_drvdata(pdev, NULL); 2383 msdc_deinit_hw(host); 2384 msdc_gate_clock(host); 2385 release_mem: 2386 if (host->dma.gpd) 2387 dma_free_coherent(&pdev->dev, 2388 2 * sizeof(struct mt_gpdma_desc), 2389 host->dma.gpd, host->dma.gpd_addr); 2390 if (host->dma.bd) 2391 dma_free_coherent(&pdev->dev, 2392 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2393 host->dma.bd, host->dma.bd_addr); 2394 host_free: 2395 mmc_free_host(mmc); 2396 2397 return ret; 2398 } 2399 2400 static int msdc_drv_remove(struct platform_device *pdev) 2401 { 2402 struct mmc_host *mmc; 2403 struct msdc_host *host; 2404 2405 mmc = platform_get_drvdata(pdev); 2406 host = mmc_priv(mmc); 2407 2408 pm_runtime_get_sync(host->dev); 2409 2410 platform_set_drvdata(pdev, NULL); 2411 mmc_remove_host(host->mmc); 2412 msdc_deinit_hw(host); 2413 msdc_gate_clock(host); 2414 2415 pm_runtime_disable(host->dev); 2416 pm_runtime_put_noidle(host->dev); 2417 dma_free_coherent(&pdev->dev, 2418 2 * sizeof(struct mt_gpdma_desc), 2419 host->dma.gpd, host->dma.gpd_addr); 2420 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2421 host->dma.bd, host->dma.bd_addr); 2422 2423 mmc_free_host(host->mmc); 2424 2425 return 0; 2426 } 2427 2428 #ifdef CONFIG_PM 2429 static void msdc_save_reg(struct msdc_host *host) 2430 { 2431 u32 tune_reg = host->dev_comp->pad_tune_reg; 2432 2433 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2434 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2435 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2436 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2437 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2438 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2439 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2440 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2441 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2442 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2443 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2444 if (host->top_base) { 2445 host->save_para.emmc_top_control = 2446 readl(host->top_base + EMMC_TOP_CONTROL); 2447 host->save_para.emmc_top_cmd = 2448 readl(host->top_base + EMMC_TOP_CMD); 2449 host->save_para.emmc50_pad_ds_tune = 2450 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2451 } else { 2452 host->save_para.pad_tune = readl(host->base + tune_reg); 2453 } 2454 } 2455 2456 static void msdc_restore_reg(struct msdc_host *host) 2457 { 2458 u32 tune_reg = host->dev_comp->pad_tune_reg; 2459 2460 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2461 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2462 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2463 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2464 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2465 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2466 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2467 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2468 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2469 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2470 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2471 if (host->top_base) { 2472 writel(host->save_para.emmc_top_control, 2473 host->top_base + EMMC_TOP_CONTROL); 2474 writel(host->save_para.emmc_top_cmd, 2475 host->top_base + EMMC_TOP_CMD); 2476 writel(host->save_para.emmc50_pad_ds_tune, 2477 host->top_base + EMMC50_PAD_DS_TUNE); 2478 } else { 2479 writel(host->save_para.pad_tune, host->base + tune_reg); 2480 } 2481 2482 if (sdio_irq_claimed(host->mmc)) 2483 __msdc_enable_sdio_irq(host, 1); 2484 } 2485 2486 static int msdc_runtime_suspend(struct device *dev) 2487 { 2488 struct mmc_host *mmc = dev_get_drvdata(dev); 2489 struct msdc_host *host = mmc_priv(mmc); 2490 2491 msdc_save_reg(host); 2492 msdc_gate_clock(host); 2493 return 0; 2494 } 2495 2496 static int msdc_runtime_resume(struct device *dev) 2497 { 2498 struct mmc_host *mmc = dev_get_drvdata(dev); 2499 struct msdc_host *host = mmc_priv(mmc); 2500 2501 msdc_ungate_clock(host); 2502 msdc_restore_reg(host); 2503 return 0; 2504 } 2505 #endif 2506 2507 static const struct dev_pm_ops msdc_dev_pm_ops = { 2508 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2509 pm_runtime_force_resume) 2510 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2511 }; 2512 2513 static struct platform_driver mt_msdc_driver = { 2514 .probe = msdc_drv_probe, 2515 .remove = msdc_drv_remove, 2516 .driver = { 2517 .name = "mtk-msdc", 2518 .of_match_table = msdc_of_ids, 2519 .pm = &msdc_dev_pm_ops, 2520 }, 2521 }; 2522 2523 module_platform_driver(mt_msdc_driver); 2524 MODULE_LICENSE("GPL v2"); 2525 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2526