1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 // Copyright (C) 2008 Juergen Beisert 4 5 #include <linux/clk.h> 6 #include <linux/completion.h> 7 #include <linux/delay.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/err.h> 11 #include <linux/gpio.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/spi/spi.h> 20 #include <linux/spi/spi_bitbang.h> 21 #include <linux/types.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_gpio.h> 25 26 #include <linux/platform_data/dma-imx.h> 27 #include <linux/platform_data/spi-imx.h> 28 29 #define DRIVER_NAME "spi_imx" 30 31 static bool use_dma = true; 32 module_param(use_dma, bool, 0644); 33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); 34 35 #define MXC_CSPIRXDATA 0x00 36 #define MXC_CSPITXDATA 0x04 37 #define MXC_CSPICTRL 0x08 38 #define MXC_CSPIINT 0x0c 39 #define MXC_RESET 0x1c 40 41 /* generic defines to abstract from the different register layouts */ 42 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 43 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 44 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ 45 46 /* The maximum bytes that a sdma BD can transfer. */ 47 #define MAX_SDMA_BD_BYTES (1 << 15) 48 #define MX51_ECSPI_CTRL_MAX_BURST 512 49 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ 50 #define MX53_MAX_TRANSFER_BYTES 512 51 52 enum spi_imx_devtype { 53 IMX1_CSPI, 54 IMX21_CSPI, 55 IMX27_CSPI, 56 IMX31_CSPI, 57 IMX35_CSPI, /* CSPI on all i.mx except above */ 58 IMX51_ECSPI, /* ECSPI on i.mx51 */ 59 IMX53_ECSPI, /* ECSPI on i.mx53 and later */ 60 }; 61 62 struct spi_imx_data; 63 64 struct spi_imx_devtype_data { 65 void (*intctrl)(struct spi_imx_data *, int); 66 int (*prepare_message)(struct spi_imx_data *, struct spi_message *); 67 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *, 68 struct spi_transfer *); 69 void (*trigger)(struct spi_imx_data *); 70 int (*rx_available)(struct spi_imx_data *); 71 void (*reset)(struct spi_imx_data *); 72 void (*setup_wml)(struct spi_imx_data *); 73 void (*disable)(struct spi_imx_data *); 74 void (*disable_dma)(struct spi_imx_data *); 75 bool has_dmamode; 76 bool has_slavemode; 77 unsigned int fifo_size; 78 bool dynamic_burst; 79 enum spi_imx_devtype devtype; 80 }; 81 82 struct spi_imx_data { 83 struct spi_bitbang bitbang; 84 struct device *dev; 85 86 struct completion xfer_done; 87 void __iomem *base; 88 unsigned long base_phys; 89 90 struct clk *clk_per; 91 struct clk *clk_ipg; 92 unsigned long spi_clk; 93 unsigned int spi_bus_clk; 94 95 unsigned int bits_per_word; 96 unsigned int spi_drctl; 97 98 unsigned int count, remainder; 99 void (*tx)(struct spi_imx_data *); 100 void (*rx)(struct spi_imx_data *); 101 void *rx_buf; 102 const void *tx_buf; 103 unsigned int txfifo; /* number of words pushed in tx FIFO */ 104 unsigned int dynamic_burst; 105 106 /* Slave mode */ 107 bool slave_mode; 108 bool slave_aborted; 109 unsigned int slave_burst; 110 111 /* DMA */ 112 bool usedma; 113 u32 wml; 114 struct completion dma_rx_completion; 115 struct completion dma_tx_completion; 116 117 const struct spi_imx_devtype_data *devtype_data; 118 }; 119 120 static inline int is_imx27_cspi(struct spi_imx_data *d) 121 { 122 return d->devtype_data->devtype == IMX27_CSPI; 123 } 124 125 static inline int is_imx35_cspi(struct spi_imx_data *d) 126 { 127 return d->devtype_data->devtype == IMX35_CSPI; 128 } 129 130 static inline int is_imx51_ecspi(struct spi_imx_data *d) 131 { 132 return d->devtype_data->devtype == IMX51_ECSPI; 133 } 134 135 static inline int is_imx53_ecspi(struct spi_imx_data *d) 136 { 137 return d->devtype_data->devtype == IMX53_ECSPI; 138 } 139 140 #define MXC_SPI_BUF_RX(type) \ 141 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 142 { \ 143 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 144 \ 145 if (spi_imx->rx_buf) { \ 146 *(type *)spi_imx->rx_buf = val; \ 147 spi_imx->rx_buf += sizeof(type); \ 148 } \ 149 \ 150 spi_imx->remainder -= sizeof(type); \ 151 } 152 153 #define MXC_SPI_BUF_TX(type) \ 154 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 155 { \ 156 type val = 0; \ 157 \ 158 if (spi_imx->tx_buf) { \ 159 val = *(type *)spi_imx->tx_buf; \ 160 spi_imx->tx_buf += sizeof(type); \ 161 } \ 162 \ 163 spi_imx->count -= sizeof(type); \ 164 \ 165 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 166 } 167 168 MXC_SPI_BUF_RX(u8) 169 MXC_SPI_BUF_TX(u8) 170 MXC_SPI_BUF_RX(u16) 171 MXC_SPI_BUF_TX(u16) 172 MXC_SPI_BUF_RX(u32) 173 MXC_SPI_BUF_TX(u32) 174 175 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 176 * (which is currently not the case in this driver) 177 */ 178 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 179 256, 384, 512, 768, 1024}; 180 181 /* MX21, MX27 */ 182 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 183 unsigned int fspi, unsigned int max, unsigned int *fres) 184 { 185 int i; 186 187 for (i = 2; i < max; i++) 188 if (fspi * mxc_clkdivs[i] >= fin) 189 break; 190 191 *fres = fin / mxc_clkdivs[i]; 192 return i; 193 } 194 195 /* MX1, MX31, MX35, MX51 CSPI */ 196 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 197 unsigned int fspi, unsigned int *fres) 198 { 199 int i, div = 4; 200 201 for (i = 0; i < 7; i++) { 202 if (fspi * div >= fin) 203 goto out; 204 div <<= 1; 205 } 206 207 out: 208 *fres = fin / div; 209 return i; 210 } 211 212 static int spi_imx_bytes_per_word(const int bits_per_word) 213 { 214 if (bits_per_word <= 8) 215 return 1; 216 else if (bits_per_word <= 16) 217 return 2; 218 else 219 return 4; 220 } 221 222 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 223 struct spi_transfer *transfer) 224 { 225 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 226 227 if (!use_dma) 228 return false; 229 230 if (!master->dma_rx) 231 return false; 232 233 if (spi_imx->slave_mode) 234 return false; 235 236 if (transfer->len < spi_imx->devtype_data->fifo_size) 237 return false; 238 239 spi_imx->dynamic_burst = 0; 240 241 return true; 242 } 243 244 #define MX51_ECSPI_CTRL 0x08 245 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 246 #define MX51_ECSPI_CTRL_XCH (1 << 2) 247 #define MX51_ECSPI_CTRL_SMC (1 << 3) 248 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 249 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) 250 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 251 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 252 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 253 #define MX51_ECSPI_CTRL_BL_OFFSET 20 254 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) 255 256 #define MX51_ECSPI_CONFIG 0x0c 257 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 258 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 259 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 260 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 261 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 262 263 #define MX51_ECSPI_INT 0x10 264 #define MX51_ECSPI_INT_TEEN (1 << 0) 265 #define MX51_ECSPI_INT_RREN (1 << 3) 266 #define MX51_ECSPI_INT_RDREN (1 << 4) 267 268 #define MX51_ECSPI_DMA 0x14 269 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 270 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 271 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 272 273 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 274 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 275 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 276 277 #define MX51_ECSPI_STAT 0x18 278 #define MX51_ECSPI_STAT_RR (1 << 3) 279 280 #define MX51_ECSPI_TESTREG 0x20 281 #define MX51_ECSPI_TESTREG_LBC BIT(31) 282 283 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) 284 { 285 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); 286 #ifdef __LITTLE_ENDIAN 287 unsigned int bytes_per_word; 288 #endif 289 290 if (spi_imx->rx_buf) { 291 #ifdef __LITTLE_ENDIAN 292 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 293 if (bytes_per_word == 1) 294 val = cpu_to_be32(val); 295 else if (bytes_per_word == 2) 296 val = (val << 16) | (val >> 16); 297 #endif 298 *(u32 *)spi_imx->rx_buf = val; 299 spi_imx->rx_buf += sizeof(u32); 300 } 301 302 spi_imx->remainder -= sizeof(u32); 303 } 304 305 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) 306 { 307 int unaligned; 308 u32 val; 309 310 unaligned = spi_imx->remainder % 4; 311 312 if (!unaligned) { 313 spi_imx_buf_rx_swap_u32(spi_imx); 314 return; 315 } 316 317 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 318 spi_imx_buf_rx_u16(spi_imx); 319 return; 320 } 321 322 val = readl(spi_imx->base + MXC_CSPIRXDATA); 323 324 while (unaligned--) { 325 if (spi_imx->rx_buf) { 326 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; 327 spi_imx->rx_buf++; 328 } 329 spi_imx->remainder--; 330 } 331 } 332 333 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) 334 { 335 u32 val = 0; 336 #ifdef __LITTLE_ENDIAN 337 unsigned int bytes_per_word; 338 #endif 339 340 if (spi_imx->tx_buf) { 341 val = *(u32 *)spi_imx->tx_buf; 342 spi_imx->tx_buf += sizeof(u32); 343 } 344 345 spi_imx->count -= sizeof(u32); 346 #ifdef __LITTLE_ENDIAN 347 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 348 349 if (bytes_per_word == 1) 350 val = cpu_to_be32(val); 351 else if (bytes_per_word == 2) 352 val = (val << 16) | (val >> 16); 353 #endif 354 writel(val, spi_imx->base + MXC_CSPITXDATA); 355 } 356 357 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) 358 { 359 int unaligned; 360 u32 val = 0; 361 362 unaligned = spi_imx->count % 4; 363 364 if (!unaligned) { 365 spi_imx_buf_tx_swap_u32(spi_imx); 366 return; 367 } 368 369 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 370 spi_imx_buf_tx_u16(spi_imx); 371 return; 372 } 373 374 while (unaligned--) { 375 if (spi_imx->tx_buf) { 376 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); 377 spi_imx->tx_buf++; 378 } 379 spi_imx->count--; 380 } 381 382 writel(val, spi_imx->base + MXC_CSPITXDATA); 383 } 384 385 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) 386 { 387 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); 388 389 if (spi_imx->rx_buf) { 390 int n_bytes = spi_imx->slave_burst % sizeof(val); 391 392 if (!n_bytes) 393 n_bytes = sizeof(val); 394 395 memcpy(spi_imx->rx_buf, 396 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); 397 398 spi_imx->rx_buf += n_bytes; 399 spi_imx->slave_burst -= n_bytes; 400 } 401 402 spi_imx->remainder -= sizeof(u32); 403 } 404 405 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) 406 { 407 u32 val = 0; 408 int n_bytes = spi_imx->count % sizeof(val); 409 410 if (!n_bytes) 411 n_bytes = sizeof(val); 412 413 if (spi_imx->tx_buf) { 414 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, 415 spi_imx->tx_buf, n_bytes); 416 val = cpu_to_be32(val); 417 spi_imx->tx_buf += n_bytes; 418 } 419 420 spi_imx->count -= n_bytes; 421 422 writel(val, spi_imx->base + MXC_CSPITXDATA); 423 } 424 425 /* MX51 eCSPI */ 426 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 427 unsigned int fspi, unsigned int *fres) 428 { 429 /* 430 * there are two 4-bit dividers, the pre-divider divides by 431 * $pre, the post-divider by 2^$post 432 */ 433 unsigned int pre, post; 434 unsigned int fin = spi_imx->spi_clk; 435 436 if (unlikely(fspi > fin)) 437 return 0; 438 439 post = fls(fin) - fls(fspi); 440 if (fin > fspi << post) 441 post++; 442 443 /* now we have: (fin <= fspi << post) with post being minimal */ 444 445 post = max(4U, post) - 4; 446 if (unlikely(post > 0xf)) { 447 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 448 fspi, fin); 449 return 0xff; 450 } 451 452 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 453 454 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 455 __func__, fin, fspi, post, pre); 456 457 /* Resulting frequency for the SCLK line. */ 458 *fres = (fin / (pre + 1)) >> post; 459 460 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 461 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 462 } 463 464 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 465 { 466 unsigned val = 0; 467 468 if (enable & MXC_INT_TE) 469 val |= MX51_ECSPI_INT_TEEN; 470 471 if (enable & MXC_INT_RR) 472 val |= MX51_ECSPI_INT_RREN; 473 474 if (enable & MXC_INT_RDR) 475 val |= MX51_ECSPI_INT_RDREN; 476 477 writel(val, spi_imx->base + MX51_ECSPI_INT); 478 } 479 480 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 481 { 482 u32 reg; 483 484 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 485 reg |= MX51_ECSPI_CTRL_XCH; 486 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 487 } 488 489 static void mx51_disable_dma(struct spi_imx_data *spi_imx) 490 { 491 writel(0, spi_imx->base + MX51_ECSPI_DMA); 492 } 493 494 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) 495 { 496 u32 ctrl; 497 498 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 499 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; 500 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 501 } 502 503 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, 504 struct spi_message *msg) 505 { 506 struct spi_device *spi = msg->spi; 507 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 508 u32 testreg; 509 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 510 511 /* set Master or Slave mode */ 512 if (spi_imx->slave_mode) 513 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; 514 else 515 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 516 517 /* 518 * Enable SPI_RDY handling (falling edge/level triggered). 519 */ 520 if (spi->mode & SPI_READY) 521 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); 522 523 /* set chip select to use */ 524 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); 525 526 /* 527 * The ctrl register must be written first, with the EN bit set other 528 * registers must not be written to. 529 */ 530 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 531 532 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 533 if (spi->mode & SPI_LOOP) 534 testreg |= MX51_ECSPI_TESTREG_LBC; 535 else 536 testreg &= ~MX51_ECSPI_TESTREG_LBC; 537 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); 538 539 /* 540 * eCSPI burst completion by Chip Select signal in Slave mode 541 * is not functional for imx53 Soc, config SPI burst completed when 542 * BURST_LENGTH + 1 bits are received 543 */ 544 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 545 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 546 else 547 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 548 549 if (spi->mode & SPI_CPHA) 550 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 551 else 552 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 553 554 if (spi->mode & SPI_CPOL) { 555 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 556 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 557 } else { 558 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 559 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 560 } 561 562 if (spi->mode & SPI_CS_HIGH) 563 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 564 else 565 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 566 567 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 568 569 return 0; 570 } 571 572 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, 573 struct spi_device *spi, 574 struct spi_transfer *t) 575 { 576 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 577 u32 clk = t->speed_hz, delay; 578 579 /* Clear BL field and set the right value */ 580 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 581 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 582 ctrl |= (spi_imx->slave_burst * 8 - 1) 583 << MX51_ECSPI_CTRL_BL_OFFSET; 584 else 585 ctrl |= (spi_imx->bits_per_word - 1) 586 << MX51_ECSPI_CTRL_BL_OFFSET; 587 588 /* set clock speed */ 589 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | 590 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); 591 ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk); 592 spi_imx->spi_bus_clk = clk; 593 594 if (spi_imx->usedma) 595 ctrl |= MX51_ECSPI_CTRL_SMC; 596 597 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 598 599 /* 600 * Wait until the changes in the configuration register CONFIGREG 601 * propagate into the hardware. It takes exactly one tick of the 602 * SCLK clock, but we will wait two SCLK clock just to be sure. The 603 * effect of the delay it takes for the hardware to apply changes 604 * is noticable if the SCLK clock run very slow. In such a case, if 605 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 606 * be asserted before the SCLK polarity changes, which would disrupt 607 * the SPI communication as the device on the other end would consider 608 * the change of SCLK polarity as a clock tick already. 609 */ 610 delay = (2 * 1000000) / clk; 611 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ 612 udelay(delay); 613 else /* SCLK is _very_ slow */ 614 usleep_range(delay, delay + 10); 615 616 return 0; 617 } 618 619 static void mx51_setup_wml(struct spi_imx_data *spi_imx) 620 { 621 /* 622 * Configure the DMA register: setup the watermark 623 * and enable DMA request. 624 */ 625 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | 626 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | 627 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 628 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 629 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 630 } 631 632 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 633 { 634 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 635 } 636 637 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 638 { 639 /* drain receive buffer */ 640 while (mx51_ecspi_rx_available(spi_imx)) 641 readl(spi_imx->base + MXC_CSPIRXDATA); 642 } 643 644 #define MX31_INTREG_TEEN (1 << 0) 645 #define MX31_INTREG_RREN (1 << 3) 646 647 #define MX31_CSPICTRL_ENABLE (1 << 0) 648 #define MX31_CSPICTRL_MASTER (1 << 1) 649 #define MX31_CSPICTRL_XCH (1 << 2) 650 #define MX31_CSPICTRL_SMC (1 << 3) 651 #define MX31_CSPICTRL_POL (1 << 4) 652 #define MX31_CSPICTRL_PHA (1 << 5) 653 #define MX31_CSPICTRL_SSCTL (1 << 6) 654 #define MX31_CSPICTRL_SSPOL (1 << 7) 655 #define MX31_CSPICTRL_BC_SHIFT 8 656 #define MX35_CSPICTRL_BL_SHIFT 20 657 #define MX31_CSPICTRL_CS_SHIFT 24 658 #define MX35_CSPICTRL_CS_SHIFT 12 659 #define MX31_CSPICTRL_DR_SHIFT 16 660 661 #define MX31_CSPI_DMAREG 0x10 662 #define MX31_DMAREG_RH_DEN (1<<4) 663 #define MX31_DMAREG_TH_DEN (1<<1) 664 665 #define MX31_CSPISTATUS 0x14 666 #define MX31_STATUS_RR (1 << 3) 667 668 #define MX31_CSPI_TESTREG 0x1C 669 #define MX31_TEST_LBC (1 << 14) 670 671 /* These functions also work for the i.MX35, but be aware that 672 * the i.MX35 has a slightly different register layout for bits 673 * we do not use here. 674 */ 675 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 676 { 677 unsigned int val = 0; 678 679 if (enable & MXC_INT_TE) 680 val |= MX31_INTREG_TEEN; 681 if (enable & MXC_INT_RR) 682 val |= MX31_INTREG_RREN; 683 684 writel(val, spi_imx->base + MXC_CSPIINT); 685 } 686 687 static void mx31_trigger(struct spi_imx_data *spi_imx) 688 { 689 unsigned int reg; 690 691 reg = readl(spi_imx->base + MXC_CSPICTRL); 692 reg |= MX31_CSPICTRL_XCH; 693 writel(reg, spi_imx->base + MXC_CSPICTRL); 694 } 695 696 static int mx31_prepare_message(struct spi_imx_data *spi_imx, 697 struct spi_message *msg) 698 { 699 return 0; 700 } 701 702 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, 703 struct spi_device *spi, 704 struct spi_transfer *t) 705 { 706 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 707 unsigned int clk; 708 709 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << 710 MX31_CSPICTRL_DR_SHIFT; 711 spi_imx->spi_bus_clk = clk; 712 713 if (is_imx35_cspi(spi_imx)) { 714 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; 715 reg |= MX31_CSPICTRL_SSCTL; 716 } else { 717 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; 718 } 719 720 if (spi->mode & SPI_CPHA) 721 reg |= MX31_CSPICTRL_PHA; 722 if (spi->mode & SPI_CPOL) 723 reg |= MX31_CSPICTRL_POL; 724 if (spi->mode & SPI_CS_HIGH) 725 reg |= MX31_CSPICTRL_SSPOL; 726 if (!gpio_is_valid(spi->cs_gpio)) 727 reg |= (spi->chip_select) << 728 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 729 MX31_CSPICTRL_CS_SHIFT); 730 731 if (spi_imx->usedma) 732 reg |= MX31_CSPICTRL_SMC; 733 734 writel(reg, spi_imx->base + MXC_CSPICTRL); 735 736 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 737 if (spi->mode & SPI_LOOP) 738 reg |= MX31_TEST_LBC; 739 else 740 reg &= ~MX31_TEST_LBC; 741 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 742 743 if (spi_imx->usedma) { 744 /* 745 * configure DMA requests when RXFIFO is half full and 746 * when TXFIFO is half empty 747 */ 748 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 749 spi_imx->base + MX31_CSPI_DMAREG); 750 } 751 752 return 0; 753 } 754 755 static int mx31_rx_available(struct spi_imx_data *spi_imx) 756 { 757 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 758 } 759 760 static void mx31_reset(struct spi_imx_data *spi_imx) 761 { 762 /* drain receive buffer */ 763 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 764 readl(spi_imx->base + MXC_CSPIRXDATA); 765 } 766 767 #define MX21_INTREG_RR (1 << 4) 768 #define MX21_INTREG_TEEN (1 << 9) 769 #define MX21_INTREG_RREN (1 << 13) 770 771 #define MX21_CSPICTRL_POL (1 << 5) 772 #define MX21_CSPICTRL_PHA (1 << 6) 773 #define MX21_CSPICTRL_SSPOL (1 << 8) 774 #define MX21_CSPICTRL_XCH (1 << 9) 775 #define MX21_CSPICTRL_ENABLE (1 << 10) 776 #define MX21_CSPICTRL_MASTER (1 << 11) 777 #define MX21_CSPICTRL_DR_SHIFT 14 778 #define MX21_CSPICTRL_CS_SHIFT 19 779 780 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 781 { 782 unsigned int val = 0; 783 784 if (enable & MXC_INT_TE) 785 val |= MX21_INTREG_TEEN; 786 if (enable & MXC_INT_RR) 787 val |= MX21_INTREG_RREN; 788 789 writel(val, spi_imx->base + MXC_CSPIINT); 790 } 791 792 static void mx21_trigger(struct spi_imx_data *spi_imx) 793 { 794 unsigned int reg; 795 796 reg = readl(spi_imx->base + MXC_CSPICTRL); 797 reg |= MX21_CSPICTRL_XCH; 798 writel(reg, spi_imx->base + MXC_CSPICTRL); 799 } 800 801 static int mx21_prepare_message(struct spi_imx_data *spi_imx, 802 struct spi_message *msg) 803 { 804 return 0; 805 } 806 807 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, 808 struct spi_device *spi, 809 struct spi_transfer *t) 810 { 811 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 812 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 813 unsigned int clk; 814 815 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk) 816 << MX21_CSPICTRL_DR_SHIFT; 817 spi_imx->spi_bus_clk = clk; 818 819 reg |= spi_imx->bits_per_word - 1; 820 821 if (spi->mode & SPI_CPHA) 822 reg |= MX21_CSPICTRL_PHA; 823 if (spi->mode & SPI_CPOL) 824 reg |= MX21_CSPICTRL_POL; 825 if (spi->mode & SPI_CS_HIGH) 826 reg |= MX21_CSPICTRL_SSPOL; 827 if (!gpio_is_valid(spi->cs_gpio)) 828 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; 829 830 writel(reg, spi_imx->base + MXC_CSPICTRL); 831 832 return 0; 833 } 834 835 static int mx21_rx_available(struct spi_imx_data *spi_imx) 836 { 837 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 838 } 839 840 static void mx21_reset(struct spi_imx_data *spi_imx) 841 { 842 writel(1, spi_imx->base + MXC_RESET); 843 } 844 845 #define MX1_INTREG_RR (1 << 3) 846 #define MX1_INTREG_TEEN (1 << 8) 847 #define MX1_INTREG_RREN (1 << 11) 848 849 #define MX1_CSPICTRL_POL (1 << 4) 850 #define MX1_CSPICTRL_PHA (1 << 5) 851 #define MX1_CSPICTRL_XCH (1 << 8) 852 #define MX1_CSPICTRL_ENABLE (1 << 9) 853 #define MX1_CSPICTRL_MASTER (1 << 10) 854 #define MX1_CSPICTRL_DR_SHIFT 13 855 856 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 857 { 858 unsigned int val = 0; 859 860 if (enable & MXC_INT_TE) 861 val |= MX1_INTREG_TEEN; 862 if (enable & MXC_INT_RR) 863 val |= MX1_INTREG_RREN; 864 865 writel(val, spi_imx->base + MXC_CSPIINT); 866 } 867 868 static void mx1_trigger(struct spi_imx_data *spi_imx) 869 { 870 unsigned int reg; 871 872 reg = readl(spi_imx->base + MXC_CSPICTRL); 873 reg |= MX1_CSPICTRL_XCH; 874 writel(reg, spi_imx->base + MXC_CSPICTRL); 875 } 876 877 static int mx1_prepare_message(struct spi_imx_data *spi_imx, 878 struct spi_message *msg) 879 { 880 return 0; 881 } 882 883 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, 884 struct spi_device *spi, 885 struct spi_transfer *t) 886 { 887 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 888 unsigned int clk; 889 890 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << 891 MX1_CSPICTRL_DR_SHIFT; 892 spi_imx->spi_bus_clk = clk; 893 894 reg |= spi_imx->bits_per_word - 1; 895 896 if (spi->mode & SPI_CPHA) 897 reg |= MX1_CSPICTRL_PHA; 898 if (spi->mode & SPI_CPOL) 899 reg |= MX1_CSPICTRL_POL; 900 901 writel(reg, spi_imx->base + MXC_CSPICTRL); 902 903 return 0; 904 } 905 906 static int mx1_rx_available(struct spi_imx_data *spi_imx) 907 { 908 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 909 } 910 911 static void mx1_reset(struct spi_imx_data *spi_imx) 912 { 913 writel(1, spi_imx->base + MXC_RESET); 914 } 915 916 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 917 .intctrl = mx1_intctrl, 918 .prepare_message = mx1_prepare_message, 919 .prepare_transfer = mx1_prepare_transfer, 920 .trigger = mx1_trigger, 921 .rx_available = mx1_rx_available, 922 .reset = mx1_reset, 923 .fifo_size = 8, 924 .has_dmamode = false, 925 .dynamic_burst = false, 926 .has_slavemode = false, 927 .devtype = IMX1_CSPI, 928 }; 929 930 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 931 .intctrl = mx21_intctrl, 932 .prepare_message = mx21_prepare_message, 933 .prepare_transfer = mx21_prepare_transfer, 934 .trigger = mx21_trigger, 935 .rx_available = mx21_rx_available, 936 .reset = mx21_reset, 937 .fifo_size = 8, 938 .has_dmamode = false, 939 .dynamic_burst = false, 940 .has_slavemode = false, 941 .devtype = IMX21_CSPI, 942 }; 943 944 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 945 /* i.mx27 cspi shares the functions with i.mx21 one */ 946 .intctrl = mx21_intctrl, 947 .prepare_message = mx21_prepare_message, 948 .prepare_transfer = mx21_prepare_transfer, 949 .trigger = mx21_trigger, 950 .rx_available = mx21_rx_available, 951 .reset = mx21_reset, 952 .fifo_size = 8, 953 .has_dmamode = false, 954 .dynamic_burst = false, 955 .has_slavemode = false, 956 .devtype = IMX27_CSPI, 957 }; 958 959 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 960 .intctrl = mx31_intctrl, 961 .prepare_message = mx31_prepare_message, 962 .prepare_transfer = mx31_prepare_transfer, 963 .trigger = mx31_trigger, 964 .rx_available = mx31_rx_available, 965 .reset = mx31_reset, 966 .fifo_size = 8, 967 .has_dmamode = false, 968 .dynamic_burst = false, 969 .has_slavemode = false, 970 .devtype = IMX31_CSPI, 971 }; 972 973 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 974 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 975 .intctrl = mx31_intctrl, 976 .prepare_message = mx31_prepare_message, 977 .prepare_transfer = mx31_prepare_transfer, 978 .trigger = mx31_trigger, 979 .rx_available = mx31_rx_available, 980 .reset = mx31_reset, 981 .fifo_size = 8, 982 .has_dmamode = true, 983 .dynamic_burst = false, 984 .has_slavemode = false, 985 .devtype = IMX35_CSPI, 986 }; 987 988 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 989 .intctrl = mx51_ecspi_intctrl, 990 .prepare_message = mx51_ecspi_prepare_message, 991 .prepare_transfer = mx51_ecspi_prepare_transfer, 992 .trigger = mx51_ecspi_trigger, 993 .rx_available = mx51_ecspi_rx_available, 994 .reset = mx51_ecspi_reset, 995 .setup_wml = mx51_setup_wml, 996 .disable_dma = mx51_disable_dma, 997 .fifo_size = 64, 998 .has_dmamode = true, 999 .dynamic_burst = true, 1000 .has_slavemode = true, 1001 .disable = mx51_ecspi_disable, 1002 .devtype = IMX51_ECSPI, 1003 }; 1004 1005 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { 1006 .intctrl = mx51_ecspi_intctrl, 1007 .prepare_message = mx51_ecspi_prepare_message, 1008 .prepare_transfer = mx51_ecspi_prepare_transfer, 1009 .trigger = mx51_ecspi_trigger, 1010 .rx_available = mx51_ecspi_rx_available, 1011 .disable_dma = mx51_disable_dma, 1012 .reset = mx51_ecspi_reset, 1013 .fifo_size = 64, 1014 .has_dmamode = true, 1015 .has_slavemode = true, 1016 .disable = mx51_ecspi_disable, 1017 .devtype = IMX53_ECSPI, 1018 }; 1019 1020 static const struct platform_device_id spi_imx_devtype[] = { 1021 { 1022 .name = "imx1-cspi", 1023 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, 1024 }, { 1025 .name = "imx21-cspi", 1026 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, 1027 }, { 1028 .name = "imx27-cspi", 1029 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, 1030 }, { 1031 .name = "imx31-cspi", 1032 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, 1033 }, { 1034 .name = "imx35-cspi", 1035 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, 1036 }, { 1037 .name = "imx51-ecspi", 1038 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 1039 }, { 1040 .name = "imx53-ecspi", 1041 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data, 1042 }, { 1043 /* sentinel */ 1044 } 1045 }; 1046 1047 static const struct of_device_id spi_imx_dt_ids[] = { 1048 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 1049 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 1050 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 1051 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 1052 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 1053 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 1054 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, 1055 { /* sentinel */ } 1056 }; 1057 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 1058 1059 static void spi_imx_chipselect(struct spi_device *spi, int is_active) 1060 { 1061 int active = is_active != BITBANG_CS_INACTIVE; 1062 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 1063 1064 if (spi->mode & SPI_NO_CS) 1065 return; 1066 1067 if (!gpio_is_valid(spi->cs_gpio)) 1068 return; 1069 1070 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); 1071 } 1072 1073 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) 1074 { 1075 u32 ctrl; 1076 1077 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 1078 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 1079 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); 1080 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 1081 } 1082 1083 static void spi_imx_push(struct spi_imx_data *spi_imx) 1084 { 1085 unsigned int burst_len, fifo_words; 1086 1087 if (spi_imx->dynamic_burst) 1088 fifo_words = 4; 1089 else 1090 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); 1091 /* 1092 * Reload the FIFO when the remaining bytes to be transferred in the 1093 * current burst is 0. This only applies when bits_per_word is a 1094 * multiple of 8. 1095 */ 1096 if (!spi_imx->remainder) { 1097 if (spi_imx->dynamic_burst) { 1098 1099 /* We need to deal unaligned data first */ 1100 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; 1101 1102 if (!burst_len) 1103 burst_len = MX51_ECSPI_CTRL_MAX_BURST; 1104 1105 spi_imx_set_burst_len(spi_imx, burst_len * 8); 1106 1107 spi_imx->remainder = burst_len; 1108 } else { 1109 spi_imx->remainder = fifo_words; 1110 } 1111 } 1112 1113 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { 1114 if (!spi_imx->count) 1115 break; 1116 if (spi_imx->dynamic_burst && 1117 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 1118 fifo_words)) 1119 break; 1120 spi_imx->tx(spi_imx); 1121 spi_imx->txfifo++; 1122 } 1123 1124 if (!spi_imx->slave_mode) 1125 spi_imx->devtype_data->trigger(spi_imx); 1126 } 1127 1128 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 1129 { 1130 struct spi_imx_data *spi_imx = dev_id; 1131 1132 while (spi_imx->txfifo && 1133 spi_imx->devtype_data->rx_available(spi_imx)) { 1134 spi_imx->rx(spi_imx); 1135 spi_imx->txfifo--; 1136 } 1137 1138 if (spi_imx->count) { 1139 spi_imx_push(spi_imx); 1140 return IRQ_HANDLED; 1141 } 1142 1143 if (spi_imx->txfifo) { 1144 /* No data left to push, but still waiting for rx data, 1145 * enable receive data available interrupt. 1146 */ 1147 spi_imx->devtype_data->intctrl( 1148 spi_imx, MXC_INT_RR); 1149 return IRQ_HANDLED; 1150 } 1151 1152 spi_imx->devtype_data->intctrl(spi_imx, 0); 1153 complete(&spi_imx->xfer_done); 1154 1155 return IRQ_HANDLED; 1156 } 1157 1158 static int spi_imx_dma_configure(struct spi_master *master) 1159 { 1160 int ret; 1161 enum dma_slave_buswidth buswidth; 1162 struct dma_slave_config rx = {}, tx = {}; 1163 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1164 1165 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { 1166 case 4: 1167 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1168 break; 1169 case 2: 1170 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1171 break; 1172 case 1: 1173 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1174 break; 1175 default: 1176 return -EINVAL; 1177 } 1178 1179 tx.direction = DMA_MEM_TO_DEV; 1180 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 1181 tx.dst_addr_width = buswidth; 1182 tx.dst_maxburst = spi_imx->wml; 1183 ret = dmaengine_slave_config(master->dma_tx, &tx); 1184 if (ret) { 1185 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 1186 return ret; 1187 } 1188 1189 rx.direction = DMA_DEV_TO_MEM; 1190 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 1191 rx.src_addr_width = buswidth; 1192 rx.src_maxburst = spi_imx->wml; 1193 ret = dmaengine_slave_config(master->dma_rx, &rx); 1194 if (ret) { 1195 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 1196 return ret; 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int spi_imx_setupxfer(struct spi_device *spi, 1203 struct spi_transfer *t) 1204 { 1205 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1206 1207 if (!t) 1208 return 0; 1209 1210 spi_imx->bits_per_word = t->bits_per_word; 1211 1212 /* 1213 * Initialize the functions for transfer. To transfer non byte-aligned 1214 * words, we have to use multiple word-size bursts, we can't use 1215 * dynamic_burst in that case. 1216 */ 1217 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && 1218 (spi_imx->bits_per_word == 8 || 1219 spi_imx->bits_per_word == 16 || 1220 spi_imx->bits_per_word == 32)) { 1221 1222 spi_imx->rx = spi_imx_buf_rx_swap; 1223 spi_imx->tx = spi_imx_buf_tx_swap; 1224 spi_imx->dynamic_burst = 1; 1225 1226 } else { 1227 if (spi_imx->bits_per_word <= 8) { 1228 spi_imx->rx = spi_imx_buf_rx_u8; 1229 spi_imx->tx = spi_imx_buf_tx_u8; 1230 } else if (spi_imx->bits_per_word <= 16) { 1231 spi_imx->rx = spi_imx_buf_rx_u16; 1232 spi_imx->tx = spi_imx_buf_tx_u16; 1233 } else { 1234 spi_imx->rx = spi_imx_buf_rx_u32; 1235 spi_imx->tx = spi_imx_buf_tx_u32; 1236 } 1237 spi_imx->dynamic_burst = 0; 1238 } 1239 1240 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 1241 spi_imx->usedma = true; 1242 else 1243 spi_imx->usedma = false; 1244 1245 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { 1246 spi_imx->rx = mx53_ecspi_rx_slave; 1247 spi_imx->tx = mx53_ecspi_tx_slave; 1248 spi_imx->slave_burst = t->len; 1249 } 1250 1251 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t); 1252 1253 return 0; 1254 } 1255 1256 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 1257 { 1258 struct spi_master *master = spi_imx->bitbang.master; 1259 1260 if (master->dma_rx) { 1261 dma_release_channel(master->dma_rx); 1262 master->dma_rx = NULL; 1263 } 1264 1265 if (master->dma_tx) { 1266 dma_release_channel(master->dma_tx); 1267 master->dma_tx = NULL; 1268 } 1269 } 1270 1271 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 1272 struct spi_master *master) 1273 { 1274 int ret; 1275 1276 /* use pio mode for i.mx6dl chip TKT238285 */ 1277 if (of_machine_is_compatible("fsl,imx6dl")) 1278 return 0; 1279 1280 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; 1281 1282 /* Prepare for TX DMA: */ 1283 master->dma_tx = dma_request_chan(dev, "tx"); 1284 if (IS_ERR(master->dma_tx)) { 1285 ret = PTR_ERR(master->dma_tx); 1286 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 1287 master->dma_tx = NULL; 1288 goto err; 1289 } 1290 1291 /* Prepare for RX : */ 1292 master->dma_rx = dma_request_chan(dev, "rx"); 1293 if (IS_ERR(master->dma_rx)) { 1294 ret = PTR_ERR(master->dma_rx); 1295 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 1296 master->dma_rx = NULL; 1297 goto err; 1298 } 1299 1300 init_completion(&spi_imx->dma_rx_completion); 1301 init_completion(&spi_imx->dma_tx_completion); 1302 master->can_dma = spi_imx_can_dma; 1303 master->max_dma_len = MAX_SDMA_BD_BYTES; 1304 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 1305 SPI_MASTER_MUST_TX; 1306 1307 return 0; 1308 err: 1309 spi_imx_sdma_exit(spi_imx); 1310 return ret; 1311 } 1312 1313 static void spi_imx_dma_rx_callback(void *cookie) 1314 { 1315 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1316 1317 complete(&spi_imx->dma_rx_completion); 1318 } 1319 1320 static void spi_imx_dma_tx_callback(void *cookie) 1321 { 1322 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1323 1324 complete(&spi_imx->dma_tx_completion); 1325 } 1326 1327 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1328 { 1329 unsigned long timeout = 0; 1330 1331 /* Time with actual data transfer and CS change delay related to HW */ 1332 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1333 1334 /* Add extra second for scheduler related activities */ 1335 timeout += 1; 1336 1337 /* Double calculated timeout */ 1338 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 1339 } 1340 1341 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1342 struct spi_transfer *transfer) 1343 { 1344 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1345 unsigned long transfer_timeout; 1346 unsigned long timeout; 1347 struct spi_master *master = spi_imx->bitbang.master; 1348 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1349 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); 1350 unsigned int bytes_per_word, i; 1351 int ret; 1352 1353 /* Get the right burst length from the last sg to ensure no tail data */ 1354 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); 1355 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { 1356 if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) 1357 break; 1358 } 1359 /* Use 1 as wml in case no available burst length got */ 1360 if (i == 0) 1361 i = 1; 1362 1363 spi_imx->wml = i; 1364 1365 ret = spi_imx_dma_configure(master); 1366 if (ret) 1367 return ret; 1368 1369 if (!spi_imx->devtype_data->setup_wml) { 1370 dev_err(spi_imx->dev, "No setup_wml()?\n"); 1371 return -EINVAL; 1372 } 1373 spi_imx->devtype_data->setup_wml(spi_imx); 1374 1375 /* 1376 * The TX DMA setup starts the transfer, so make sure RX is configured 1377 * before TX. 1378 */ 1379 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 1380 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1381 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1382 if (!desc_rx) 1383 return -EINVAL; 1384 1385 desc_rx->callback = spi_imx_dma_rx_callback; 1386 desc_rx->callback_param = (void *)spi_imx; 1387 dmaengine_submit(desc_rx); 1388 reinit_completion(&spi_imx->dma_rx_completion); 1389 dma_async_issue_pending(master->dma_rx); 1390 1391 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 1392 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1393 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1394 if (!desc_tx) { 1395 dmaengine_terminate_all(master->dma_tx); 1396 dmaengine_terminate_all(master->dma_rx); 1397 return -EINVAL; 1398 } 1399 1400 desc_tx->callback = spi_imx_dma_tx_callback; 1401 desc_tx->callback_param = (void *)spi_imx; 1402 dmaengine_submit(desc_tx); 1403 reinit_completion(&spi_imx->dma_tx_completion); 1404 dma_async_issue_pending(master->dma_tx); 1405 1406 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1407 1408 /* Wait SDMA to finish the data transfer.*/ 1409 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1410 transfer_timeout); 1411 if (!timeout) { 1412 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1413 dmaengine_terminate_all(master->dma_tx); 1414 dmaengine_terminate_all(master->dma_rx); 1415 return -ETIMEDOUT; 1416 } 1417 1418 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1419 transfer_timeout); 1420 if (!timeout) { 1421 dev_err(&master->dev, "I/O Error in DMA RX\n"); 1422 spi_imx->devtype_data->reset(spi_imx); 1423 dmaengine_terminate_all(master->dma_rx); 1424 return -ETIMEDOUT; 1425 } 1426 1427 return transfer->len; 1428 } 1429 1430 static int spi_imx_pio_transfer(struct spi_device *spi, 1431 struct spi_transfer *transfer) 1432 { 1433 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1434 unsigned long transfer_timeout; 1435 unsigned long timeout; 1436 1437 spi_imx->tx_buf = transfer->tx_buf; 1438 spi_imx->rx_buf = transfer->rx_buf; 1439 spi_imx->count = transfer->len; 1440 spi_imx->txfifo = 0; 1441 spi_imx->remainder = 0; 1442 1443 reinit_completion(&spi_imx->xfer_done); 1444 1445 spi_imx_push(spi_imx); 1446 1447 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1448 1449 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1450 1451 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, 1452 transfer_timeout); 1453 if (!timeout) { 1454 dev_err(&spi->dev, "I/O Error in PIO\n"); 1455 spi_imx->devtype_data->reset(spi_imx); 1456 return -ETIMEDOUT; 1457 } 1458 1459 return transfer->len; 1460 } 1461 1462 static int spi_imx_pio_transfer_slave(struct spi_device *spi, 1463 struct spi_transfer *transfer) 1464 { 1465 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1466 int ret = transfer->len; 1467 1468 if (is_imx53_ecspi(spi_imx) && 1469 transfer->len > MX53_MAX_TRANSFER_BYTES) { 1470 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", 1471 MX53_MAX_TRANSFER_BYTES); 1472 return -EMSGSIZE; 1473 } 1474 1475 spi_imx->tx_buf = transfer->tx_buf; 1476 spi_imx->rx_buf = transfer->rx_buf; 1477 spi_imx->count = transfer->len; 1478 spi_imx->txfifo = 0; 1479 spi_imx->remainder = 0; 1480 1481 reinit_completion(&spi_imx->xfer_done); 1482 spi_imx->slave_aborted = false; 1483 1484 spi_imx_push(spi_imx); 1485 1486 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); 1487 1488 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || 1489 spi_imx->slave_aborted) { 1490 dev_dbg(&spi->dev, "interrupted\n"); 1491 ret = -EINTR; 1492 } 1493 1494 /* ecspi has a HW issue when works in Slave mode, 1495 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, 1496 * ECSPI_TXDATA keeps shift out the last word data, 1497 * so we have to disable ECSPI when in slave mode after the 1498 * transfer completes 1499 */ 1500 if (spi_imx->devtype_data->disable) 1501 spi_imx->devtype_data->disable(spi_imx); 1502 1503 return ret; 1504 } 1505 1506 static int spi_imx_transfer(struct spi_device *spi, 1507 struct spi_transfer *transfer) 1508 { 1509 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1510 int ret; 1511 1512 /* flush rxfifo before transfer */ 1513 while (spi_imx->devtype_data->rx_available(spi_imx)) 1514 readl(spi_imx->base + MXC_CSPIRXDATA); 1515 1516 if (spi_imx->slave_mode) 1517 return spi_imx_pio_transfer_slave(spi, transfer); 1518 1519 /* 1520 * fallback PIO mode if dma setup error happen, for example sdma 1521 * firmware may not be updated as ERR009165 required. 1522 */ 1523 if (spi_imx->usedma) { 1524 ret = spi_imx_dma_transfer(spi_imx, transfer); 1525 if (ret != -EINVAL) 1526 return ret; 1527 1528 spi_imx->devtype_data->disable_dma(spi_imx); 1529 1530 spi_imx->usedma = false; 1531 spi_imx->dynamic_burst = spi_imx->devtype_data->dynamic_burst; 1532 dev_dbg(&spi->dev, "Fallback to PIO mode\n"); 1533 } 1534 1535 return spi_imx_pio_transfer(spi, transfer); 1536 } 1537 1538 static int spi_imx_setup(struct spi_device *spi) 1539 { 1540 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1541 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1542 1543 if (spi->mode & SPI_NO_CS) 1544 return 0; 1545 1546 if (gpio_is_valid(spi->cs_gpio)) 1547 gpio_direction_output(spi->cs_gpio, 1548 spi->mode & SPI_CS_HIGH ? 0 : 1); 1549 1550 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); 1551 1552 return 0; 1553 } 1554 1555 static void spi_imx_cleanup(struct spi_device *spi) 1556 { 1557 } 1558 1559 static int 1560 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1561 { 1562 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1563 int ret; 1564 1565 ret = clk_enable(spi_imx->clk_per); 1566 if (ret) 1567 return ret; 1568 1569 ret = clk_enable(spi_imx->clk_ipg); 1570 if (ret) { 1571 clk_disable(spi_imx->clk_per); 1572 return ret; 1573 } 1574 1575 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); 1576 if (ret) { 1577 clk_disable(spi_imx->clk_ipg); 1578 clk_disable(spi_imx->clk_per); 1579 } 1580 1581 return ret; 1582 } 1583 1584 static int 1585 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1586 { 1587 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1588 1589 clk_disable(spi_imx->clk_ipg); 1590 clk_disable(spi_imx->clk_per); 1591 return 0; 1592 } 1593 1594 static int spi_imx_slave_abort(struct spi_master *master) 1595 { 1596 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1597 1598 spi_imx->slave_aborted = true; 1599 complete(&spi_imx->xfer_done); 1600 1601 return 0; 1602 } 1603 1604 static int spi_imx_probe(struct platform_device *pdev) 1605 { 1606 struct device_node *np = pdev->dev.of_node; 1607 const struct of_device_id *of_id = 1608 of_match_device(spi_imx_dt_ids, &pdev->dev); 1609 struct spi_imx_master *mxc_platform_info = 1610 dev_get_platdata(&pdev->dev); 1611 struct spi_master *master; 1612 struct spi_imx_data *spi_imx; 1613 struct resource *res; 1614 int i, ret, irq, spi_drctl; 1615 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : 1616 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; 1617 bool slave_mode; 1618 1619 if (!np && !mxc_platform_info) { 1620 dev_err(&pdev->dev, "can't get the platform data\n"); 1621 return -EINVAL; 1622 } 1623 1624 slave_mode = devtype_data->has_slavemode && 1625 of_property_read_bool(np, "spi-slave"); 1626 if (slave_mode) 1627 master = spi_alloc_slave(&pdev->dev, 1628 sizeof(struct spi_imx_data)); 1629 else 1630 master = spi_alloc_master(&pdev->dev, 1631 sizeof(struct spi_imx_data)); 1632 if (!master) 1633 return -ENOMEM; 1634 1635 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); 1636 if ((ret < 0) || (spi_drctl >= 0x3)) { 1637 /* '11' is reserved */ 1638 spi_drctl = 0; 1639 } 1640 1641 platform_set_drvdata(pdev, master); 1642 1643 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1644 master->bus_num = np ? -1 : pdev->id; 1645 1646 spi_imx = spi_master_get_devdata(master); 1647 spi_imx->bitbang.master = master; 1648 spi_imx->dev = &pdev->dev; 1649 spi_imx->slave_mode = slave_mode; 1650 1651 spi_imx->devtype_data = devtype_data; 1652 1653 /* Get number of chip selects, either platform data or OF */ 1654 if (mxc_platform_info) { 1655 master->num_chipselect = mxc_platform_info->num_chipselect; 1656 if (mxc_platform_info->chipselect) { 1657 master->cs_gpios = devm_kcalloc(&master->dev, 1658 master->num_chipselect, sizeof(int), 1659 GFP_KERNEL); 1660 if (!master->cs_gpios) 1661 return -ENOMEM; 1662 1663 for (i = 0; i < master->num_chipselect; i++) 1664 master->cs_gpios[i] = mxc_platform_info->chipselect[i]; 1665 } 1666 } else { 1667 u32 num_cs; 1668 1669 if (!of_property_read_u32(np, "num-cs", &num_cs)) 1670 master->num_chipselect = num_cs; 1671 /* If not preset, default value of 1 is used */ 1672 } 1673 1674 spi_imx->bitbang.chipselect = spi_imx_chipselect; 1675 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1676 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1677 spi_imx->bitbang.master->setup = spi_imx_setup; 1678 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1679 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1680 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1681 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; 1682 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 1683 | SPI_NO_CS; 1684 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || 1685 is_imx53_ecspi(spi_imx)) 1686 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; 1687 1688 spi_imx->spi_drctl = spi_drctl; 1689 1690 init_completion(&spi_imx->xfer_done); 1691 1692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1693 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1694 if (IS_ERR(spi_imx->base)) { 1695 ret = PTR_ERR(spi_imx->base); 1696 goto out_master_put; 1697 } 1698 spi_imx->base_phys = res->start; 1699 1700 irq = platform_get_irq(pdev, 0); 1701 if (irq < 0) { 1702 ret = irq; 1703 goto out_master_put; 1704 } 1705 1706 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1707 dev_name(&pdev->dev), spi_imx); 1708 if (ret) { 1709 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1710 goto out_master_put; 1711 } 1712 1713 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1714 if (IS_ERR(spi_imx->clk_ipg)) { 1715 ret = PTR_ERR(spi_imx->clk_ipg); 1716 goto out_master_put; 1717 } 1718 1719 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1720 if (IS_ERR(spi_imx->clk_per)) { 1721 ret = PTR_ERR(spi_imx->clk_per); 1722 goto out_master_put; 1723 } 1724 1725 ret = clk_prepare_enable(spi_imx->clk_per); 1726 if (ret) 1727 goto out_master_put; 1728 1729 ret = clk_prepare_enable(spi_imx->clk_ipg); 1730 if (ret) 1731 goto out_put_per; 1732 1733 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1734 /* 1735 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1736 * if validated on other chips. 1737 */ 1738 if (spi_imx->devtype_data->has_dmamode) { 1739 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1740 if (ret == -EPROBE_DEFER) 1741 goto out_clk_put; 1742 1743 if (ret < 0) 1744 dev_err(&pdev->dev, "dma setup error %d, use pio\n", 1745 ret); 1746 } 1747 1748 spi_imx->devtype_data->reset(spi_imx); 1749 1750 spi_imx->devtype_data->intctrl(spi_imx, 0); 1751 1752 master->dev.of_node = pdev->dev.of_node; 1753 ret = spi_bitbang_start(&spi_imx->bitbang); 1754 if (ret) { 1755 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 1756 goto out_clk_put; 1757 } 1758 1759 /* Request GPIO CS lines, if any */ 1760 if (!spi_imx->slave_mode && master->cs_gpios) { 1761 for (i = 0; i < master->num_chipselect; i++) { 1762 if (!gpio_is_valid(master->cs_gpios[i])) 1763 continue; 1764 1765 ret = devm_gpio_request(&pdev->dev, 1766 master->cs_gpios[i], 1767 DRIVER_NAME); 1768 if (ret) { 1769 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", 1770 master->cs_gpios[i]); 1771 goto out_spi_bitbang; 1772 } 1773 } 1774 } 1775 1776 dev_info(&pdev->dev, "probed\n"); 1777 1778 clk_disable(spi_imx->clk_ipg); 1779 clk_disable(spi_imx->clk_per); 1780 return ret; 1781 1782 out_spi_bitbang: 1783 spi_bitbang_stop(&spi_imx->bitbang); 1784 out_clk_put: 1785 clk_disable_unprepare(spi_imx->clk_ipg); 1786 out_put_per: 1787 clk_disable_unprepare(spi_imx->clk_per); 1788 out_master_put: 1789 spi_master_put(master); 1790 1791 return ret; 1792 } 1793 1794 static int spi_imx_remove(struct platform_device *pdev) 1795 { 1796 struct spi_master *master = platform_get_drvdata(pdev); 1797 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1798 int ret; 1799 1800 spi_bitbang_stop(&spi_imx->bitbang); 1801 1802 ret = clk_enable(spi_imx->clk_per); 1803 if (ret) 1804 return ret; 1805 1806 ret = clk_enable(spi_imx->clk_ipg); 1807 if (ret) { 1808 clk_disable(spi_imx->clk_per); 1809 return ret; 1810 } 1811 1812 writel(0, spi_imx->base + MXC_CSPICTRL); 1813 clk_disable_unprepare(spi_imx->clk_ipg); 1814 clk_disable_unprepare(spi_imx->clk_per); 1815 spi_imx_sdma_exit(spi_imx); 1816 spi_master_put(master); 1817 1818 return 0; 1819 } 1820 1821 static struct platform_driver spi_imx_driver = { 1822 .driver = { 1823 .name = DRIVER_NAME, 1824 .of_match_table = spi_imx_dt_ids, 1825 }, 1826 .id_table = spi_imx_devtype, 1827 .probe = spi_imx_probe, 1828 .remove = spi_imx_remove, 1829 }; 1830 module_platform_driver(spi_imx_driver); 1831 1832 MODULE_DESCRIPTION("SPI Controller driver"); 1833 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1834 MODULE_LICENSE("GPL"); 1835 MODULE_ALIAS("platform:" DRIVER_NAME); 1836