1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_SH_IO_H 3 #define __ASM_SH_IO_H 4 5 /* 6 * Convention: 7 * read{b,w,l,q}/write{b,w,l,q} are for PCI, 8 * while in{b,w,l}/out{b,w,l} are for ISA 9 * 10 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p 11 * and 'string' versions: ins{b,w,l}/outs{b,w,l} 12 * 13 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers 14 * automatically, there are also __raw versions, which do not. 15 */ 16 #include <linux/errno.h> 17 #include <asm/cache.h> 18 #include <asm/addrspace.h> 19 #include <asm/machvec.h> 20 #include <linux/pgtable.h> 21 #include <asm-generic/iomap.h> 22 23 #ifdef __KERNEL__ 24 #define __IO_PREFIX generic 25 #include <asm/io_generic.h> 26 #include <asm/io_trapped.h> 27 #include <asm-generic/pci_iomap.h> 28 #include <mach/mangle-port.h> 29 30 #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) 31 #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) 32 #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) 33 #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) 34 35 #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a)) 36 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a)) 37 #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) 38 #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) 39 40 #define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; }) 41 #define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; }) 42 #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; }) 43 #define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; }) 44 45 #define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c)) 46 #define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c)) 47 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) 48 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) 49 50 #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; }) 51 #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; }) 52 #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; }) 53 #define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; }) 54 55 #define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); }) 56 #define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); }) 57 #define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) 58 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); }) 59 60 #define readsb(p,d,l) __raw_readsb(p,d,l) 61 #define readsw(p,d,l) __raw_readsw(p,d,l) 62 #define readsl(p,d,l) __raw_readsl(p,d,l) 63 64 #define writesb(p,d,l) __raw_writesb(p,d,l) 65 #define writesw(p,d,l) __raw_writesw(p,d,l) 66 #define writesl(p,d,l) __raw_writesl(p,d,l) 67 68 #define __BUILD_UNCACHED_IO(bwlq, type) \ 69 static inline type read##bwlq##_uncached(unsigned long addr) \ 70 { \ 71 type ret; \ 72 jump_to_uncached(); \ 73 ret = __raw_read##bwlq(addr); \ 74 back_to_cached(); \ 75 return ret; \ 76 } \ 77 \ 78 static inline void write##bwlq##_uncached(type v, unsigned long addr) \ 79 { \ 80 jump_to_uncached(); \ 81 __raw_write##bwlq(v, addr); \ 82 back_to_cached(); \ 83 } 84 85 __BUILD_UNCACHED_IO(b, u8) 86 __BUILD_UNCACHED_IO(w, u16) 87 __BUILD_UNCACHED_IO(l, u32) 88 __BUILD_UNCACHED_IO(q, u64) 89 90 #define __BUILD_MEMORY_STRING(pfx, bwlq, type) \ 91 \ 92 static inline void \ 93 pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \ 94 unsigned int count) \ 95 { \ 96 const volatile type *__addr = addr; \ 97 \ 98 while (count--) { \ 99 __raw_write##bwlq(*__addr, mem); \ 100 __addr++; \ 101 } \ 102 } \ 103 \ 104 static inline void pfx##reads##bwlq(volatile void __iomem *mem, \ 105 void *addr, unsigned int count) \ 106 { \ 107 volatile type *__addr = addr; \ 108 \ 109 while (count--) { \ 110 *__addr = __raw_read##bwlq(mem); \ 111 __addr++; \ 112 } \ 113 } 114 115 __BUILD_MEMORY_STRING(__raw_, b, u8) 116 __BUILD_MEMORY_STRING(__raw_, w, u16) 117 118 void __raw_writesl(void __iomem *addr, const void *data, int longlen); 119 void __raw_readsl(const void __iomem *addr, void *data, int longlen); 120 121 __BUILD_MEMORY_STRING(__raw_, q, u64) 122 123 #ifdef CONFIG_HAS_IOPORT_MAP 124 125 /* 126 * Slowdown I/O port space accesses for antique hardware. 127 */ 128 #undef CONF_SLOWDOWN_IO 129 130 /* 131 * On SuperH I/O ports are memory mapped, so we access them using normal 132 * load/store instructions. sh_io_port_base is the virtual address to 133 * which all ports are being mapped. 134 */ 135 extern unsigned long sh_io_port_base; 136 137 static inline void __set_io_port_base(unsigned long pbase) 138 { 139 *(unsigned long *)&sh_io_port_base = pbase; 140 barrier(); 141 } 142 143 #ifdef CONFIG_GENERIC_IOMAP 144 #define __ioport_map ioport_map 145 #else 146 extern void __iomem *__ioport_map(unsigned long addr, unsigned int size); 147 #endif 148 149 #ifdef CONF_SLOWDOWN_IO 150 #define SLOW_DOWN_IO __raw_readw(sh_io_port_base) 151 #else 152 #define SLOW_DOWN_IO 153 #endif 154 155 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ 156 \ 157 static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 158 { \ 159 volatile type *__addr; \ 160 \ 161 __addr = __ioport_map(port, sizeof(type)); \ 162 *__addr = val; \ 163 slow; \ 164 } \ 165 \ 166 static inline type pfx##in##bwlq##p(unsigned long port) \ 167 { \ 168 volatile type *__addr; \ 169 type __val; \ 170 \ 171 __addr = __ioport_map(port, sizeof(type)); \ 172 __val = *__addr; \ 173 slow; \ 174 \ 175 return __val; \ 176 } 177 178 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 179 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ 180 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) 181 182 #define BUILDIO_IOPORT(bwlq, type) \ 183 __BUILD_IOPORT_PFX(, bwlq, type) 184 185 BUILDIO_IOPORT(b, u8) 186 BUILDIO_IOPORT(w, u16) 187 BUILDIO_IOPORT(l, u32) 188 BUILDIO_IOPORT(q, u64) 189 190 #define __BUILD_IOPORT_STRING(bwlq, type) \ 191 \ 192 static inline void outs##bwlq(unsigned long port, const void *addr, \ 193 unsigned int count) \ 194 { \ 195 const volatile type *__addr = addr; \ 196 \ 197 while (count--) { \ 198 out##bwlq(*__addr, port); \ 199 __addr++; \ 200 } \ 201 } \ 202 \ 203 static inline void ins##bwlq(unsigned long port, void *addr, \ 204 unsigned int count) \ 205 { \ 206 volatile type *__addr = addr; \ 207 \ 208 while (count--) { \ 209 *__addr = in##bwlq(port); \ 210 __addr++; \ 211 } \ 212 } 213 214 __BUILD_IOPORT_STRING(b, u8) 215 __BUILD_IOPORT_STRING(w, u16) 216 __BUILD_IOPORT_STRING(l, u32) 217 __BUILD_IOPORT_STRING(q, u64) 218 219 #else /* !CONFIG_HAS_IOPORT_MAP */ 220 221 #include <asm/io_noioport.h> 222 223 #endif 224 225 226 #define IO_SPACE_LIMIT 0xffffffff 227 228 /* We really want to try and get these to memcpy etc */ 229 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); 230 void memcpy_toio(volatile void __iomem *, const void *, unsigned long); 231 void memset_io(volatile void __iomem *, int, unsigned long); 232 233 /* Quad-word real-mode I/O, don't ask.. */ 234 unsigned long long peek_real_address_q(unsigned long long addr); 235 unsigned long long poke_real_address_q(unsigned long long addr, 236 unsigned long long val); 237 238 #if !defined(CONFIG_MMU) 239 #define virt_to_phys(address) ((unsigned long)(address)) 240 #define phys_to_virt(address) ((void *)(address)) 241 #else 242 #define virt_to_phys(address) (__pa(address)) 243 #define phys_to_virt(address) (__va(address)) 244 #endif 245 246 /* 247 * On 32-bit SH, we traditionally have the whole physical address space 248 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do 249 * not need to do anything but place the address in the proper segment. 250 * This is true for P1 and P2 addresses, as well as some P3 ones. 251 * However, most of the P3 addresses and newer cores using extended 252 * addressing need to map through page tables, so the ioremap() 253 * implementation becomes a bit more complicated. 254 * 255 * See arch/sh/mm/ioremap.c for additional notes on this. 256 * 257 * We cheat a bit and always return uncachable areas until we've fixed 258 * the drivers to handle caching properly. 259 * 260 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply 261 * doesn't exist, so everything must go through page tables. 262 */ 263 #ifdef CONFIG_MMU 264 void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size, 265 pgprot_t prot, void *caller); 266 void iounmap(void __iomem *addr); 267 268 static inline void __iomem * 269 __ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot) 270 { 271 return __ioremap_caller(offset, size, prot, __builtin_return_address(0)); 272 } 273 274 static inline void __iomem * 275 __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot) 276 { 277 #ifdef CONFIG_29BIT 278 phys_addr_t last_addr = offset + size - 1; 279 280 /* 281 * For P1 and P2 space this is trivial, as everything is already 282 * mapped. Uncached access for P1 addresses are done through P2. 283 * In the P3 case or for addresses outside of the 29-bit space, 284 * mapping must be done by the PMB or by using page tables. 285 */ 286 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { 287 u64 flags = pgprot_val(prot); 288 289 /* 290 * Anything using the legacy PTEA space attributes needs 291 * to be kicked down to page table mappings. 292 */ 293 if (unlikely(flags & _PAGE_PCC_MASK)) 294 return NULL; 295 if (unlikely(flags & _PAGE_CACHABLE)) 296 return (void __iomem *)P1SEGADDR(offset); 297 298 return (void __iomem *)P2SEGADDR(offset); 299 } 300 301 /* P4 above the store queues are always mapped. */ 302 if (unlikely(offset >= P3_ADDR_MAX)) 303 return (void __iomem *)P4SEGADDR(offset); 304 #endif 305 306 return NULL; 307 } 308 309 static inline void __iomem * 310 __ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot) 311 { 312 void __iomem *ret; 313 314 ret = __ioremap_trapped(offset, size); 315 if (ret) 316 return ret; 317 318 ret = __ioremap_29bit(offset, size, prot); 319 if (ret) 320 return ret; 321 322 return __ioremap(offset, size, prot); 323 } 324 #else 325 #define __ioremap(offset, size, prot) ((void __iomem *)(offset)) 326 #define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset)) 327 static inline void iounmap(void __iomem *addr) {} 328 #endif /* CONFIG_MMU */ 329 330 static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) 331 { 332 return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE); 333 } 334 335 static inline void __iomem * 336 ioremap_cache(phys_addr_t offset, unsigned long size) 337 { 338 return __ioremap_mode(offset, size, PAGE_KERNEL); 339 } 340 #define ioremap_cache ioremap_cache 341 342 #ifdef CONFIG_HAVE_IOREMAP_PROT 343 static inline void __iomem * 344 ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags) 345 { 346 return __ioremap_mode(offset, size, __pgprot(flags)); 347 } 348 #endif 349 350 #ifdef CONFIG_IOREMAP_FIXED 351 extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t); 352 extern int iounmap_fixed(void __iomem *); 353 extern void ioremap_fixed_init(void); 354 #else 355 static inline void __iomem * 356 ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot) 357 { 358 BUG(); 359 return NULL; 360 } 361 362 static inline void ioremap_fixed_init(void) { } 363 static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; } 364 #endif 365 366 #define ioremap_uc ioremap 367 368 /* 369 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 370 * access 371 */ 372 #define xlate_dev_mem_ptr(p) __va(p) 373 374 /* 375 * Convert a virtual cached pointer to an uncached pointer 376 */ 377 #define xlate_dev_kmem_ptr(p) p 378 379 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 380 int valid_phys_addr_range(phys_addr_t addr, size_t size); 381 int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 382 383 #endif /* __KERNEL__ */ 384 385 #endif /* __ASM_SH_IO_H */ 386