1 /* 2 * Copyright 2000, 2007-2008 MontaVista Software Inc. 3 * Author: MontaVista Software, Inc. <source@mvista.com 4 * 5 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28 #include <linux/init.h> 29 #include <linux/ioport.h> 30 #include <linux/mm.h> 31 32 #include <asm/dma-coherence.h> 33 #include <asm/mipsregs.h> 34 35 #include <au1000.h> 36 37 extern void __init board_setup(void); 38 extern void __init alchemy_set_lpj(void); 39 40 void __init plat_mem_setup(void) 41 { 42 alchemy_set_lpj(); 43 44 if (au1xxx_cpu_needs_config_od()) 45 /* Various early Au1xx0 errata corrected by this */ 46 set_c0_config(1 << 19); /* Set Config[OD] */ 47 else 48 /* Clear to obtain best system bus performance */ 49 clear_c0_config(1 << 19); /* Clear Config[OD] */ 50 51 hw_coherentio = 0; 52 coherentio = IO_COHERENCE_ENABLED; 53 switch (alchemy_get_cputype()) { 54 case ALCHEMY_CPU_AU1000: 55 case ALCHEMY_CPU_AU1500: 56 case ALCHEMY_CPU_AU1100: 57 coherentio = IO_COHERENCE_DISABLED; 58 break; 59 case ALCHEMY_CPU_AU1200: 60 /* Au1200 AB USB does not support coherent memory */ 61 if (0 == (read_c0_prid() & PRID_REV_MASK)) 62 coherentio = IO_COHERENCE_DISABLED; 63 break; 64 } 65 66 board_setup(); /* board specific setup */ 67 68 /* IO/MEM resources. */ 69 set_io_port_base(0); 70 ioport_resource.start = IOPORT_RESOURCE_START; 71 ioport_resource.end = IOPORT_RESOURCE_END; 72 iomem_resource.start = IOMEM_RESOURCE_START; 73 iomem_resource.end = IOMEM_RESOURCE_END; 74 } 75 76 #ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR 77 /* This routine should be valid for all Au1x based boards */ 78 phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) 79 { 80 unsigned long start = ALCHEMY_PCI_MEMWIN_START; 81 unsigned long end = ALCHEMY_PCI_MEMWIN_END; 82 83 /* Don't fixup 36-bit addresses */ 84 if ((phys_addr >> 32) != 0) 85 return phys_addr; 86 87 /* Check for PCI memory window */ 88 if (phys_addr >= start && (phys_addr + size - 1) <= end) 89 return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr); 90 91 /* default nop */ 92 return phys_addr; 93 } 94 95 int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr, 96 unsigned long pfn, unsigned long size, pgprot_t prot) 97 { 98 phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size); 99 100 return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot); 101 } 102 EXPORT_SYMBOL(io_remap_pfn_range); 103 #endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */ 104