1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dce/dce_8_0_d.h" 29 #include "dce/dce_8_0_sh_mask.h" 30 31 #include "dm_services.h" 32 33 #include "link_encoder.h" 34 #include "stream_encoder.h" 35 36 #include "resource.h" 37 #include "include/irq_service_interface.h" 38 #include "irq/dce80/irq_service_dce80.h" 39 #include "dce110/dce110_timing_generator.h" 40 #include "dce110/dce110_resource.h" 41 #include "dce80/dce80_timing_generator.h" 42 #include "dce/dce_mem_input.h" 43 #include "dce/dce_link_encoder.h" 44 #include "dce/dce_stream_encoder.h" 45 #include "dce/dce_ipp.h" 46 #include "dce/dce_transform.h" 47 #include "dce/dce_opp.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_abm.h" 59 #include "dce/dce_i2c.h" 60 /* TODO remove this include */ 61 62 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 63 #include "gmc/gmc_7_1_d.h" 64 #include "gmc/gmc_7_1_sh_mask.h" 65 #endif 66 67 #ifndef mmDP_DPHY_INTERNAL_CTRL 68 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 69 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 71 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 72 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 73 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 74 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 75 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 76 #endif 77 78 79 #ifndef mmBIOS_SCRATCH_2 80 #define mmBIOS_SCRATCH_2 0x05CB 81 #define mmBIOS_SCRATCH_3 0x05CC 82 #define mmBIOS_SCRATCH_6 0x05CF 83 #endif 84 85 #ifndef mmDP_DPHY_FAST_TRAINING 86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 93 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 94 #endif 95 96 97 #ifndef mmHPD_DC_HPD_CONTROL 98 #define mmHPD_DC_HPD_CONTROL 0x189A 99 #define mmHPD0_DC_HPD_CONTROL 0x189A 100 #define mmHPD1_DC_HPD_CONTROL 0x18A2 101 #define mmHPD2_DC_HPD_CONTROL 0x18AA 102 #define mmHPD3_DC_HPD_CONTROL 0x18B2 103 #define mmHPD4_DC_HPD_CONTROL 0x18BA 104 #define mmHPD5_DC_HPD_CONTROL 0x18C2 105 #endif 106 107 #define DCE11_DIG_FE_CNTL 0x4a00 108 #define DCE11_DIG_BE_CNTL 0x4a47 109 #define DCE11_DP_SEC 0x4ac3 110 111 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 112 { 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 115 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 116 - mmDPG_WATERMARK_MASK_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 121 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 122 - mmDPG_WATERMARK_MASK_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 128 - mmDPG_WATERMARK_MASK_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 134 - mmDPG_WATERMARK_MASK_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 139 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 140 - mmDPG_WATERMARK_MASK_CONTROL), 141 }, 142 { 143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 144 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 145 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 146 - mmDPG_WATERMARK_MASK_CONTROL), 147 } 148 }; 149 150 /* set register offset */ 151 #define SR(reg_name)\ 152 .reg_name = mm ## reg_name 153 154 /* set register offset with instance */ 155 #define SRI(reg_name, block, id)\ 156 .reg_name = mm ## block ## id ## _ ## reg_name 157 158 #define ipp_regs(id)\ 159 [id] = {\ 160 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 161 } 162 163 static const struct dce_ipp_registers ipp_regs[] = { 164 ipp_regs(0), 165 ipp_regs(1), 166 ipp_regs(2), 167 ipp_regs(3), 168 ipp_regs(4), 169 ipp_regs(5) 170 }; 171 172 static const struct dce_ipp_shift ipp_shift = { 173 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 174 }; 175 176 static const struct dce_ipp_mask ipp_mask = { 177 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 178 }; 179 180 #define transform_regs(id)\ 181 [id] = {\ 182 XFM_COMMON_REG_LIST_DCE80(id)\ 183 } 184 185 static const struct dce_transform_registers xfm_regs[] = { 186 transform_regs(0), 187 transform_regs(1), 188 transform_regs(2), 189 transform_regs(3), 190 transform_regs(4), 191 transform_regs(5) 192 }; 193 194 static const struct dce_transform_shift xfm_shift = { 195 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 196 }; 197 198 static const struct dce_transform_mask xfm_mask = { 199 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 200 }; 201 202 #define aux_regs(id)\ 203 [id] = {\ 204 AUX_REG_LIST(id)\ 205 } 206 207 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 208 aux_regs(0), 209 aux_regs(1), 210 aux_regs(2), 211 aux_regs(3), 212 aux_regs(4), 213 aux_regs(5) 214 }; 215 216 #define hpd_regs(id)\ 217 [id] = {\ 218 HPD_REG_LIST(id)\ 219 } 220 221 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 222 hpd_regs(0), 223 hpd_regs(1), 224 hpd_regs(2), 225 hpd_regs(3), 226 hpd_regs(4), 227 hpd_regs(5) 228 }; 229 230 #define link_regs(id)\ 231 [id] = {\ 232 LE_DCE80_REG_LIST(id)\ 233 } 234 235 static const struct dce110_link_enc_registers link_enc_regs[] = { 236 link_regs(0), 237 link_regs(1), 238 link_regs(2), 239 link_regs(3), 240 link_regs(4), 241 link_regs(5), 242 link_regs(6), 243 }; 244 245 #define stream_enc_regs(id)\ 246 [id] = {\ 247 SE_COMMON_REG_LIST_DCE_BASE(id),\ 248 .AFMT_CNTL = 0,\ 249 } 250 251 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 252 stream_enc_regs(0), 253 stream_enc_regs(1), 254 stream_enc_regs(2), 255 stream_enc_regs(3), 256 stream_enc_regs(4), 257 stream_enc_regs(5), 258 stream_enc_regs(6) 259 }; 260 261 static const struct dce_stream_encoder_shift se_shift = { 262 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 263 }; 264 265 static const struct dce_stream_encoder_mask se_mask = { 266 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 267 }; 268 269 #define opp_regs(id)\ 270 [id] = {\ 271 OPP_DCE_80_REG_LIST(id),\ 272 } 273 274 static const struct dce_opp_registers opp_regs[] = { 275 opp_regs(0), 276 opp_regs(1), 277 opp_regs(2), 278 opp_regs(3), 279 opp_regs(4), 280 opp_regs(5) 281 }; 282 283 static const struct dce_opp_shift opp_shift = { 284 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 285 }; 286 287 static const struct dce_opp_mask opp_mask = { 288 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 289 }; 290 291 static const struct dce110_aux_registers_shift aux_shift = { 292 DCE10_AUX_MASK_SH_LIST(__SHIFT) 293 }; 294 295 static const struct dce110_aux_registers_mask aux_mask = { 296 DCE10_AUX_MASK_SH_LIST(_MASK) 297 }; 298 299 #define aux_engine_regs(id)\ 300 [id] = {\ 301 AUX_COMMON_REG_LIST(id), \ 302 .AUX_RESET_MASK = 0 \ 303 } 304 305 static const struct dce110_aux_registers aux_engine_regs[] = { 306 aux_engine_regs(0), 307 aux_engine_regs(1), 308 aux_engine_regs(2), 309 aux_engine_regs(3), 310 aux_engine_regs(4), 311 aux_engine_regs(5) 312 }; 313 314 #define audio_regs(id)\ 315 [id] = {\ 316 AUD_COMMON_REG_LIST(id)\ 317 } 318 319 static const struct dce_audio_registers audio_regs[] = { 320 audio_regs(0), 321 audio_regs(1), 322 audio_regs(2), 323 audio_regs(3), 324 audio_regs(4), 325 audio_regs(5), 326 audio_regs(6), 327 }; 328 329 static const struct dce_audio_shift audio_shift = { 330 AUD_COMMON_MASK_SH_LIST(__SHIFT) 331 }; 332 333 static const struct dce_audio_mask audio_mask = { 334 AUD_COMMON_MASK_SH_LIST(_MASK) 335 }; 336 337 #define clk_src_regs(id)\ 338 [id] = {\ 339 CS_COMMON_REG_LIST_DCE_80(id),\ 340 } 341 342 343 static const struct dce110_clk_src_regs clk_src_regs[] = { 344 clk_src_regs(0), 345 clk_src_regs(1), 346 clk_src_regs(2) 347 }; 348 349 static const struct dce110_clk_src_shift cs_shift = { 350 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 351 }; 352 353 static const struct dce110_clk_src_mask cs_mask = { 354 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 355 }; 356 357 static const struct bios_registers bios_regs = { 358 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 359 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 360 }; 361 362 static const struct resource_caps res_cap = { 363 .num_timing_generator = 6, 364 .num_audio = 6, 365 .num_stream_encoder = 6, 366 .num_pll = 3, 367 .num_ddc = 6, 368 }; 369 370 static const struct resource_caps res_cap_81 = { 371 .num_timing_generator = 4, 372 .num_audio = 7, 373 .num_stream_encoder = 7, 374 .num_pll = 3, 375 .num_ddc = 6, 376 }; 377 378 static const struct resource_caps res_cap_83 = { 379 .num_timing_generator = 2, 380 .num_audio = 6, 381 .num_stream_encoder = 6, 382 .num_pll = 2, 383 .num_ddc = 2, 384 }; 385 386 static const struct dc_plane_cap plane_cap = { 387 .type = DC_PLANE_TYPE_DCE_RGB, 388 389 .pixel_format_support = { 390 .argb8888 = true, 391 .nv12 = false, 392 .fp16 = false 393 }, 394 395 .max_upscale_factor = { 396 .argb8888 = 16000, 397 .nv12 = 1, 398 .fp16 = 1 399 }, 400 401 .max_downscale_factor = { 402 .argb8888 = 250, 403 .nv12 = 1, 404 .fp16 = 1 405 } 406 }; 407 408 static const struct dce_dmcu_registers dmcu_regs = { 409 DMCU_DCE80_REG_LIST() 410 }; 411 412 static const struct dce_dmcu_shift dmcu_shift = { 413 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 414 }; 415 416 static const struct dce_dmcu_mask dmcu_mask = { 417 DMCU_MASK_SH_LIST_DCE80(_MASK) 418 }; 419 static const struct dce_abm_registers abm_regs = { 420 ABM_DCE110_COMMON_REG_LIST() 421 }; 422 423 static const struct dce_abm_shift abm_shift = { 424 ABM_MASK_SH_LIST_DCE110(__SHIFT) 425 }; 426 427 static const struct dce_abm_mask abm_mask = { 428 ABM_MASK_SH_LIST_DCE110(_MASK) 429 }; 430 431 #define CTX ctx 432 #define REG(reg) mm ## reg 433 434 #ifndef mmCC_DC_HDMI_STRAPS 435 #define mmCC_DC_HDMI_STRAPS 0x1918 436 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 437 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 438 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 439 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 440 #endif 441 442 static int map_transmitter_id_to_phy_instance( 443 enum transmitter transmitter) 444 { 445 switch (transmitter) { 446 case TRANSMITTER_UNIPHY_A: 447 return 0; 448 break; 449 case TRANSMITTER_UNIPHY_B: 450 return 1; 451 break; 452 case TRANSMITTER_UNIPHY_C: 453 return 2; 454 break; 455 case TRANSMITTER_UNIPHY_D: 456 return 3; 457 break; 458 case TRANSMITTER_UNIPHY_E: 459 return 4; 460 break; 461 case TRANSMITTER_UNIPHY_F: 462 return 5; 463 break; 464 case TRANSMITTER_UNIPHY_G: 465 return 6; 466 break; 467 default: 468 ASSERT(0); 469 return 0; 470 } 471 } 472 473 static void read_dce_straps( 474 struct dc_context *ctx, 475 struct resource_straps *straps) 476 { 477 REG_GET_2(CC_DC_HDMI_STRAPS, 478 HDMI_DISABLE, &straps->hdmi_disable, 479 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 480 481 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 482 } 483 484 static struct audio *create_audio( 485 struct dc_context *ctx, unsigned int inst) 486 { 487 return dce_audio_create(ctx, inst, 488 &audio_regs[inst], &audio_shift, &audio_mask); 489 } 490 491 static struct timing_generator *dce80_timing_generator_create( 492 struct dc_context *ctx, 493 uint32_t instance, 494 const struct dce110_timing_generator_offsets *offsets) 495 { 496 struct dce110_timing_generator *tg110 = 497 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 498 499 if (!tg110) 500 return NULL; 501 502 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 503 return &tg110->base; 504 } 505 506 static struct output_pixel_processor *dce80_opp_create( 507 struct dc_context *ctx, 508 uint32_t inst) 509 { 510 struct dce110_opp *opp = 511 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 512 513 if (!opp) 514 return NULL; 515 516 dce110_opp_construct(opp, 517 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 518 return &opp->base; 519 } 520 521 struct dce_aux *dce80_aux_engine_create( 522 struct dc_context *ctx, 523 uint32_t inst) 524 { 525 struct aux_engine_dce110 *aux_engine = 526 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 527 528 if (!aux_engine) 529 return NULL; 530 531 dce110_aux_engine_construct(aux_engine, ctx, inst, 532 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 533 &aux_engine_regs[inst], 534 &aux_mask, 535 &aux_shift, 536 ctx->dc->caps.extended_aux_timeout_support); 537 538 return &aux_engine->base; 539 } 540 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 541 542 static const struct dce_i2c_registers i2c_hw_regs[] = { 543 i2c_inst_regs(1), 544 i2c_inst_regs(2), 545 i2c_inst_regs(3), 546 i2c_inst_regs(4), 547 i2c_inst_regs(5), 548 i2c_inst_regs(6), 549 }; 550 551 static const struct dce_i2c_shift i2c_shifts = { 552 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 553 }; 554 555 static const struct dce_i2c_mask i2c_masks = { 556 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 557 }; 558 559 struct dce_i2c_hw *dce80_i2c_hw_create( 560 struct dc_context *ctx, 561 uint32_t inst) 562 { 563 struct dce_i2c_hw *dce_i2c_hw = 564 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 565 566 if (!dce_i2c_hw) 567 return NULL; 568 569 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst, 570 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 571 572 return dce_i2c_hw; 573 } 574 575 struct dce_i2c_sw *dce80_i2c_sw_create( 576 struct dc_context *ctx) 577 { 578 struct dce_i2c_sw *dce_i2c_sw = 579 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL); 580 581 if (!dce_i2c_sw) 582 return NULL; 583 584 dce_i2c_sw_construct(dce_i2c_sw, ctx); 585 586 return dce_i2c_sw; 587 } 588 static struct stream_encoder *dce80_stream_encoder_create( 589 enum engine_id eng_id, 590 struct dc_context *ctx) 591 { 592 struct dce110_stream_encoder *enc110 = 593 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 594 595 if (!enc110) 596 return NULL; 597 598 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 599 &stream_enc_regs[eng_id], 600 &se_shift, &se_mask); 601 return &enc110->base; 602 } 603 604 #define SRII(reg_name, block, id)\ 605 .reg_name[id] = mm ## block ## id ## _ ## reg_name 606 607 static const struct dce_hwseq_registers hwseq_reg = { 608 HWSEQ_DCE8_REG_LIST() 609 }; 610 611 static const struct dce_hwseq_shift hwseq_shift = { 612 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 613 }; 614 615 static const struct dce_hwseq_mask hwseq_mask = { 616 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 617 }; 618 619 static struct dce_hwseq *dce80_hwseq_create( 620 struct dc_context *ctx) 621 { 622 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 623 624 if (hws) { 625 hws->ctx = ctx; 626 hws->regs = &hwseq_reg; 627 hws->shifts = &hwseq_shift; 628 hws->masks = &hwseq_mask; 629 } 630 return hws; 631 } 632 633 static const struct resource_create_funcs res_create_funcs = { 634 .read_dce_straps = read_dce_straps, 635 .create_audio = create_audio, 636 .create_stream_encoder = dce80_stream_encoder_create, 637 .create_hwseq = dce80_hwseq_create, 638 }; 639 640 #define mi_inst_regs(id) { \ 641 MI_DCE8_REG_LIST(id), \ 642 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 643 } 644 static const struct dce_mem_input_registers mi_regs[] = { 645 mi_inst_regs(0), 646 mi_inst_regs(1), 647 mi_inst_regs(2), 648 mi_inst_regs(3), 649 mi_inst_regs(4), 650 mi_inst_regs(5), 651 }; 652 653 static const struct dce_mem_input_shift mi_shifts = { 654 MI_DCE8_MASK_SH_LIST(__SHIFT), 655 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 656 }; 657 658 static const struct dce_mem_input_mask mi_masks = { 659 MI_DCE8_MASK_SH_LIST(_MASK), 660 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 661 }; 662 663 static struct mem_input *dce80_mem_input_create( 664 struct dc_context *ctx, 665 uint32_t inst) 666 { 667 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 668 GFP_KERNEL); 669 670 if (!dce_mi) { 671 BREAK_TO_DEBUGGER(); 672 return NULL; 673 } 674 675 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 676 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 677 return &dce_mi->base; 678 } 679 680 static void dce80_transform_destroy(struct transform **xfm) 681 { 682 kfree(TO_DCE_TRANSFORM(*xfm)); 683 *xfm = NULL; 684 } 685 686 static struct transform *dce80_transform_create( 687 struct dc_context *ctx, 688 uint32_t inst) 689 { 690 struct dce_transform *transform = 691 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 692 693 if (!transform) 694 return NULL; 695 696 dce_transform_construct(transform, ctx, inst, 697 &xfm_regs[inst], &xfm_shift, &xfm_mask); 698 transform->prescaler_on = false; 699 return &transform->base; 700 } 701 702 static const struct encoder_feature_support link_enc_feature = { 703 .max_hdmi_deep_color = COLOR_DEPTH_121212, 704 .max_hdmi_pixel_clock = 297000, 705 .flags.bits.IS_HBR2_CAPABLE = true, 706 .flags.bits.IS_TPS3_CAPABLE = true 707 }; 708 709 struct link_encoder *dce80_link_encoder_create( 710 const struct encoder_init_data *enc_init_data) 711 { 712 struct dce110_link_encoder *enc110 = 713 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 714 int link_regs_id; 715 716 if (!enc110) 717 return NULL; 718 719 link_regs_id = 720 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 721 722 dce110_link_encoder_construct(enc110, 723 enc_init_data, 724 &link_enc_feature, 725 &link_enc_regs[link_regs_id], 726 &link_enc_aux_regs[enc_init_data->channel - 1], 727 &link_enc_hpd_regs[enc_init_data->hpd_source]); 728 return &enc110->base; 729 } 730 731 struct clock_source *dce80_clock_source_create( 732 struct dc_context *ctx, 733 struct dc_bios *bios, 734 enum clock_source_id id, 735 const struct dce110_clk_src_regs *regs, 736 bool dp_clk_src) 737 { 738 struct dce110_clk_src *clk_src = 739 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 740 741 if (!clk_src) 742 return NULL; 743 744 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 745 regs, &cs_shift, &cs_mask)) { 746 clk_src->base.dp_clk_src = dp_clk_src; 747 return &clk_src->base; 748 } 749 750 kfree(clk_src); 751 BREAK_TO_DEBUGGER(); 752 return NULL; 753 } 754 755 void dce80_clock_source_destroy(struct clock_source **clk_src) 756 { 757 kfree(TO_DCE110_CLK_SRC(*clk_src)); 758 *clk_src = NULL; 759 } 760 761 static struct input_pixel_processor *dce80_ipp_create( 762 struct dc_context *ctx, uint32_t inst) 763 { 764 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 765 766 if (!ipp) { 767 BREAK_TO_DEBUGGER(); 768 return NULL; 769 } 770 771 dce_ipp_construct(ipp, ctx, inst, 772 &ipp_regs[inst], &ipp_shift, &ipp_mask); 773 return &ipp->base; 774 } 775 776 static void dce80_resource_destruct(struct dce110_resource_pool *pool) 777 { 778 unsigned int i; 779 780 for (i = 0; i < pool->base.pipe_count; i++) { 781 if (pool->base.opps[i] != NULL) 782 dce110_opp_destroy(&pool->base.opps[i]); 783 784 if (pool->base.transforms[i] != NULL) 785 dce80_transform_destroy(&pool->base.transforms[i]); 786 787 if (pool->base.ipps[i] != NULL) 788 dce_ipp_destroy(&pool->base.ipps[i]); 789 790 if (pool->base.mis[i] != NULL) { 791 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 792 pool->base.mis[i] = NULL; 793 } 794 795 if (pool->base.timing_generators[i] != NULL) { 796 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 797 pool->base.timing_generators[i] = NULL; 798 } 799 } 800 801 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 802 if (pool->base.engines[i] != NULL) 803 dce110_engine_destroy(&pool->base.engines[i]); 804 if (pool->base.hw_i2cs[i] != NULL) { 805 kfree(pool->base.hw_i2cs[i]); 806 pool->base.hw_i2cs[i] = NULL; 807 } 808 if (pool->base.sw_i2cs[i] != NULL) { 809 kfree(pool->base.sw_i2cs[i]); 810 pool->base.sw_i2cs[i] = NULL; 811 } 812 } 813 814 for (i = 0; i < pool->base.stream_enc_count; i++) { 815 if (pool->base.stream_enc[i] != NULL) 816 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 817 } 818 819 for (i = 0; i < pool->base.clk_src_count; i++) { 820 if (pool->base.clock_sources[i] != NULL) { 821 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 822 } 823 } 824 825 if (pool->base.abm != NULL) 826 dce_abm_destroy(&pool->base.abm); 827 828 if (pool->base.dmcu != NULL) 829 dce_dmcu_destroy(&pool->base.dmcu); 830 831 if (pool->base.dp_clock_source != NULL) 832 dce80_clock_source_destroy(&pool->base.dp_clock_source); 833 834 for (i = 0; i < pool->base.audio_count; i++) { 835 if (pool->base.audios[i] != NULL) { 836 dce_aud_destroy(&pool->base.audios[i]); 837 } 838 } 839 840 if (pool->base.irqs != NULL) { 841 dal_irq_service_destroy(&pool->base.irqs); 842 } 843 } 844 845 bool dce80_validate_bandwidth( 846 struct dc *dc, 847 struct dc_state *context, 848 bool fast_validate) 849 { 850 int i; 851 bool at_least_one_pipe = false; 852 853 for (i = 0; i < dc->res_pool->pipe_count; i++) { 854 if (context->res_ctx.pipe_ctx[i].stream) 855 at_least_one_pipe = true; 856 } 857 858 if (at_least_one_pipe) { 859 /* TODO implement when needed but for now hardcode max value*/ 860 context->bw_ctx.bw.dce.dispclk_khz = 681000; 861 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; 862 } else { 863 context->bw_ctx.bw.dce.dispclk_khz = 0; 864 context->bw_ctx.bw.dce.yclk_khz = 0; 865 } 866 867 return true; 868 } 869 870 static bool dce80_validate_surface_sets( 871 struct dc_state *context) 872 { 873 int i; 874 875 for (i = 0; i < context->stream_count; i++) { 876 if (context->stream_status[i].plane_count == 0) 877 continue; 878 879 if (context->stream_status[i].plane_count > 1) 880 return false; 881 882 if (context->stream_status[i].plane_states[0]->format 883 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 884 return false; 885 } 886 887 return true; 888 } 889 890 enum dc_status dce80_validate_global( 891 struct dc *dc, 892 struct dc_state *context) 893 { 894 if (!dce80_validate_surface_sets(context)) 895 return DC_FAIL_SURFACE_VALIDATE; 896 897 return DC_OK; 898 } 899 900 static void dce80_destroy_resource_pool(struct resource_pool **pool) 901 { 902 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 903 904 dce80_resource_destruct(dce110_pool); 905 kfree(dce110_pool); 906 *pool = NULL; 907 } 908 909 static const struct resource_funcs dce80_res_pool_funcs = { 910 .destroy = dce80_destroy_resource_pool, 911 .link_enc_create = dce80_link_encoder_create, 912 .validate_bandwidth = dce80_validate_bandwidth, 913 .validate_plane = dce100_validate_plane, 914 .add_stream_to_ctx = dce100_add_stream_to_ctx, 915 .validate_global = dce80_validate_global, 916 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link 917 }; 918 919 static bool dce80_construct( 920 uint8_t num_virtual_links, 921 struct dc *dc, 922 struct dce110_resource_pool *pool) 923 { 924 unsigned int i; 925 struct dc_context *ctx = dc->ctx; 926 struct dc_bios *bp; 927 928 ctx->dc_bios->regs = &bios_regs; 929 930 pool->base.res_cap = &res_cap; 931 pool->base.funcs = &dce80_res_pool_funcs; 932 933 934 /************************************************* 935 * Resource + asic cap harcoding * 936 *************************************************/ 937 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 938 pool->base.pipe_count = res_cap.num_timing_generator; 939 pool->base.timing_generator_count = res_cap.num_timing_generator; 940 dc->caps.max_downscale_ratio = 200; 941 dc->caps.i2c_speed_in_khz = 40; 942 dc->caps.max_cursor_size = 128; 943 dc->caps.dual_link_dvi = true; 944 dc->caps.extended_aux_timeout_support = false; 945 946 /************************************************* 947 * Create resources * 948 *************************************************/ 949 950 bp = ctx->dc_bios; 951 952 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 953 pool->base.dp_clock_source = 954 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 955 956 pool->base.clock_sources[0] = 957 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 958 pool->base.clock_sources[1] = 959 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 960 pool->base.clock_sources[2] = 961 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 962 pool->base.clk_src_count = 3; 963 964 } else { 965 pool->base.dp_clock_source = 966 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 967 968 pool->base.clock_sources[0] = 969 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 970 pool->base.clock_sources[1] = 971 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 972 pool->base.clk_src_count = 2; 973 } 974 975 if (pool->base.dp_clock_source == NULL) { 976 dm_error("DC: failed to create dp clock source!\n"); 977 BREAK_TO_DEBUGGER(); 978 goto res_create_fail; 979 } 980 981 for (i = 0; i < pool->base.clk_src_count; i++) { 982 if (pool->base.clock_sources[i] == NULL) { 983 dm_error("DC: failed to create clock sources!\n"); 984 BREAK_TO_DEBUGGER(); 985 goto res_create_fail; 986 } 987 } 988 989 pool->base.dmcu = dce_dmcu_create(ctx, 990 &dmcu_regs, 991 &dmcu_shift, 992 &dmcu_mask); 993 if (pool->base.dmcu == NULL) { 994 dm_error("DC: failed to create dmcu!\n"); 995 BREAK_TO_DEBUGGER(); 996 goto res_create_fail; 997 } 998 999 pool->base.abm = dce_abm_create(ctx, 1000 &abm_regs, 1001 &abm_shift, 1002 &abm_mask); 1003 if (pool->base.abm == NULL) { 1004 dm_error("DC: failed to create abm!\n"); 1005 BREAK_TO_DEBUGGER(); 1006 goto res_create_fail; 1007 } 1008 1009 { 1010 struct irq_service_init_data init_data; 1011 init_data.ctx = dc->ctx; 1012 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1013 if (!pool->base.irqs) 1014 goto res_create_fail; 1015 } 1016 1017 for (i = 0; i < pool->base.pipe_count; i++) { 1018 pool->base.timing_generators[i] = dce80_timing_generator_create( 1019 ctx, i, &dce80_tg_offsets[i]); 1020 if (pool->base.timing_generators[i] == NULL) { 1021 BREAK_TO_DEBUGGER(); 1022 dm_error("DC: failed to create tg!\n"); 1023 goto res_create_fail; 1024 } 1025 1026 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1027 if (pool->base.mis[i] == NULL) { 1028 BREAK_TO_DEBUGGER(); 1029 dm_error("DC: failed to create memory input!\n"); 1030 goto res_create_fail; 1031 } 1032 1033 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1034 if (pool->base.ipps[i] == NULL) { 1035 BREAK_TO_DEBUGGER(); 1036 dm_error("DC: failed to create input pixel processor!\n"); 1037 goto res_create_fail; 1038 } 1039 1040 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1041 if (pool->base.transforms[i] == NULL) { 1042 BREAK_TO_DEBUGGER(); 1043 dm_error("DC: failed to create transform!\n"); 1044 goto res_create_fail; 1045 } 1046 1047 pool->base.opps[i] = dce80_opp_create(ctx, i); 1048 if (pool->base.opps[i] == NULL) { 1049 BREAK_TO_DEBUGGER(); 1050 dm_error("DC: failed to create output pixel processor!\n"); 1051 goto res_create_fail; 1052 } 1053 } 1054 1055 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1056 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1057 if (pool->base.engines[i] == NULL) { 1058 BREAK_TO_DEBUGGER(); 1059 dm_error( 1060 "DC:failed to create aux engine!!\n"); 1061 goto res_create_fail; 1062 } 1063 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1064 if (pool->base.hw_i2cs[i] == NULL) { 1065 BREAK_TO_DEBUGGER(); 1066 dm_error( 1067 "DC:failed to create i2c engine!!\n"); 1068 goto res_create_fail; 1069 } 1070 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1071 if (pool->base.sw_i2cs[i] == NULL) { 1072 BREAK_TO_DEBUGGER(); 1073 dm_error( 1074 "DC:failed to create sw i2c!!\n"); 1075 goto res_create_fail; 1076 } 1077 } 1078 1079 dc->caps.max_planes = pool->base.pipe_count; 1080 1081 for (i = 0; i < dc->caps.max_planes; ++i) 1082 dc->caps.planes[i] = plane_cap; 1083 1084 dc->caps.disable_dp_clk_share = true; 1085 1086 if (!resource_construct(num_virtual_links, dc, &pool->base, 1087 &res_create_funcs)) 1088 goto res_create_fail; 1089 1090 /* Create hardware sequencer */ 1091 dce80_hw_sequencer_construct(dc); 1092 1093 return true; 1094 1095 res_create_fail: 1096 dce80_resource_destruct(pool); 1097 return false; 1098 } 1099 1100 struct resource_pool *dce80_create_resource_pool( 1101 uint8_t num_virtual_links, 1102 struct dc *dc) 1103 { 1104 struct dce110_resource_pool *pool = 1105 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1106 1107 if (!pool) 1108 return NULL; 1109 1110 if (dce80_construct(num_virtual_links, dc, pool)) 1111 return &pool->base; 1112 1113 BREAK_TO_DEBUGGER(); 1114 return NULL; 1115 } 1116 1117 static bool dce81_construct( 1118 uint8_t num_virtual_links, 1119 struct dc *dc, 1120 struct dce110_resource_pool *pool) 1121 { 1122 unsigned int i; 1123 struct dc_context *ctx = dc->ctx; 1124 struct dc_bios *bp; 1125 1126 ctx->dc_bios->regs = &bios_regs; 1127 1128 pool->base.res_cap = &res_cap_81; 1129 pool->base.funcs = &dce80_res_pool_funcs; 1130 1131 1132 /************************************************* 1133 * Resource + asic cap harcoding * 1134 *************************************************/ 1135 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1136 pool->base.pipe_count = res_cap_81.num_timing_generator; 1137 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1138 dc->caps.max_downscale_ratio = 200; 1139 dc->caps.i2c_speed_in_khz = 40; 1140 dc->caps.max_cursor_size = 128; 1141 dc->caps.is_apu = true; 1142 1143 /************************************************* 1144 * Create resources * 1145 *************************************************/ 1146 1147 bp = ctx->dc_bios; 1148 1149 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1150 pool->base.dp_clock_source = 1151 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1152 1153 pool->base.clock_sources[0] = 1154 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1155 pool->base.clock_sources[1] = 1156 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1157 pool->base.clock_sources[2] = 1158 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1159 pool->base.clk_src_count = 3; 1160 1161 } else { 1162 pool->base.dp_clock_source = 1163 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1164 1165 pool->base.clock_sources[0] = 1166 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1167 pool->base.clock_sources[1] = 1168 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1169 pool->base.clk_src_count = 2; 1170 } 1171 1172 if (pool->base.dp_clock_source == NULL) { 1173 dm_error("DC: failed to create dp clock source!\n"); 1174 BREAK_TO_DEBUGGER(); 1175 goto res_create_fail; 1176 } 1177 1178 for (i = 0; i < pool->base.clk_src_count; i++) { 1179 if (pool->base.clock_sources[i] == NULL) { 1180 dm_error("DC: failed to create clock sources!\n"); 1181 BREAK_TO_DEBUGGER(); 1182 goto res_create_fail; 1183 } 1184 } 1185 1186 pool->base.dmcu = dce_dmcu_create(ctx, 1187 &dmcu_regs, 1188 &dmcu_shift, 1189 &dmcu_mask); 1190 if (pool->base.dmcu == NULL) { 1191 dm_error("DC: failed to create dmcu!\n"); 1192 BREAK_TO_DEBUGGER(); 1193 goto res_create_fail; 1194 } 1195 1196 pool->base.abm = dce_abm_create(ctx, 1197 &abm_regs, 1198 &abm_shift, 1199 &abm_mask); 1200 if (pool->base.abm == NULL) { 1201 dm_error("DC: failed to create abm!\n"); 1202 BREAK_TO_DEBUGGER(); 1203 goto res_create_fail; 1204 } 1205 1206 { 1207 struct irq_service_init_data init_data; 1208 init_data.ctx = dc->ctx; 1209 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1210 if (!pool->base.irqs) 1211 goto res_create_fail; 1212 } 1213 1214 for (i = 0; i < pool->base.pipe_count; i++) { 1215 pool->base.timing_generators[i] = dce80_timing_generator_create( 1216 ctx, i, &dce80_tg_offsets[i]); 1217 if (pool->base.timing_generators[i] == NULL) { 1218 BREAK_TO_DEBUGGER(); 1219 dm_error("DC: failed to create tg!\n"); 1220 goto res_create_fail; 1221 } 1222 1223 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1224 if (pool->base.mis[i] == NULL) { 1225 BREAK_TO_DEBUGGER(); 1226 dm_error("DC: failed to create memory input!\n"); 1227 goto res_create_fail; 1228 } 1229 1230 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1231 if (pool->base.ipps[i] == NULL) { 1232 BREAK_TO_DEBUGGER(); 1233 dm_error("DC: failed to create input pixel processor!\n"); 1234 goto res_create_fail; 1235 } 1236 1237 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1238 if (pool->base.transforms[i] == NULL) { 1239 BREAK_TO_DEBUGGER(); 1240 dm_error("DC: failed to create transform!\n"); 1241 goto res_create_fail; 1242 } 1243 1244 pool->base.opps[i] = dce80_opp_create(ctx, i); 1245 if (pool->base.opps[i] == NULL) { 1246 BREAK_TO_DEBUGGER(); 1247 dm_error("DC: failed to create output pixel processor!\n"); 1248 goto res_create_fail; 1249 } 1250 } 1251 1252 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1253 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1254 if (pool->base.engines[i] == NULL) { 1255 BREAK_TO_DEBUGGER(); 1256 dm_error( 1257 "DC:failed to create aux engine!!\n"); 1258 goto res_create_fail; 1259 } 1260 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1261 if (pool->base.hw_i2cs[i] == NULL) { 1262 BREAK_TO_DEBUGGER(); 1263 dm_error( 1264 "DC:failed to create i2c engine!!\n"); 1265 goto res_create_fail; 1266 } 1267 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1268 if (pool->base.sw_i2cs[i] == NULL) { 1269 BREAK_TO_DEBUGGER(); 1270 dm_error( 1271 "DC:failed to create sw i2c!!\n"); 1272 goto res_create_fail; 1273 } 1274 } 1275 1276 dc->caps.max_planes = pool->base.pipe_count; 1277 1278 for (i = 0; i < dc->caps.max_planes; ++i) 1279 dc->caps.planes[i] = plane_cap; 1280 1281 dc->caps.disable_dp_clk_share = true; 1282 1283 if (!resource_construct(num_virtual_links, dc, &pool->base, 1284 &res_create_funcs)) 1285 goto res_create_fail; 1286 1287 /* Create hardware sequencer */ 1288 dce80_hw_sequencer_construct(dc); 1289 1290 return true; 1291 1292 res_create_fail: 1293 dce80_resource_destruct(pool); 1294 return false; 1295 } 1296 1297 struct resource_pool *dce81_create_resource_pool( 1298 uint8_t num_virtual_links, 1299 struct dc *dc) 1300 { 1301 struct dce110_resource_pool *pool = 1302 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1303 1304 if (!pool) 1305 return NULL; 1306 1307 if (dce81_construct(num_virtual_links, dc, pool)) 1308 return &pool->base; 1309 1310 BREAK_TO_DEBUGGER(); 1311 return NULL; 1312 } 1313 1314 static bool dce83_construct( 1315 uint8_t num_virtual_links, 1316 struct dc *dc, 1317 struct dce110_resource_pool *pool) 1318 { 1319 unsigned int i; 1320 struct dc_context *ctx = dc->ctx; 1321 struct dc_bios *bp; 1322 1323 ctx->dc_bios->regs = &bios_regs; 1324 1325 pool->base.res_cap = &res_cap_83; 1326 pool->base.funcs = &dce80_res_pool_funcs; 1327 1328 1329 /************************************************* 1330 * Resource + asic cap harcoding * 1331 *************************************************/ 1332 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1333 pool->base.pipe_count = res_cap_83.num_timing_generator; 1334 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1335 dc->caps.max_downscale_ratio = 200; 1336 dc->caps.i2c_speed_in_khz = 40; 1337 dc->caps.max_cursor_size = 128; 1338 dc->caps.is_apu = true; 1339 1340 /************************************************* 1341 * Create resources * 1342 *************************************************/ 1343 1344 bp = ctx->dc_bios; 1345 1346 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { 1347 pool->base.dp_clock_source = 1348 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1349 1350 pool->base.clock_sources[0] = 1351 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1352 pool->base.clock_sources[1] = 1353 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1354 pool->base.clk_src_count = 2; 1355 1356 } else { 1357 pool->base.dp_clock_source = 1358 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1359 1360 pool->base.clock_sources[0] = 1361 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1362 pool->base.clk_src_count = 1; 1363 } 1364 1365 if (pool->base.dp_clock_source == NULL) { 1366 dm_error("DC: failed to create dp clock source!\n"); 1367 BREAK_TO_DEBUGGER(); 1368 goto res_create_fail; 1369 } 1370 1371 for (i = 0; i < pool->base.clk_src_count; i++) { 1372 if (pool->base.clock_sources[i] == NULL) { 1373 dm_error("DC: failed to create clock sources!\n"); 1374 BREAK_TO_DEBUGGER(); 1375 goto res_create_fail; 1376 } 1377 } 1378 1379 pool->base.dmcu = dce_dmcu_create(ctx, 1380 &dmcu_regs, 1381 &dmcu_shift, 1382 &dmcu_mask); 1383 if (pool->base.dmcu == NULL) { 1384 dm_error("DC: failed to create dmcu!\n"); 1385 BREAK_TO_DEBUGGER(); 1386 goto res_create_fail; 1387 } 1388 1389 pool->base.abm = dce_abm_create(ctx, 1390 &abm_regs, 1391 &abm_shift, 1392 &abm_mask); 1393 if (pool->base.abm == NULL) { 1394 dm_error("DC: failed to create abm!\n"); 1395 BREAK_TO_DEBUGGER(); 1396 goto res_create_fail; 1397 } 1398 1399 { 1400 struct irq_service_init_data init_data; 1401 init_data.ctx = dc->ctx; 1402 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1403 if (!pool->base.irqs) 1404 goto res_create_fail; 1405 } 1406 1407 for (i = 0; i < pool->base.pipe_count; i++) { 1408 pool->base.timing_generators[i] = dce80_timing_generator_create( 1409 ctx, i, &dce80_tg_offsets[i]); 1410 if (pool->base.timing_generators[i] == NULL) { 1411 BREAK_TO_DEBUGGER(); 1412 dm_error("DC: failed to create tg!\n"); 1413 goto res_create_fail; 1414 } 1415 1416 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1417 if (pool->base.mis[i] == NULL) { 1418 BREAK_TO_DEBUGGER(); 1419 dm_error("DC: failed to create memory input!\n"); 1420 goto res_create_fail; 1421 } 1422 1423 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1424 if (pool->base.ipps[i] == NULL) { 1425 BREAK_TO_DEBUGGER(); 1426 dm_error("DC: failed to create input pixel processor!\n"); 1427 goto res_create_fail; 1428 } 1429 1430 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1431 if (pool->base.transforms[i] == NULL) { 1432 BREAK_TO_DEBUGGER(); 1433 dm_error("DC: failed to create transform!\n"); 1434 goto res_create_fail; 1435 } 1436 1437 pool->base.opps[i] = dce80_opp_create(ctx, i); 1438 if (pool->base.opps[i] == NULL) { 1439 BREAK_TO_DEBUGGER(); 1440 dm_error("DC: failed to create output pixel processor!\n"); 1441 goto res_create_fail; 1442 } 1443 } 1444 1445 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1446 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 1447 if (pool->base.engines[i] == NULL) { 1448 BREAK_TO_DEBUGGER(); 1449 dm_error( 1450 "DC:failed to create aux engine!!\n"); 1451 goto res_create_fail; 1452 } 1453 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i); 1454 if (pool->base.hw_i2cs[i] == NULL) { 1455 BREAK_TO_DEBUGGER(); 1456 dm_error( 1457 "DC:failed to create i2c engine!!\n"); 1458 goto res_create_fail; 1459 } 1460 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx); 1461 if (pool->base.sw_i2cs[i] == NULL) { 1462 BREAK_TO_DEBUGGER(); 1463 dm_error( 1464 "DC:failed to create sw i2c!!\n"); 1465 goto res_create_fail; 1466 } 1467 } 1468 1469 dc->caps.max_planes = pool->base.pipe_count; 1470 1471 for (i = 0; i < dc->caps.max_planes; ++i) 1472 dc->caps.planes[i] = plane_cap; 1473 1474 dc->caps.disable_dp_clk_share = true; 1475 1476 if (!resource_construct(num_virtual_links, dc, &pool->base, 1477 &res_create_funcs)) 1478 goto res_create_fail; 1479 1480 /* Create hardware sequencer */ 1481 dce80_hw_sequencer_construct(dc); 1482 1483 return true; 1484 1485 res_create_fail: 1486 dce80_resource_destruct(pool); 1487 return false; 1488 } 1489 1490 struct resource_pool *dce83_create_resource_pool( 1491 uint8_t num_virtual_links, 1492 struct dc *dc) 1493 { 1494 struct dce110_resource_pool *pool = 1495 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1496 1497 if (!pool) 1498 return NULL; 1499 1500 if (dce83_construct(num_virtual_links, dc, pool)) 1501 return &pool->base; 1502 1503 BREAK_TO_DEBUGGER(); 1504 return NULL; 1505 } 1506