1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sram/sram.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Generic on-chip SRAM
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  Simple IO memory regions to be managed by the genalloc API.
14
15  Each child of the sram node specifies a region of reserved memory. Each
16  child node should use a 'reg' property to specify a specific range of
17  reserved memory.
18
19  Following the generic-names recommended practice, node names should
20  reflect the purpose of the node. Unit address (@<address>) should be
21  appended to the name.
22
23properties:
24  $nodename:
25    pattern: "^sram(@.*)?"
26
27  compatible:
28    contains:
29      enum:
30        - mmio-sram
31        - atmel,sama5d2-securam
32        - rockchip,rk3288-pmu-sram
33
34  reg:
35    maxItems: 1
36
37  clocks:
38    description:
39      A list of phandle and clock specifier pair that controls the single
40      SRAM clock.
41
42  "#address-cells":
43    const: 1
44
45  "#size-cells":
46    const: 1
47
48  ranges:
49    description:
50      Should translate from local addresses within the sram to bus addresses.
51
52  no-memory-wc:
53    description:
54      The flag indicating, that SRAM memory region has not to be remapped
55      as write combining. WC is used by default.
56    type: boolean
57
58patternProperties:
59  "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
60    type: object
61    description:
62      Each child of the sram node specifies a region of reserved memory.
63    properties:
64      compatible:
65        description:
66          Should contain a vendor specific string in the form
67          <vendor>,[<device>-]<usage>
68        contains:
69          enum:
70            - allwinner,sun4i-a10-sram-a3-a4
71            - allwinner,sun4i-a10-sram-c1
72            - allwinner,sun4i-a10-sram-d
73            - allwinner,sun9i-a80-smp-sram
74            - allwinner,sun50i-a64-sram-c
75            - amlogic,meson8-smp-sram
76            - amlogic,meson8b-smp-sram
77            - amlogic,meson-gxbb-scp-shmem
78            - amlogic,meson-axg-scp-shmem
79            - renesas,smp-sram
80            - rockchip,rk3066-smp-sram
81            - samsung,exynos4210-sysram
82            - samsung,exynos4210-sysram-ns
83            - socionext,milbeaut-smp-sram
84
85      reg:
86        description:
87          IO mem address range, relative to the SRAM range.
88        maxItems: 1
89
90      pool:
91        description:
92          Indicates that the particular reserved SRAM area is addressable
93          and in use by another device or devices.
94        type: boolean
95
96      export:
97        description:
98          Indicates that the reserved SRAM area may be accessed outside
99          of the kernel, e.g. by bootloader or userspace.
100        type: boolean
101
102      protect-exec:
103        description: |
104          Same as 'pool' above but with the additional constraint that code
105          will be run from the region and that the memory is maintained as
106          read-only, executable during code execution. NOTE: This region must
107          be page aligned on start and end in order to properly allow
108          manipulation of the page attributes.
109        type: boolean
110
111      label:
112        description:
113          The name for the reserved partition, if omitted, the label is taken
114          from the node name excluding the unit address.
115
116    required:
117      - reg
118
119    additionalProperties: false
120
121required:
122  - compatible
123  - reg
124
125if:
126  properties:
127    compatible:
128      contains:
129        const: rockchip,rk3288-pmu-sram
130
131else:
132  required:
133    - "#address-cells"
134    - "#size-cells"
135    - ranges
136
137additionalProperties: false
138
139examples:
140  - |
141    sram@5c000000 {
142        compatible = "mmio-sram";
143        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
144
145        #address-cells = <1>;
146        #size-cells = <1>;
147        ranges = <0 0x5c000000 0x40000>;
148
149        smp-sram@100 {
150            reg = <0x100 0x50>;
151        };
152
153        device-sram@1000 {
154            reg = <0x1000 0x1000>;
155            pool;
156        };
157
158        exported-sram@20000 {
159            reg = <0x20000 0x20000>;
160            export;
161        };
162    };
163
164  - |
165    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
166    // of the secondary cores. Once the core gets powered up it executes the
167    // code that is residing at some specific location of the SYSRAM.
168    //
169    // Therefore reserved section sub-nodes have to be added to the mmio-sram
170    // declaration. These nodes are of two types depending upon secure or
171    // non-secure execution environment.
172    sram@2020000 {
173        compatible = "mmio-sram";
174        reg = <0x02020000 0x54000>;
175        #address-cells = <1>;
176        #size-cells = <1>;
177        ranges = <0 0x02020000 0x54000>;
178
179        smp-sram@0 {
180            compatible = "samsung,exynos4210-sysram";
181            reg = <0x0 0x1000>;
182        };
183
184        smp-sram@53000 {
185            compatible = "samsung,exynos4210-sysram-ns";
186            reg = <0x53000 0x1000>;
187        };
188    };
189
190  - |
191    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
192    // Once the core gets powered up it executes the code that is residing at a
193    // specific location.
194    //
195    // Therefore a reserved section sub-node has to be added to the mmio-sram
196    // declaration.
197    sram@d9000000 {
198        compatible = "mmio-sram";
199        reg = <0xd9000000 0x20000>;
200        #address-cells = <1>;
201        #size-cells = <1>;
202        ranges = <0 0xd9000000 0x20000>;
203
204        smp-sram@1ff80 {
205            compatible = "amlogic,meson8b-smp-sram";
206            reg = <0x1ff80 0x8>;
207        };
208    };
209
210  - |
211    sram@e63c0000 {
212        compatible = "mmio-sram";
213        reg = <0xe63c0000 0x1000>;
214        #address-cells = <1>;
215        #size-cells = <1>;
216        ranges = <0 0xe63c0000 0x1000>;
217
218        smp-sram@0 {
219            compatible = "renesas,smp-sram";
220            reg = <0 0x10>;
221        };
222    };
223
224  - |
225    sram@10080000 {
226        compatible = "mmio-sram";
227        reg = <0x10080000 0x10000>;
228        #address-cells = <1>;
229        #size-cells = <1>;
230        ranges;
231
232        smp-sram@10080000 {
233            compatible = "rockchip,rk3066-smp-sram";
234            reg = <0x10080000 0x50>;
235        };
236    };
237
238  - |
239    // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
240    // resume from maskrom(the 1st level loader). This is a common use of
241    // the "pmu-sram" because it keeps power even in low power states
242    // in the system.
243    sram@ff720000 {
244      compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
245      reg = <0xff720000 0x1000>;
246    };
247
248  - |
249    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
250    // primary core (cpu0). Once the core gets powered up it checks if a magic
251    // value is set at a specific location. If it is then the BROM will jump
252    // to the software entry address, instead of executing a standard boot.
253    //
254    // Also there are no "secure-only" properties. The implementation should
255    // check if this SRAM is usable first.
256    sram@20000 {
257        // 256 KiB secure SRAM at 0x20000
258        compatible = "mmio-sram";
259        reg = <0x00020000 0x40000>;
260        #address-cells = <1>;
261        #size-cells = <1>;
262        ranges = <0 0x00020000 0x40000>;
263
264        smp-sram@1000 {
265            // This is checked by BROM to determine if
266            // cpu0 should jump to SMP entry vector
267            compatible = "allwinner,sun9i-a80-smp-sram";
268            reg = <0x1000 0x8>;
269        };
270    };
271
272  - |
273    sram@0 {
274        compatible = "mmio-sram";
275        reg = <0x0 0x10000>;
276        #address-cells = <1>;
277        #size-cells = <1>;
278        ranges = <0 0x0 0x10000>;
279
280        smp-sram@f100 {
281            compatible = "socionext,milbeaut-smp-sram";
282            reg = <0xf100 0x20>;
283        };
284    };
285