1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <linux/clk.h> 38 #include <linux/component.h> 39 #include <linux/i2c.h> 40 #include <linux/of_address.h> 41 #include <linux/of_gpio.h> 42 #include <linux/of_platform.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/rational.h> 45 #include <sound/dmaengine_pcm.h> 46 #include <sound/pcm_drm_eld.h> 47 #include <sound/pcm_params.h> 48 #include <sound/soc.h> 49 #include "media/cec.h" 50 #include "vc4_drv.h" 51 #include "vc4_regs.h" 52 53 #define HSM_CLOCK_FREQ 163682864 54 #define CEC_CLOCK_FREQ 40000 55 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) 56 57 /* HDMI audio information */ 58 struct vc4_hdmi_audio { 59 struct snd_soc_card card; 60 struct snd_soc_dai_link link; 61 struct snd_soc_dai_link_component cpu; 62 struct snd_soc_dai_link_component codec; 63 struct snd_soc_dai_link_component platform; 64 int samplerate; 65 int channels; 66 struct snd_dmaengine_dai_dma_data dma_data; 67 struct snd_pcm_substream *substream; 68 }; 69 70 /* General HDMI hardware state. */ 71 struct vc4_hdmi { 72 struct platform_device *pdev; 73 74 struct drm_encoder *encoder; 75 struct drm_connector *connector; 76 77 struct vc4_hdmi_audio audio; 78 79 struct i2c_adapter *ddc; 80 void __iomem *hdmicore_regs; 81 void __iomem *hd_regs; 82 int hpd_gpio; 83 bool hpd_active_low; 84 85 struct cec_adapter *cec_adap; 86 struct cec_msg cec_rx_msg; 87 bool cec_tx_ok; 88 bool cec_irq_was_rx; 89 90 struct clk *pixel_clock; 91 struct clk *hsm_clock; 92 93 struct debugfs_regset32 hdmi_regset; 94 struct debugfs_regset32 hd_regset; 95 }; 96 97 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 98 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 99 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 100 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 101 102 /* VC4 HDMI encoder KMS struct */ 103 struct vc4_hdmi_encoder { 104 struct vc4_encoder base; 105 bool hdmi_monitor; 106 bool limited_rgb_range; 107 }; 108 109 static inline struct vc4_hdmi_encoder * 110 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 111 { 112 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 113 } 114 115 /* VC4 HDMI connector KMS struct */ 116 struct vc4_hdmi_connector { 117 struct drm_connector base; 118 119 /* Since the connector is attached to just the one encoder, 120 * this is the reference to it so we can do the best_encoder() 121 * hook. 122 */ 123 struct drm_encoder *encoder; 124 }; 125 126 static inline struct vc4_hdmi_connector * 127 to_vc4_hdmi_connector(struct drm_connector *connector) 128 { 129 return container_of(connector, struct vc4_hdmi_connector, base); 130 } 131 132 static const struct debugfs_reg32 hdmi_regs[] = { 133 VC4_REG32(VC4_HDMI_CORE_REV), 134 VC4_REG32(VC4_HDMI_SW_RESET_CONTROL), 135 VC4_REG32(VC4_HDMI_HOTPLUG_INT), 136 VC4_REG32(VC4_HDMI_HOTPLUG), 137 VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP), 138 VC4_REG32(VC4_HDMI_MAI_CONFIG), 139 VC4_REG32(VC4_HDMI_MAI_FORMAT), 140 VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG), 141 VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG), 142 VC4_REG32(VC4_HDMI_HORZA), 143 VC4_REG32(VC4_HDMI_HORZB), 144 VC4_REG32(VC4_HDMI_FIFO_CTL), 145 VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL), 146 VC4_REG32(VC4_HDMI_VERTA0), 147 VC4_REG32(VC4_HDMI_VERTA1), 148 VC4_REG32(VC4_HDMI_VERTB0), 149 VC4_REG32(VC4_HDMI_VERTB1), 150 VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL), 151 VC4_REG32(VC4_HDMI_TX_PHY_CTL0), 152 153 VC4_REG32(VC4_HDMI_CEC_CNTRL_1), 154 VC4_REG32(VC4_HDMI_CEC_CNTRL_2), 155 VC4_REG32(VC4_HDMI_CEC_CNTRL_3), 156 VC4_REG32(VC4_HDMI_CEC_CNTRL_4), 157 VC4_REG32(VC4_HDMI_CEC_CNTRL_5), 158 VC4_REG32(VC4_HDMI_CPU_STATUS), 159 VC4_REG32(VC4_HDMI_CPU_MASK_STATUS), 160 161 VC4_REG32(VC4_HDMI_CEC_RX_DATA_1), 162 VC4_REG32(VC4_HDMI_CEC_RX_DATA_2), 163 VC4_REG32(VC4_HDMI_CEC_RX_DATA_3), 164 VC4_REG32(VC4_HDMI_CEC_RX_DATA_4), 165 VC4_REG32(VC4_HDMI_CEC_TX_DATA_1), 166 VC4_REG32(VC4_HDMI_CEC_TX_DATA_2), 167 VC4_REG32(VC4_HDMI_CEC_TX_DATA_3), 168 VC4_REG32(VC4_HDMI_CEC_TX_DATA_4), 169 }; 170 171 static const struct debugfs_reg32 hd_regs[] = { 172 VC4_REG32(VC4_HD_M_CTL), 173 VC4_REG32(VC4_HD_MAI_CTL), 174 VC4_REG32(VC4_HD_MAI_THR), 175 VC4_REG32(VC4_HD_MAI_FMT), 176 VC4_REG32(VC4_HD_MAI_SMP), 177 VC4_REG32(VC4_HD_VID_CTL), 178 VC4_REG32(VC4_HD_CSC_CTL), 179 VC4_REG32(VC4_HD_FRAME_COUNT), 180 }; 181 182 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 183 { 184 struct drm_info_node *node = (struct drm_info_node *)m->private; 185 struct drm_device *dev = node->minor->dev; 186 struct vc4_dev *vc4 = to_vc4_dev(dev); 187 struct vc4_hdmi *hdmi = vc4->hdmi; 188 struct drm_printer p = drm_seq_file_printer(m); 189 190 drm_print_regset32(&p, &hdmi->hdmi_regset); 191 drm_print_regset32(&p, &hdmi->hd_regset); 192 193 return 0; 194 } 195 196 static enum drm_connector_status 197 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 198 { 199 struct drm_device *dev = connector->dev; 200 struct vc4_dev *vc4 = to_vc4_dev(dev); 201 202 if (vc4->hdmi->hpd_gpio) { 203 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 204 vc4->hdmi->hpd_active_low) 205 return connector_status_connected; 206 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 207 return connector_status_disconnected; 208 } 209 210 if (drm_probe_ddc(vc4->hdmi->ddc)) 211 return connector_status_connected; 212 213 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 214 return connector_status_connected; 215 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 216 return connector_status_disconnected; 217 } 218 219 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 220 { 221 drm_connector_unregister(connector); 222 drm_connector_cleanup(connector); 223 } 224 225 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 226 { 227 struct vc4_hdmi_connector *vc4_connector = 228 to_vc4_hdmi_connector(connector); 229 struct drm_encoder *encoder = vc4_connector->encoder; 230 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 231 struct drm_device *dev = connector->dev; 232 struct vc4_dev *vc4 = to_vc4_dev(dev); 233 int ret = 0; 234 struct edid *edid; 235 236 edid = drm_get_edid(connector, vc4->hdmi->ddc); 237 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid); 238 if (!edid) 239 return -ENODEV; 240 241 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 242 243 drm_connector_update_edid_property(connector, edid); 244 ret = drm_add_edid_modes(connector, edid); 245 kfree(edid); 246 247 return ret; 248 } 249 250 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 251 { 252 drm_atomic_helper_connector_reset(connector); 253 drm_atomic_helper_connector_tv_reset(connector); 254 } 255 256 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 257 .detect = vc4_hdmi_connector_detect, 258 .fill_modes = drm_helper_probe_single_connector_modes, 259 .destroy = vc4_hdmi_connector_destroy, 260 .reset = vc4_hdmi_connector_reset, 261 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 262 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 263 }; 264 265 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 266 .get_modes = vc4_hdmi_connector_get_modes, 267 }; 268 269 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 270 struct drm_encoder *encoder, 271 struct i2c_adapter *ddc) 272 { 273 struct drm_connector *connector; 274 struct vc4_hdmi_connector *hdmi_connector; 275 int ret; 276 277 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 278 GFP_KERNEL); 279 if (!hdmi_connector) 280 return ERR_PTR(-ENOMEM); 281 connector = &hdmi_connector->base; 282 283 hdmi_connector->encoder = encoder; 284 285 drm_connector_init_with_ddc(dev, connector, 286 &vc4_hdmi_connector_funcs, 287 DRM_MODE_CONNECTOR_HDMIA, 288 ddc); 289 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 290 291 /* Create and attach TV margin props to this connector. */ 292 ret = drm_mode_create_tv_margin_properties(dev); 293 if (ret) 294 return ERR_PTR(ret); 295 296 drm_connector_attach_tv_margin_properties(connector); 297 298 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 299 DRM_CONNECTOR_POLL_DISCONNECT); 300 301 connector->interlace_allowed = 1; 302 connector->doublescan_allowed = 0; 303 304 drm_connector_attach_encoder(connector, encoder); 305 306 return connector; 307 } 308 309 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 310 { 311 drm_encoder_cleanup(encoder); 312 } 313 314 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 315 .destroy = vc4_hdmi_encoder_destroy, 316 }; 317 318 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 319 enum hdmi_infoframe_type type) 320 { 321 struct drm_device *dev = encoder->dev; 322 struct vc4_dev *vc4 = to_vc4_dev(dev); 323 u32 packet_id = type - 0x80; 324 325 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 326 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 327 328 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 329 BIT(packet_id)), 100); 330 } 331 332 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 333 union hdmi_infoframe *frame) 334 { 335 struct drm_device *dev = encoder->dev; 336 struct vc4_dev *vc4 = to_vc4_dev(dev); 337 u32 packet_id = frame->any.type - 0x80; 338 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 339 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 340 ssize_t len, i; 341 int ret; 342 343 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 344 VC4_HDMI_RAM_PACKET_ENABLE), 345 "Packet RAM has to be on to store the packet."); 346 347 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 348 if (len < 0) 349 return; 350 351 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 352 if (ret) { 353 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 354 return; 355 } 356 357 for (i = 0; i < len; i += 7) { 358 HDMI_WRITE(packet_reg, 359 buffer[i + 0] << 0 | 360 buffer[i + 1] << 8 | 361 buffer[i + 2] << 16); 362 packet_reg += 4; 363 364 HDMI_WRITE(packet_reg, 365 buffer[i + 3] << 0 | 366 buffer[i + 4] << 8 | 367 buffer[i + 5] << 16 | 368 buffer[i + 6] << 24); 369 packet_reg += 4; 370 } 371 372 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 373 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 374 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 375 BIT(packet_id)), 100); 376 if (ret) 377 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 378 } 379 380 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 381 { 382 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 383 struct vc4_dev *vc4 = encoder->dev->dev_private; 384 struct vc4_hdmi *hdmi = vc4->hdmi; 385 struct drm_connector_state *cstate = hdmi->connector->state; 386 struct drm_crtc *crtc = encoder->crtc; 387 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 388 union hdmi_infoframe frame; 389 int ret; 390 391 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 392 hdmi->connector, mode); 393 if (ret < 0) { 394 DRM_ERROR("couldn't fill AVI infoframe\n"); 395 return; 396 } 397 398 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 399 hdmi->connector, mode, 400 vc4_encoder->limited_rgb_range ? 401 HDMI_QUANTIZATION_RANGE_LIMITED : 402 HDMI_QUANTIZATION_RANGE_FULL); 403 404 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 405 406 vc4_hdmi_write_infoframe(encoder, &frame); 407 } 408 409 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 410 { 411 union hdmi_infoframe frame; 412 int ret; 413 414 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 415 if (ret < 0) { 416 DRM_ERROR("couldn't fill SPD infoframe\n"); 417 return; 418 } 419 420 frame.spd.sdi = HDMI_SPD_SDI_PC; 421 422 vc4_hdmi_write_infoframe(encoder, &frame); 423 } 424 425 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 426 { 427 struct drm_device *drm = encoder->dev; 428 struct vc4_dev *vc4 = drm->dev_private; 429 struct vc4_hdmi *hdmi = vc4->hdmi; 430 union hdmi_infoframe frame; 431 int ret; 432 433 ret = hdmi_audio_infoframe_init(&frame.audio); 434 435 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 436 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 437 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 438 frame.audio.channels = hdmi->audio.channels; 439 440 vc4_hdmi_write_infoframe(encoder, &frame); 441 } 442 443 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 444 { 445 vc4_hdmi_set_avi_infoframe(encoder); 446 vc4_hdmi_set_spd_infoframe(encoder); 447 } 448 449 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 450 { 451 struct drm_device *dev = encoder->dev; 452 struct vc4_dev *vc4 = to_vc4_dev(dev); 453 struct vc4_hdmi *hdmi = vc4->hdmi; 454 int ret; 455 456 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 457 458 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 459 HD_WRITE(VC4_HD_VID_CTL, 460 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 461 462 clk_disable_unprepare(hdmi->pixel_clock); 463 464 ret = pm_runtime_put(&hdmi->pdev->dev); 465 if (ret < 0) 466 DRM_ERROR("Failed to release power domain: %d\n", ret); 467 } 468 469 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 470 { 471 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 472 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 473 struct drm_device *dev = encoder->dev; 474 struct vc4_dev *vc4 = to_vc4_dev(dev); 475 struct vc4_hdmi *hdmi = vc4->hdmi; 476 bool debug_dump_regs = false; 477 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 478 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 479 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 480 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 481 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 482 VC4_HDMI_VERTA_VSP) | 483 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 484 VC4_HDMI_VERTA_VFP) | 485 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 486 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 487 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 488 VC4_HDMI_VERTB_VBP)); 489 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 490 VC4_SET_FIELD(mode->crtc_vtotal - 491 mode->crtc_vsync_end - 492 interlaced, 493 VC4_HDMI_VERTB_VBP)); 494 u32 csc_ctl; 495 int ret; 496 497 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 498 if (ret < 0) { 499 DRM_ERROR("Failed to retain power domain: %d\n", ret); 500 return; 501 } 502 503 ret = clk_set_rate(hdmi->pixel_clock, 504 mode->clock * 1000 * 505 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 506 if (ret) { 507 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 508 return; 509 } 510 511 ret = clk_prepare_enable(hdmi->pixel_clock); 512 if (ret) { 513 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 514 return; 515 } 516 517 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 518 VC4_HDMI_SW_RESET_HDMI | 519 VC4_HDMI_SW_RESET_FORMAT_DETECT); 520 521 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 522 523 /* PHY should be in reset, like 524 * vc4_hdmi_encoder_disable() does. 525 */ 526 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 527 528 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 529 530 if (debug_dump_regs) { 531 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 532 533 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n"); 534 drm_print_regset32(&p, &hdmi->hdmi_regset); 535 drm_print_regset32(&p, &hdmi->hd_regset); 536 } 537 538 HD_WRITE(VC4_HD_VID_CTL, 0); 539 540 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 541 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 542 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 543 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 544 545 HDMI_WRITE(VC4_HDMI_HORZA, 546 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 547 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 548 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 549 VC4_HDMI_HORZA_HAP)); 550 551 HDMI_WRITE(VC4_HDMI_HORZB, 552 VC4_SET_FIELD((mode->htotal - 553 mode->hsync_end) * pixel_rep, 554 VC4_HDMI_HORZB_HBP) | 555 VC4_SET_FIELD((mode->hsync_end - 556 mode->hsync_start) * pixel_rep, 557 VC4_HDMI_HORZB_HSP) | 558 VC4_SET_FIELD((mode->hsync_start - 559 mode->hdisplay) * pixel_rep, 560 VC4_HDMI_HORZB_HFP)); 561 562 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 563 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 564 565 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 566 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 567 568 HD_WRITE(VC4_HD_VID_CTL, 569 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 570 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 571 572 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 573 VC4_HD_CSC_CTL_ORDER); 574 575 if (vc4_encoder->hdmi_monitor && 576 drm_default_rgb_quant_range(mode) == 577 HDMI_QUANTIZATION_RANGE_LIMITED) { 578 /* CEA VICs other than #1 requre limited range RGB 579 * output unless overridden by an AVI infoframe. 580 * Apply a colorspace conversion to squash 0-255 down 581 * to 16-235. The matrix here is: 582 * 583 * [ 0 0 0.8594 16] 584 * [ 0 0.8594 0 16] 585 * [ 0.8594 0 0 16] 586 * [ 0 0 0 1] 587 */ 588 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 589 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 590 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 591 VC4_HD_CSC_CTL_MODE); 592 593 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 594 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 595 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 596 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 597 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 598 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 599 vc4_encoder->limited_rgb_range = true; 600 } else { 601 vc4_encoder->limited_rgb_range = false; 602 } 603 604 /* The RGB order applies even when CSC is disabled. */ 605 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 606 607 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 608 609 if (debug_dump_regs) { 610 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 611 612 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n"); 613 drm_print_regset32(&p, &hdmi->hdmi_regset); 614 drm_print_regset32(&p, &hdmi->hd_regset); 615 } 616 617 HD_WRITE(VC4_HD_VID_CTL, 618 HD_READ(VC4_HD_VID_CTL) | 619 VC4_HD_VID_CTL_ENABLE | 620 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 621 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 622 623 if (vc4_encoder->hdmi_monitor) { 624 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 625 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 626 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 627 628 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 629 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 630 WARN_ONCE(ret, "Timeout waiting for " 631 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 632 } else { 633 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 634 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 635 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 636 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 637 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 638 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 639 640 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 641 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 642 WARN_ONCE(ret, "Timeout waiting for " 643 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 644 } 645 646 if (vc4_encoder->hdmi_monitor) { 647 u32 drift; 648 649 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 650 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 651 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 652 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 653 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 654 655 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 656 VC4_HDMI_RAM_PACKET_ENABLE); 657 658 vc4_hdmi_set_infoframes(encoder); 659 660 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 661 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 662 663 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 664 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 665 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 666 drift | VC4_HDMI_FIFO_CTL_RECENTER); 667 usleep_range(1000, 1100); 668 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 669 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 670 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 671 drift | VC4_HDMI_FIFO_CTL_RECENTER); 672 673 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 674 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 675 WARN_ONCE(ret, "Timeout waiting for " 676 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 677 } 678 } 679 680 static enum drm_mode_status 681 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc, 682 const struct drm_display_mode *mode) 683 { 684 /* HSM clock must be 108% of the pixel clock. Additionally, 685 * the AXI clock needs to be at least 25% of pixel clock, but 686 * HSM ends up being the limiting factor. 687 */ 688 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100)) 689 return MODE_CLOCK_HIGH; 690 691 return MODE_OK; 692 } 693 694 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 695 .mode_valid = vc4_hdmi_encoder_mode_valid, 696 .disable = vc4_hdmi_encoder_disable, 697 .enable = vc4_hdmi_encoder_enable, 698 }; 699 700 /* HDMI audio codec callbacks */ 701 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 702 { 703 struct drm_device *drm = hdmi->encoder->dev; 704 struct vc4_dev *vc4 = to_vc4_dev(drm); 705 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 706 unsigned long n, m; 707 708 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 709 VC4_HD_MAI_SMP_N_MASK >> 710 VC4_HD_MAI_SMP_N_SHIFT, 711 (VC4_HD_MAI_SMP_M_MASK >> 712 VC4_HD_MAI_SMP_M_SHIFT) + 1, 713 &n, &m); 714 715 HD_WRITE(VC4_HD_MAI_SMP, 716 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 717 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 718 } 719 720 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 721 { 722 struct drm_encoder *encoder = hdmi->encoder; 723 struct drm_crtc *crtc = encoder->crtc; 724 struct drm_device *drm = encoder->dev; 725 struct vc4_dev *vc4 = to_vc4_dev(drm); 726 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 727 u32 samplerate = hdmi->audio.samplerate; 728 u32 n, cts; 729 u64 tmp; 730 731 n = 128 * samplerate / 1000; 732 tmp = (u64)(mode->clock * 1000) * n; 733 do_div(tmp, 128 * samplerate); 734 cts = tmp; 735 736 HDMI_WRITE(VC4_HDMI_CRP_CFG, 737 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 738 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 739 740 /* 741 * We could get slightly more accurate clocks in some cases by 742 * providing a CTS_1 value. The two CTS values are alternated 743 * between based on the period fields 744 */ 745 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 746 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 747 } 748 749 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 750 { 751 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 752 753 return snd_soc_card_get_drvdata(card); 754 } 755 756 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 757 struct snd_soc_dai *dai) 758 { 759 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 760 struct drm_encoder *encoder = hdmi->encoder; 761 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 762 int ret; 763 764 if (hdmi->audio.substream && hdmi->audio.substream != substream) 765 return -EINVAL; 766 767 hdmi->audio.substream = substream; 768 769 /* 770 * If the HDMI encoder hasn't probed, or the encoder is 771 * currently in DVI mode, treat the codec dai as missing. 772 */ 773 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 774 VC4_HDMI_RAM_PACKET_ENABLE)) 775 return -ENODEV; 776 777 ret = snd_pcm_hw_constraint_eld(substream->runtime, 778 hdmi->connector->eld); 779 if (ret) 780 return ret; 781 782 return 0; 783 } 784 785 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 786 { 787 return 0; 788 } 789 790 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 791 { 792 struct drm_encoder *encoder = hdmi->encoder; 793 struct drm_device *drm = encoder->dev; 794 struct device *dev = &hdmi->pdev->dev; 795 struct vc4_dev *vc4 = to_vc4_dev(drm); 796 int ret; 797 798 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 799 if (ret) 800 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 801 802 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 803 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 804 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 805 } 806 807 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 808 struct snd_soc_dai *dai) 809 { 810 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 811 812 if (substream != hdmi->audio.substream) 813 return; 814 815 vc4_hdmi_audio_reset(hdmi); 816 817 hdmi->audio.substream = NULL; 818 } 819 820 /* HDMI audio codec callbacks */ 821 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 822 struct snd_pcm_hw_params *params, 823 struct snd_soc_dai *dai) 824 { 825 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 826 struct drm_encoder *encoder = hdmi->encoder; 827 struct drm_device *drm = encoder->dev; 828 struct device *dev = &hdmi->pdev->dev; 829 struct vc4_dev *vc4 = to_vc4_dev(drm); 830 u32 audio_packet_config, channel_mask; 831 u32 channel_map, i; 832 833 if (substream != hdmi->audio.substream) 834 return -EINVAL; 835 836 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 837 params_rate(params), params_width(params), 838 params_channels(params)); 839 840 hdmi->audio.channels = params_channels(params); 841 hdmi->audio.samplerate = params_rate(params); 842 843 HD_WRITE(VC4_HD_MAI_CTL, 844 VC4_HD_MAI_CTL_RESET | 845 VC4_HD_MAI_CTL_FLUSH | 846 VC4_HD_MAI_CTL_DLATE | 847 VC4_HD_MAI_CTL_ERRORE | 848 VC4_HD_MAI_CTL_ERRORF); 849 850 vc4_hdmi_audio_set_mai_clock(hdmi); 851 852 audio_packet_config = 853 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 854 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 855 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 856 857 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 858 audio_packet_config |= VC4_SET_FIELD(channel_mask, 859 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 860 861 /* Set the MAI threshold. This logic mimics the firmware's. */ 862 if (hdmi->audio.samplerate > 96000) { 863 HD_WRITE(VC4_HD_MAI_THR, 864 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 865 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 866 } else if (hdmi->audio.samplerate > 48000) { 867 HD_WRITE(VC4_HD_MAI_THR, 868 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 869 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 870 } else { 871 HD_WRITE(VC4_HD_MAI_THR, 872 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 873 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 874 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 875 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 876 } 877 878 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 879 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 880 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 881 882 channel_map = 0; 883 for (i = 0; i < 8; i++) { 884 if (channel_mask & BIT(i)) 885 channel_map |= i << (3 * i); 886 } 887 888 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 889 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 890 vc4_hdmi_set_n_cts(hdmi); 891 892 return 0; 893 } 894 895 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 896 struct snd_soc_dai *dai) 897 { 898 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 899 struct drm_encoder *encoder = hdmi->encoder; 900 struct drm_device *drm = encoder->dev; 901 struct vc4_dev *vc4 = to_vc4_dev(drm); 902 903 switch (cmd) { 904 case SNDRV_PCM_TRIGGER_START: 905 vc4_hdmi_set_audio_infoframe(encoder); 906 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 907 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 908 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 909 HD_WRITE(VC4_HD_MAI_CTL, 910 VC4_SET_FIELD(hdmi->audio.channels, 911 VC4_HD_MAI_CTL_CHNUM) | 912 VC4_HD_MAI_CTL_ENABLE); 913 break; 914 case SNDRV_PCM_TRIGGER_STOP: 915 HD_WRITE(VC4_HD_MAI_CTL, 916 VC4_HD_MAI_CTL_DLATE | 917 VC4_HD_MAI_CTL_ERRORE | 918 VC4_HD_MAI_CTL_ERRORF); 919 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 920 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 921 VC4_HDMI_TX_PHY_RNG_PWRDN); 922 break; 923 default: 924 break; 925 } 926 927 return 0; 928 } 929 930 static inline struct vc4_hdmi * 931 snd_component_to_hdmi(struct snd_soc_component *component) 932 { 933 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 934 935 return snd_soc_card_get_drvdata(card); 936 } 937 938 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 939 struct snd_ctl_elem_info *uinfo) 940 { 941 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 942 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 943 944 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 945 uinfo->count = sizeof(hdmi->connector->eld); 946 947 return 0; 948 } 949 950 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 951 struct snd_ctl_elem_value *ucontrol) 952 { 953 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 954 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 955 956 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 957 sizeof(hdmi->connector->eld)); 958 959 return 0; 960 } 961 962 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 963 { 964 .access = SNDRV_CTL_ELEM_ACCESS_READ | 965 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 966 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 967 .name = "ELD", 968 .info = vc4_hdmi_audio_eld_ctl_info, 969 .get = vc4_hdmi_audio_eld_ctl_get, 970 }, 971 }; 972 973 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 974 SND_SOC_DAPM_OUTPUT("TX"), 975 }; 976 977 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 978 { "TX", NULL, "Playback" }, 979 }; 980 981 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 982 .controls = vc4_hdmi_audio_controls, 983 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 984 .dapm_widgets = vc4_hdmi_audio_widgets, 985 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 986 .dapm_routes = vc4_hdmi_audio_routes, 987 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 988 .idle_bias_on = 1, 989 .use_pmdown_time = 1, 990 .endianness = 1, 991 .non_legacy_dai_naming = 1, 992 }; 993 994 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 995 .startup = vc4_hdmi_audio_startup, 996 .shutdown = vc4_hdmi_audio_shutdown, 997 .hw_params = vc4_hdmi_audio_hw_params, 998 .set_fmt = vc4_hdmi_audio_set_fmt, 999 .trigger = vc4_hdmi_audio_trigger, 1000 }; 1001 1002 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1003 .name = "vc4-hdmi-hifi", 1004 .playback = { 1005 .stream_name = "Playback", 1006 .channels_min = 2, 1007 .channels_max = 8, 1008 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1009 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1010 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1011 SNDRV_PCM_RATE_192000, 1012 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1013 }, 1014 }; 1015 1016 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1017 .name = "vc4-hdmi-cpu-dai-component", 1018 }; 1019 1020 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1021 { 1022 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1023 1024 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1025 1026 return 0; 1027 } 1028 1029 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1030 .name = "vc4-hdmi-cpu-dai", 1031 .probe = vc4_hdmi_audio_cpu_dai_probe, 1032 .playback = { 1033 .stream_name = "Playback", 1034 .channels_min = 1, 1035 .channels_max = 8, 1036 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1037 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1038 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1039 SNDRV_PCM_RATE_192000, 1040 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1041 }, 1042 .ops = &vc4_hdmi_audio_dai_ops, 1043 }; 1044 1045 static const struct snd_dmaengine_pcm_config pcm_conf = { 1046 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1047 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1048 }; 1049 1050 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1051 { 1052 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1053 struct snd_soc_card *card = &hdmi->audio.card; 1054 struct device *dev = &hdmi->pdev->dev; 1055 const __be32 *addr; 1056 int ret; 1057 1058 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1059 dev_warn(dev, 1060 "'dmas' DT property is missing, no HDMI audio\n"); 1061 return 0; 1062 } 1063 1064 /* 1065 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1066 * the bus address specified in the DT, because the physical address 1067 * (the one returned by platform_get_resource()) is not appropriate 1068 * for DMA transfers. 1069 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1070 */ 1071 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1072 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1073 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1074 hdmi->audio.dma_data.maxburst = 2; 1075 1076 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1077 if (ret) { 1078 dev_err(dev, "Could not register PCM component: %d\n", ret); 1079 return ret; 1080 } 1081 1082 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1083 &vc4_hdmi_audio_cpu_dai_drv, 1); 1084 if (ret) { 1085 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1086 return ret; 1087 } 1088 1089 /* register component and codec dai */ 1090 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1091 &vc4_hdmi_audio_codec_dai_drv, 1); 1092 if (ret) { 1093 dev_err(dev, "Could not register component: %d\n", ret); 1094 return ret; 1095 } 1096 1097 dai_link->cpus = &hdmi->audio.cpu; 1098 dai_link->codecs = &hdmi->audio.codec; 1099 dai_link->platforms = &hdmi->audio.platform; 1100 1101 dai_link->num_cpus = 1; 1102 dai_link->num_codecs = 1; 1103 dai_link->num_platforms = 1; 1104 1105 dai_link->name = "MAI"; 1106 dai_link->stream_name = "MAI PCM"; 1107 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1108 dai_link->cpus->dai_name = dev_name(dev); 1109 dai_link->codecs->name = dev_name(dev); 1110 dai_link->platforms->name = dev_name(dev); 1111 1112 card->dai_link = dai_link; 1113 card->num_links = 1; 1114 card->name = "vc4-hdmi"; 1115 card->dev = dev; 1116 1117 /* 1118 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1119 * stores a pointer to the snd card object in dev->driver_data. This 1120 * means we cannot use it for something else. The hdmi back-pointer is 1121 * now stored in card->drvdata and should be retrieved with 1122 * snd_soc_card_get_drvdata() if needed. 1123 */ 1124 snd_soc_card_set_drvdata(card, hdmi); 1125 ret = devm_snd_soc_register_card(dev, card); 1126 if (ret) 1127 dev_err(dev, "Could not register sound card: %d\n", ret); 1128 1129 return ret; 1130 1131 } 1132 1133 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1134 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1135 { 1136 struct vc4_dev *vc4 = priv; 1137 struct vc4_hdmi *hdmi = vc4->hdmi; 1138 1139 if (hdmi->cec_irq_was_rx) { 1140 if (hdmi->cec_rx_msg.len) 1141 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg); 1142 } else if (hdmi->cec_tx_ok) { 1143 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK, 1144 0, 0, 0, 0); 1145 } else { 1146 /* 1147 * This CEC implementation makes 1 retry, so if we 1148 * get a NACK, then that means it made 2 attempts. 1149 */ 1150 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK, 1151 0, 2, 0, 0); 1152 } 1153 return IRQ_HANDLED; 1154 } 1155 1156 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) 1157 { 1158 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg; 1159 unsigned int i; 1160 1161 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1162 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1163 for (i = 0; i < msg->len; i += 4) { 1164 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); 1165 1166 msg->msg[i] = val & 0xff; 1167 msg->msg[i + 1] = (val >> 8) & 0xff; 1168 msg->msg[i + 2] = (val >> 16) & 0xff; 1169 msg->msg[i + 3] = (val >> 24) & 0xff; 1170 } 1171 } 1172 1173 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1174 { 1175 struct vc4_dev *vc4 = priv; 1176 struct vc4_hdmi *hdmi = vc4->hdmi; 1177 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); 1178 u32 cntrl1, cntrl5; 1179 1180 if (!(stat & VC4_HDMI_CPU_CEC)) 1181 return IRQ_NONE; 1182 hdmi->cec_rx_msg.len = 0; 1183 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1184 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1185 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1186 if (hdmi->cec_irq_was_rx) { 1187 vc4_cec_read_msg(vc4, cntrl1); 1188 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1189 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1190 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1191 } else { 1192 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1193 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1194 } 1195 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1196 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1197 1198 return IRQ_WAKE_THREAD; 1199 } 1200 1201 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1202 { 1203 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1204 /* clock period in microseconds */ 1205 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1206 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1207 1208 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1209 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1210 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1211 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1212 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1213 1214 if (enable) { 1215 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1216 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1217 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); 1218 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, 1219 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1220 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1221 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1222 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1223 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1224 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, 1225 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1226 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1227 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1228 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1229 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, 1230 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1231 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1232 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1233 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1234 1235 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1236 } else { 1237 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1238 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1239 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1240 } 1241 return 0; 1242 } 1243 1244 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1245 { 1246 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1247 1248 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, 1249 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1250 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1251 return 0; 1252 } 1253 1254 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1255 u32 signal_free_time, struct cec_msg *msg) 1256 { 1257 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1258 u32 val; 1259 unsigned int i; 1260 1261 for (i = 0; i < msg->len; i += 4) 1262 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, 1263 (msg->msg[i]) | 1264 (msg->msg[i + 1] << 8) | 1265 (msg->msg[i + 2] << 16) | 1266 (msg->msg[i + 3] << 24)); 1267 1268 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1269 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1270 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1271 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1272 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1273 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1274 1275 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1276 return 0; 1277 } 1278 1279 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1280 .adap_enable = vc4_hdmi_cec_adap_enable, 1281 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1282 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1283 }; 1284 #endif 1285 1286 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1287 { 1288 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1289 struct cec_connector_info conn_info; 1290 #endif 1291 struct platform_device *pdev = to_platform_device(dev); 1292 struct drm_device *drm = dev_get_drvdata(master); 1293 struct vc4_dev *vc4 = drm->dev_private; 1294 struct vc4_hdmi *hdmi; 1295 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1296 struct device_node *ddc_node; 1297 u32 value; 1298 int ret; 1299 1300 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1301 if (!hdmi) 1302 return -ENOMEM; 1303 1304 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1305 GFP_KERNEL); 1306 if (!vc4_hdmi_encoder) 1307 return -ENOMEM; 1308 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1309 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1310 1311 hdmi->pdev = pdev; 1312 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1313 if (IS_ERR(hdmi->hdmicore_regs)) 1314 return PTR_ERR(hdmi->hdmicore_regs); 1315 1316 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1317 if (IS_ERR(hdmi->hd_regs)) 1318 return PTR_ERR(hdmi->hd_regs); 1319 1320 hdmi->hdmi_regset.base = hdmi->hdmicore_regs; 1321 hdmi->hdmi_regset.regs = hdmi_regs; 1322 hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs); 1323 hdmi->hd_regset.base = hdmi->hd_regs; 1324 hdmi->hd_regset.regs = hd_regs; 1325 hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs); 1326 1327 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1328 if (IS_ERR(hdmi->pixel_clock)) { 1329 DRM_ERROR("Failed to get pixel clock\n"); 1330 return PTR_ERR(hdmi->pixel_clock); 1331 } 1332 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1333 if (IS_ERR(hdmi->hsm_clock)) { 1334 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1335 return PTR_ERR(hdmi->hsm_clock); 1336 } 1337 1338 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1339 if (!ddc_node) { 1340 DRM_ERROR("Failed to find ddc node in device tree\n"); 1341 return -ENODEV; 1342 } 1343 1344 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1345 of_node_put(ddc_node); 1346 if (!hdmi->ddc) { 1347 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1348 return -EPROBE_DEFER; 1349 } 1350 1351 /* This is the rate that is set by the firmware. The number 1352 * needs to be a bit higher than the pixel clock rate 1353 * (generally 148.5Mhz). 1354 */ 1355 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ); 1356 if (ret) { 1357 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1358 goto err_put_i2c; 1359 } 1360 1361 ret = clk_prepare_enable(hdmi->hsm_clock); 1362 if (ret) { 1363 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1364 ret); 1365 goto err_put_i2c; 1366 } 1367 1368 /* Only use the GPIO HPD pin if present in the DT, otherwise 1369 * we'll use the HDMI core's register. 1370 */ 1371 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1372 enum of_gpio_flags hpd_gpio_flags; 1373 1374 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1375 "hpd-gpios", 0, 1376 &hpd_gpio_flags); 1377 if (hdmi->hpd_gpio < 0) { 1378 ret = hdmi->hpd_gpio; 1379 goto err_unprepare_hsm; 1380 } 1381 1382 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1383 } 1384 1385 vc4->hdmi = hdmi; 1386 1387 /* HDMI core must be enabled. */ 1388 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1389 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1390 udelay(1); 1391 HD_WRITE(VC4_HD_M_CTL, 0); 1392 1393 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1394 } 1395 pm_runtime_enable(dev); 1396 1397 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1398 DRM_MODE_ENCODER_TMDS, NULL); 1399 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1400 1401 hdmi->connector = 1402 vc4_hdmi_connector_init(drm, hdmi->encoder, hdmi->ddc); 1403 if (IS_ERR(hdmi->connector)) { 1404 ret = PTR_ERR(hdmi->connector); 1405 goto err_destroy_encoder; 1406 } 1407 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1408 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1409 vc4, "vc4", 1410 CEC_CAP_DEFAULTS | 1411 CEC_CAP_CONNECTOR_INFO, 1); 1412 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 1413 if (ret < 0) 1414 goto err_destroy_conn; 1415 1416 cec_fill_conn_info_from_drm(&conn_info, hdmi->connector); 1417 cec_s_conn_info(hdmi->cec_adap, &conn_info); 1418 1419 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); 1420 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1421 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1422 /* 1423 * Set the logical address to Unregistered and set the clock 1424 * divider: the hsm_clock rate and this divider setting will 1425 * give a 40 kHz CEC clock. 1426 */ 1427 value |= VC4_HDMI_CEC_ADDR_MASK | 1428 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1429 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); 1430 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1431 vc4_cec_irq_handler, 1432 vc4_cec_irq_handler_thread, 0, 1433 "vc4 hdmi cec", vc4); 1434 if (ret) 1435 goto err_delete_cec_adap; 1436 ret = cec_register_adapter(hdmi->cec_adap, dev); 1437 if (ret < 0) 1438 goto err_delete_cec_adap; 1439 #endif 1440 1441 ret = vc4_hdmi_audio_init(hdmi); 1442 if (ret) 1443 goto err_destroy_encoder; 1444 1445 vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi); 1446 1447 return 0; 1448 1449 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1450 err_delete_cec_adap: 1451 cec_delete_adapter(hdmi->cec_adap); 1452 err_destroy_conn: 1453 vc4_hdmi_connector_destroy(hdmi->connector); 1454 #endif 1455 err_destroy_encoder: 1456 vc4_hdmi_encoder_destroy(hdmi->encoder); 1457 err_unprepare_hsm: 1458 clk_disable_unprepare(hdmi->hsm_clock); 1459 pm_runtime_disable(dev); 1460 err_put_i2c: 1461 put_device(&hdmi->ddc->dev); 1462 1463 return ret; 1464 } 1465 1466 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1467 void *data) 1468 { 1469 struct drm_device *drm = dev_get_drvdata(master); 1470 struct vc4_dev *vc4 = drm->dev_private; 1471 struct vc4_hdmi *hdmi = vc4->hdmi; 1472 1473 cec_unregister_adapter(hdmi->cec_adap); 1474 vc4_hdmi_connector_destroy(hdmi->connector); 1475 vc4_hdmi_encoder_destroy(hdmi->encoder); 1476 1477 clk_disable_unprepare(hdmi->hsm_clock); 1478 pm_runtime_disable(dev); 1479 1480 put_device(&hdmi->ddc->dev); 1481 1482 vc4->hdmi = NULL; 1483 } 1484 1485 static const struct component_ops vc4_hdmi_ops = { 1486 .bind = vc4_hdmi_bind, 1487 .unbind = vc4_hdmi_unbind, 1488 }; 1489 1490 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1491 { 1492 return component_add(&pdev->dev, &vc4_hdmi_ops); 1493 } 1494 1495 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1496 { 1497 component_del(&pdev->dev, &vc4_hdmi_ops); 1498 return 0; 1499 } 1500 1501 static const struct of_device_id vc4_hdmi_dt_match[] = { 1502 { .compatible = "brcm,bcm2835-hdmi" }, 1503 {} 1504 }; 1505 1506 struct platform_driver vc4_hdmi_driver = { 1507 .probe = vc4_hdmi_dev_probe, 1508 .remove = vc4_hdmi_dev_remove, 1509 .driver = { 1510 .name = "vc4_hdmi", 1511 .of_match_table = vc4_hdmi_dt_match, 1512 }, 1513 }; 1514