1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/alpha/kernel/sys_ruffian.c 4 * 5 * Copyright (C) 1995 David A Rusling 6 * Copyright (C) 1996 Jay A Estabrook 7 * Copyright (C) 1998, 1999, 2000 Richard Henderson 8 * 9 * Code supporting the RUFFIAN. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/mm.h> 15 #include <linux/sched.h> 16 #include <linux/pci.h> 17 #include <linux/ioport.h> 18 #include <linux/timex.h> 19 #include <linux/init.h> 20 21 #include <asm/ptrace.h> 22 #include <asm/dma.h> 23 #include <asm/irq.h> 24 #include <asm/mmu_context.h> 25 #include <asm/io.h> 26 #include <asm/pgtable.h> 27 #include <asm/core_cia.h> 28 #include <asm/tlbflush.h> 29 30 #include "proto.h" 31 #include "irq_impl.h" 32 #include "pci_impl.h" 33 #include "machvec_impl.h" 34 35 36 static void __init 37 ruffian_init_irq(void) 38 { 39 /* Invert 6&7 for i82371 */ 40 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); 41 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ 42 43 outb(0x11,0xA0); 44 outb(0x08,0xA1); 45 outb(0x02,0xA1); 46 outb(0x01,0xA1); 47 outb(0xFF,0xA1); 48 49 outb(0x11,0x20); 50 outb(0x00,0x21); 51 outb(0x04,0x21); 52 outb(0x01,0x21); 53 outb(0xFF,0x21); 54 55 /* Finish writing the 82C59A PIC Operation Control Words */ 56 outb(0x20,0xA0); 57 outb(0x20,0x20); 58 59 init_i8259a_irqs(); 60 61 /* Not interested in the bogus interrupts (0,3,6), 62 NMI (1), HALT (2), flash (5), or 21142 (8). */ 63 init_pyxis_irqs(0x16f0000); 64 65 common_init_isa_dma(); 66 } 67 68 #define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ) 69 70 static void __init 71 ruffian_init_rtc(void) 72 { 73 /* Ruffian does not have the RTC connected to the CPU timer 74 interrupt. Instead, it uses the PIT connected to IRQ 0. */ 75 76 /* Setup interval timer. */ 77 outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */ 78 outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */ 79 outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */ 80 81 outb(0xb6, 0x43); /* pit counter 2: speaker */ 82 outb(0x31, 0x42); 83 outb(0x13, 0x42); 84 85 if (request_irq(0, rtc_timer_interrupt, 0, "timer", NULL)) 86 pr_err("Failed to request irq 0 (timer)\n"); 87 } 88 89 static void 90 ruffian_kill_arch (int mode) 91 { 92 cia_kill_arch(mode); 93 #if 0 94 /* This only causes re-entry to ARCSBIOS */ 95 /* Perhaps this works for other PYXIS as well? */ 96 *(vuip) PYXIS_RESET = 0x0000dead; 97 mb(); 98 #endif 99 } 100 101 /* 102 * Interrupt routing: 103 * 104 * Primary bus 105 * IdSel INTA INTB INTC INTD 106 * 21052 13 - - - - 107 * SIO 14 23 - - - 108 * 21143 15 44 - - - 109 * Slot 0 17 43 42 41 40 110 * 111 * Secondary bus 112 * IdSel INTA INTB INTC INTD 113 * Slot 0 8 (18) 19 18 17 16 114 * Slot 1 9 (19) 31 30 29 28 115 * Slot 2 10 (20) 27 26 25 24 116 * Slot 3 11 (21) 39 38 37 36 117 * Slot 4 12 (22) 35 34 33 32 118 * 53c875 13 (23) 20 - - - 119 * 120 */ 121 122 static int 123 ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 124 { 125 static char irq_tab[11][5] = { 126 /*INT INTA INTB INTC INTD */ 127 {-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */ 128 {-1, -1, -1, -1, -1}, /* IdSel 14, SIO */ 129 {44, 44, 44, 44, 44}, /* IdSel 15, 21143 */ 130 {-1, -1, -1, -1, -1}, /* IdSel 16, none */ 131 {43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */ 132 /* the next 6 are actually on PCI bus 1, across the bridge */ 133 {19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */ 134 {31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */ 135 {27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */ 136 {39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */ 137 {35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */ 138 {20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */ 139 }; 140 const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5; 141 return COMMON_TABLE_LOOKUP; 142 } 143 144 static u8 145 ruffian_swizzle(struct pci_dev *dev, u8 *pinp) 146 { 147 int slot, pin = *pinp; 148 149 if (dev->bus->number == 0) { 150 slot = PCI_SLOT(dev->devfn); 151 } 152 /* Check for the built-in bridge. */ 153 else if (PCI_SLOT(dev->bus->self->devfn) == 13) { 154 slot = PCI_SLOT(dev->devfn) + 10; 155 } 156 else 157 { 158 /* Must be a card-based bridge. */ 159 do { 160 if (PCI_SLOT(dev->bus->self->devfn) == 13) { 161 slot = PCI_SLOT(dev->devfn) + 10; 162 break; 163 } 164 pin = pci_swizzle_interrupt_pin(dev, pin); 165 166 /* Move up the chain of bridges. */ 167 dev = dev->bus->self; 168 /* Slot of the next bridge. */ 169 slot = PCI_SLOT(dev->devfn); 170 } while (dev->bus->self); 171 } 172 *pinp = pin; 173 return slot; 174 } 175 176 #ifdef BUILDING_FOR_MILO 177 /* 178 * The DeskStation Ruffian motherboard firmware does not place 179 * the memory size in the PALimpure area. Therefore, we use 180 * the Bank Configuration Registers in PYXIS to obtain the size. 181 */ 182 static unsigned long __init 183 ruffian_get_bank_size(unsigned long offset) 184 { 185 unsigned long bank_addr, bank, ret = 0; 186 187 /* Valid offsets are: 0x800, 0x840 and 0x880 188 since Ruffian only uses three banks. */ 189 bank_addr = (unsigned long)PYXIS_MCR + offset; 190 bank = *(vulp)bank_addr; 191 192 /* Check BANK_ENABLE */ 193 if (bank & 0x01) { 194 static unsigned long size[] __initdata = { 195 0x40000000UL, /* 0x00, 1G */ 196 0x20000000UL, /* 0x02, 512M */ 197 0x10000000UL, /* 0x04, 256M */ 198 0x08000000UL, /* 0x06, 128M */ 199 0x04000000UL, /* 0x08, 64M */ 200 0x02000000UL, /* 0x0a, 32M */ 201 0x01000000UL, /* 0x0c, 16M */ 202 0x00800000UL, /* 0x0e, 8M */ 203 0x80000000UL, /* 0x10, 2G */ 204 }; 205 206 bank = (bank & 0x1e) >> 1; 207 if (bank < ARRAY_SIZE(size)) 208 ret = size[bank]; 209 } 210 211 return ret; 212 } 213 #endif /* BUILDING_FOR_MILO */ 214 215 /* 216 * The System Vector 217 */ 218 219 struct alpha_machine_vector ruffian_mv __initmv = { 220 .vector_name = "Ruffian", 221 DO_EV5_MMU, 222 DO_DEFAULT_RTC, 223 DO_PYXIS_IO, 224 .machine_check = cia_machine_check, 225 .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS, 226 .min_io_address = DEFAULT_IO_BASE, 227 .min_mem_address = DEFAULT_MEM_BASE, 228 .pci_dac_offset = PYXIS_DAC_OFFSET, 229 230 .nr_irqs = 48, 231 .device_interrupt = pyxis_device_interrupt, 232 233 .init_arch = pyxis_init_arch, 234 .init_irq = ruffian_init_irq, 235 .init_rtc = ruffian_init_rtc, 236 .init_pci = cia_init_pci, 237 .kill_arch = ruffian_kill_arch, 238 .pci_map_irq = ruffian_map_irq, 239 .pci_swizzle = ruffian_swizzle, 240 }; 241 ALIAS_MV(ruffian) 242