1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs3 SoC 4// 5// Copyright (C) 2017 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "socionext,uniphier-pxs3"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 core2 { 31 cpu = <&cpu2>; 32 }; 33 core3 { 34 cpu = <&cpu3>; 35 }; 36 }; 37 }; 38 39 cpu0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0 0x000>; 43 clocks = <&sys_clk 33>; 44 enable-method = "psci"; 45 operating-points-v2 = <&cluster0_opp>; 46 #cooling-cells = <2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0 0x001>; 53 clocks = <&sys_clk 33>; 54 enable-method = "psci"; 55 operating-points-v2 = <&cluster0_opp>; 56 #cooling-cells = <2>; 57 }; 58 59 cpu2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0 0x002>; 63 clocks = <&sys_clk 33>; 64 enable-method = "psci"; 65 operating-points-v2 = <&cluster0_opp>; 66 #cooling-cells = <2>; 67 }; 68 69 cpu3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0 0x003>; 73 clocks = <&sys_clk 33>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cluster0_opp>; 76 #cooling-cells = <2>; 77 }; 78 }; 79 80 cluster0_opp: opp-table { 81 compatible = "operating-points-v2"; 82 opp-shared; 83 84 opp-250000000 { 85 opp-hz = /bits/ 64 <250000000>; 86 clock-latency-ns = <300>; 87 }; 88 opp-325000000 { 89 opp-hz = /bits/ 64 <325000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp-500000000 { 93 opp-hz = /bits/ 64 <500000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-650000000 { 97 opp-hz = /bits/ 64 <650000000>; 98 clock-latency-ns = <300>; 99 }; 100 opp-666667000 { 101 opp-hz = /bits/ 64 <666667000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-866667000 { 105 opp-hz = /bits/ 64 <866667000>; 106 clock-latency-ns = <300>; 107 }; 108 opp-1000000000 { 109 opp-hz = /bits/ 64 <1000000000>; 110 clock-latency-ns = <300>; 111 }; 112 opp-1300000000 { 113 opp-hz = /bits/ 64 <1300000000>; 114 clock-latency-ns = <300>; 115 }; 116 }; 117 118 psci { 119 compatible = "arm,psci-1.0"; 120 method = "smc"; 121 }; 122 123 clocks { 124 refclk: ref { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <25000000>; 128 }; 129 }; 130 131 emmc_pwrseq: emmc-pwrseq { 132 compatible = "mmc-pwrseq-emmc"; 133 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 134 }; 135 136 timer { 137 compatible = "arm,armv8-timer"; 138 interrupts = <1 13 4>, 139 <1 14 4>, 140 <1 11 4>, 141 <1 10 4>; 142 }; 143 144 thermal-zones { 145 cpu-thermal { 146 polling-delay-passive = <250>; /* 250ms */ 147 polling-delay = <1000>; /* 1000ms */ 148 thermal-sensors = <&pvtctl>; 149 150 trips { 151 cpu_crit: cpu-crit { 152 temperature = <110000>; /* 110C */ 153 hysteresis = <2000>; 154 type = "critical"; 155 }; 156 cpu_alert: cpu-alert { 157 temperature = <100000>; /* 100C */ 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 }; 162 163 cooling-maps { 164 map0 { 165 trip = <&cpu_alert>; 166 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 167 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 168 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 169 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 170 }; 171 }; 172 }; 173 }; 174 175 reserved-memory { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges; 179 180 secure-memory@81000000 { 181 reg = <0x0 0x81000000 0x0 0x01000000>; 182 no-map; 183 }; 184 }; 185 186 soc@0 { 187 compatible = "simple-bus"; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges = <0 0 0 0xffffffff>; 191 192 spi0: spi@54006000 { 193 compatible = "socionext,uniphier-scssi"; 194 status = "disabled"; 195 reg = <0x54006000 0x100>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 interrupts = <0 39 4>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_spi0>; 201 clocks = <&peri_clk 11>; 202 resets = <&peri_rst 11>; 203 }; 204 205 spi1: spi@54006100 { 206 compatible = "socionext,uniphier-scssi"; 207 status = "disabled"; 208 reg = <0x54006100 0x100>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <0 216 4>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_spi1>; 214 clocks = <&peri_clk 12>; 215 resets = <&peri_rst 12>; 216 }; 217 218 serial0: serial@54006800 { 219 compatible = "socionext,uniphier-uart"; 220 status = "disabled"; 221 reg = <0x54006800 0x40>; 222 interrupts = <0 33 4>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_uart0>; 225 clocks = <&peri_clk 0>; 226 resets = <&peri_rst 0>; 227 }; 228 229 serial1: serial@54006900 { 230 compatible = "socionext,uniphier-uart"; 231 status = "disabled"; 232 reg = <0x54006900 0x40>; 233 interrupts = <0 35 4>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_uart1>; 236 clocks = <&peri_clk 1>; 237 resets = <&peri_rst 1>; 238 }; 239 240 serial2: serial@54006a00 { 241 compatible = "socionext,uniphier-uart"; 242 status = "disabled"; 243 reg = <0x54006a00 0x40>; 244 interrupts = <0 37 4>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_uart2>; 247 clocks = <&peri_clk 2>; 248 resets = <&peri_rst 2>; 249 }; 250 251 serial3: serial@54006b00 { 252 compatible = "socionext,uniphier-uart"; 253 status = "disabled"; 254 reg = <0x54006b00 0x40>; 255 interrupts = <0 177 4>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_uart3>; 258 clocks = <&peri_clk 3>; 259 resets = <&peri_rst 3>; 260 }; 261 262 gpio: gpio@55000000 { 263 compatible = "socionext,uniphier-gpio"; 264 reg = <0x55000000 0x200>; 265 interrupt-parent = <&aidet>; 266 interrupt-controller; 267 #interrupt-cells = <2>; 268 gpio-controller; 269 #gpio-cells = <2>; 270 gpio-ranges = <&pinctrl 0 0 0>, 271 <&pinctrl 104 0 0>, 272 <&pinctrl 168 0 0>; 273 gpio-ranges-group-names = "gpio_range0", 274 "gpio_range1", 275 "gpio_range2"; 276 ngpios = <286>; 277 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 278 <21 217 3>; 279 }; 280 281 i2c0: i2c@58780000 { 282 compatible = "socionext,uniphier-fi2c"; 283 status = "disabled"; 284 reg = <0x58780000 0x80>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 interrupts = <0 41 4>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_i2c0>; 290 clocks = <&peri_clk 4>; 291 resets = <&peri_rst 4>; 292 clock-frequency = <100000>; 293 }; 294 295 i2c1: i2c@58781000 { 296 compatible = "socionext,uniphier-fi2c"; 297 status = "disabled"; 298 reg = <0x58781000 0x80>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 interrupts = <0 42 4>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_i2c1>; 304 clocks = <&peri_clk 5>; 305 resets = <&peri_rst 5>; 306 clock-frequency = <100000>; 307 }; 308 309 i2c2: i2c@58782000 { 310 compatible = "socionext,uniphier-fi2c"; 311 status = "disabled"; 312 reg = <0x58782000 0x80>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 interrupts = <0 43 4>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_i2c2>; 318 clocks = <&peri_clk 6>; 319 resets = <&peri_rst 6>; 320 clock-frequency = <100000>; 321 }; 322 323 i2c3: i2c@58783000 { 324 compatible = "socionext,uniphier-fi2c"; 325 status = "disabled"; 326 reg = <0x58783000 0x80>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 interrupts = <0 44 4>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_i2c3>; 332 clocks = <&peri_clk 7>; 333 resets = <&peri_rst 7>; 334 clock-frequency = <100000>; 335 }; 336 337 /* chip-internal connection for HDMI */ 338 i2c6: i2c@58786000 { 339 compatible = "socionext,uniphier-fi2c"; 340 reg = <0x58786000 0x80>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 interrupts = <0 26 4>; 344 clocks = <&peri_clk 10>; 345 resets = <&peri_rst 10>; 346 clock-frequency = <400000>; 347 }; 348 349 system_bus: system-bus@58c00000 { 350 compatible = "socionext,uniphier-system-bus"; 351 status = "disabled"; 352 reg = <0x58c00000 0x400>; 353 #address-cells = <2>; 354 #size-cells = <1>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&pinctrl_system_bus>; 357 }; 358 359 smpctrl@59801000 { 360 compatible = "socionext,uniphier-smpctrl"; 361 reg = <0x59801000 0x400>; 362 }; 363 364 sdctrl@59810000 { 365 compatible = "socionext,uniphier-pxs3-sdctrl", 366 "simple-mfd", "syscon"; 367 reg = <0x59810000 0x400>; 368 369 sd_clk: clock { 370 compatible = "socionext,uniphier-pxs3-sd-clock"; 371 #clock-cells = <1>; 372 }; 373 374 sd_rst: reset { 375 compatible = "socionext,uniphier-pxs3-sd-reset"; 376 #reset-cells = <1>; 377 }; 378 }; 379 380 perictrl@59820000 { 381 compatible = "socionext,uniphier-pxs3-perictrl", 382 "simple-mfd", "syscon"; 383 reg = <0x59820000 0x200>; 384 385 peri_clk: clock { 386 compatible = "socionext,uniphier-pxs3-peri-clock"; 387 #clock-cells = <1>; 388 }; 389 390 peri_rst: reset { 391 compatible = "socionext,uniphier-pxs3-peri-reset"; 392 #reset-cells = <1>; 393 }; 394 }; 395 396 emmc: mmc@5a000000 { 397 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 398 reg = <0x5a000000 0x400>; 399 interrupts = <0 78 4>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_emmc>; 402 clocks = <&sys_clk 4>; 403 resets = <&sys_rst 4>; 404 bus-width = <8>; 405 mmc-ddr-1_8v; 406 mmc-hs200-1_8v; 407 mmc-pwrseq = <&emmc_pwrseq>; 408 cdns,phy-input-delay-legacy = <9>; 409 cdns,phy-input-delay-mmc-highspeed = <2>; 410 cdns,phy-input-delay-mmc-ddr = <3>; 411 cdns,phy-dll-delay-sdclk = <21>; 412 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 413 }; 414 415 sd: mmc@5a400000 { 416 compatible = "socionext,uniphier-sd-v3.1.1"; 417 status = "disabled"; 418 reg = <0x5a400000 0x800>; 419 interrupts = <0 76 4>; 420 pinctrl-names = "default", "uhs"; 421 pinctrl-0 = <&pinctrl_sd>; 422 pinctrl-1 = <&pinctrl_sd_uhs>; 423 clocks = <&sd_clk 0>; 424 reset-names = "host"; 425 resets = <&sd_rst 0>; 426 bus-width = <4>; 427 cap-sd-highspeed; 428 sd-uhs-sdr12; 429 sd-uhs-sdr25; 430 sd-uhs-sdr50; 431 }; 432 433 soc_glue: soc-glue@5f800000 { 434 compatible = "socionext,uniphier-pxs3-soc-glue", 435 "simple-mfd", "syscon"; 436 reg = <0x5f800000 0x2000>; 437 438 pinctrl: pinctrl { 439 compatible = "socionext,uniphier-pxs3-pinctrl"; 440 }; 441 }; 442 443 soc-glue@5f900000 { 444 compatible = "socionext,uniphier-pxs3-soc-glue-debug", 445 "simple-mfd"; 446 #address-cells = <1>; 447 #size-cells = <1>; 448 ranges = <0 0x5f900000 0x2000>; 449 450 efuse@100 { 451 compatible = "socionext,uniphier-efuse"; 452 reg = <0x100 0x28>; 453 }; 454 455 efuse@200 { 456 compatible = "socionext,uniphier-efuse"; 457 reg = <0x200 0x68>; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 461 /* USB cells */ 462 usb_rterm0: trim@54,4 { 463 reg = <0x54 1>; 464 bits = <4 2>; 465 }; 466 usb_rterm1: trim@55,4 { 467 reg = <0x55 1>; 468 bits = <4 2>; 469 }; 470 usb_rterm2: trim@58,4 { 471 reg = <0x58 1>; 472 bits = <4 2>; 473 }; 474 usb_rterm3: trim@59,4 { 475 reg = <0x59 1>; 476 bits = <4 2>; 477 }; 478 usb_sel_t0: trim@54,0 { 479 reg = <0x54 1>; 480 bits = <0 4>; 481 }; 482 usb_sel_t1: trim@55,0 { 483 reg = <0x55 1>; 484 bits = <0 4>; 485 }; 486 usb_sel_t2: trim@58,0 { 487 reg = <0x58 1>; 488 bits = <0 4>; 489 }; 490 usb_sel_t3: trim@59,0 { 491 reg = <0x59 1>; 492 bits = <0 4>; 493 }; 494 usb_hs_i0: trim@56,0 { 495 reg = <0x56 1>; 496 bits = <0 4>; 497 }; 498 usb_hs_i2: trim@5a,0 { 499 reg = <0x5a 1>; 500 bits = <0 4>; 501 }; 502 }; 503 }; 504 505 xdmac: dma-controller@5fc10000 { 506 compatible = "socionext,uniphier-xdmac"; 507 reg = <0x5fc10000 0x5300>; 508 interrupts = <0 188 4>; 509 dma-channels = <16>; 510 #dma-cells = <2>; 511 }; 512 513 aidet: interrupt-controller@5fc20000 { 514 compatible = "socionext,uniphier-pxs3-aidet"; 515 reg = <0x5fc20000 0x200>; 516 interrupt-controller; 517 #interrupt-cells = <2>; 518 }; 519 520 gic: interrupt-controller@5fe00000 { 521 compatible = "arm,gic-v3"; 522 reg = <0x5fe00000 0x10000>, /* GICD */ 523 <0x5fe80000 0x80000>; /* GICR */ 524 interrupt-controller; 525 #interrupt-cells = <3>; 526 interrupts = <1 9 4>; 527 }; 528 529 sysctrl@61840000 { 530 compatible = "socionext,uniphier-pxs3-sysctrl", 531 "simple-mfd", "syscon"; 532 reg = <0x61840000 0x10000>; 533 534 sys_clk: clock { 535 compatible = "socionext,uniphier-pxs3-clock"; 536 #clock-cells = <1>; 537 }; 538 539 sys_rst: reset { 540 compatible = "socionext,uniphier-pxs3-reset"; 541 #reset-cells = <1>; 542 }; 543 544 watchdog { 545 compatible = "socionext,uniphier-wdt"; 546 }; 547 548 pvtctl: pvtctl { 549 compatible = "socionext,uniphier-pxs3-thermal"; 550 interrupts = <0 3 4>; 551 #thermal-sensor-cells = <0>; 552 socionext,tmod-calibration = <0x0f22 0x68ee>; 553 }; 554 }; 555 556 eth0: ethernet@65000000 { 557 compatible = "socionext,uniphier-pxs3-ave4"; 558 status = "disabled"; 559 reg = <0x65000000 0x8500>; 560 interrupts = <0 66 4>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_ether_rgmii>; 563 clock-names = "ether"; 564 clocks = <&sys_clk 6>; 565 reset-names = "ether"; 566 resets = <&sys_rst 6>; 567 phy-mode = "rgmii"; 568 local-mac-address = [00 00 00 00 00 00]; 569 socionext,syscon-phy-mode = <&soc_glue 0>; 570 571 mdio0: mdio { 572 #address-cells = <1>; 573 #size-cells = <0>; 574 }; 575 }; 576 577 eth1: ethernet@65200000 { 578 compatible = "socionext,uniphier-pxs3-ave4"; 579 status = "disabled"; 580 reg = <0x65200000 0x8500>; 581 interrupts = <0 67 4>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&pinctrl_ether1_rgmii>; 584 clock-names = "ether"; 585 clocks = <&sys_clk 7>; 586 reset-names = "ether"; 587 resets = <&sys_rst 7>; 588 phy-mode = "rgmii"; 589 local-mac-address = [00 00 00 00 00 00]; 590 socionext,syscon-phy-mode = <&soc_glue 1>; 591 592 mdio1: mdio { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 }; 596 }; 597 598 usb0: usb@65a00000 { 599 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 600 status = "disabled"; 601 reg = <0x65a00000 0xcd00>; 602 interrupt-names = "host", "peripheral"; 603 interrupts = <0 134 4>, <0 135 4>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 606 clock-names = "ref", "bus_early", "suspend"; 607 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; 608 resets = <&usb0_rst 15>; 609 phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 610 <&usb0_ssphy0>, <&usb0_ssphy1>; 611 dr_mode = "host"; 612 }; 613 614 usb-glue@65b00000 { 615 compatible = "socionext,uniphier-pxs3-dwc3-glue", 616 "simple-mfd"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges = <0 0x65b00000 0x400>; 620 621 usb0_rst: reset@0 { 622 compatible = "socionext,uniphier-pxs3-usb3-reset"; 623 reg = <0x0 0x4>; 624 #reset-cells = <1>; 625 clock-names = "link"; 626 clocks = <&sys_clk 12>; 627 reset-names = "link"; 628 resets = <&sys_rst 12>; 629 }; 630 631 usb0_vbus0: regulator@100 { 632 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 633 reg = <0x100 0x10>; 634 clock-names = "link"; 635 clocks = <&sys_clk 12>; 636 reset-names = "link"; 637 resets = <&sys_rst 12>; 638 }; 639 640 usb0_vbus1: regulator@110 { 641 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 642 reg = <0x110 0x10>; 643 clock-names = "link"; 644 clocks = <&sys_clk 12>; 645 reset-names = "link"; 646 resets = <&sys_rst 12>; 647 }; 648 649 usb0_hsphy0: hs-phy@200 { 650 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 651 reg = <0x200 0x10>; 652 #phy-cells = <0>; 653 clock-names = "link", "phy"; 654 clocks = <&sys_clk 12>, <&sys_clk 16>; 655 reset-names = "link", "phy"; 656 resets = <&sys_rst 12>, <&sys_rst 16>; 657 vbus-supply = <&usb0_vbus0>; 658 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 659 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 660 <&usb_hs_i0>; 661 }; 662 663 usb0_hsphy1: hs-phy@210 { 664 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 665 reg = <0x210 0x10>; 666 #phy-cells = <0>; 667 clock-names = "link", "phy"; 668 clocks = <&sys_clk 12>, <&sys_clk 16>; 669 reset-names = "link", "phy"; 670 resets = <&sys_rst 12>, <&sys_rst 16>; 671 vbus-supply = <&usb0_vbus1>; 672 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 673 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 674 <&usb_hs_i0>; 675 }; 676 677 usb0_ssphy0: ss-phy@300 { 678 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 679 reg = <0x300 0x10>; 680 #phy-cells = <0>; 681 clock-names = "link", "phy"; 682 clocks = <&sys_clk 12>, <&sys_clk 17>; 683 reset-names = "link", "phy"; 684 resets = <&sys_rst 12>, <&sys_rst 17>; 685 vbus-supply = <&usb0_vbus0>; 686 }; 687 688 usb0_ssphy1: ss-phy@310 { 689 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 690 reg = <0x310 0x10>; 691 #phy-cells = <0>; 692 clock-names = "link", "phy"; 693 clocks = <&sys_clk 12>, <&sys_clk 18>; 694 reset-names = "link", "phy"; 695 resets = <&sys_rst 12>, <&sys_rst 18>; 696 vbus-supply = <&usb0_vbus1>; 697 }; 698 }; 699 700 usb1: usb@65c00000 { 701 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 702 status = "disabled"; 703 reg = <0x65c00000 0xcd00>; 704 interrupt-names = "host", "peripheral"; 705 interrupts = <0 137 4>, <0 138 4>; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 708 clock-names = "ref", "bus_early", "suspend"; 709 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; 710 resets = <&usb1_rst 15>; 711 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, 712 <&usb1_ssphy0>; 713 dr_mode = "host"; 714 }; 715 716 usb-glue@65d00000 { 717 compatible = "socionext,uniphier-pxs3-dwc3-glue", 718 "simple-mfd"; 719 #address-cells = <1>; 720 #size-cells = <1>; 721 ranges = <0 0x65d00000 0x400>; 722 723 usb1_rst: reset@0 { 724 compatible = "socionext,uniphier-pxs3-usb3-reset"; 725 reg = <0x0 0x4>; 726 #reset-cells = <1>; 727 clock-names = "link"; 728 clocks = <&sys_clk 13>; 729 reset-names = "link"; 730 resets = <&sys_rst 13>; 731 }; 732 733 usb1_vbus0: regulator@100 { 734 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 735 reg = <0x100 0x10>; 736 clock-names = "link"; 737 clocks = <&sys_clk 13>; 738 reset-names = "link"; 739 resets = <&sys_rst 13>; 740 }; 741 742 usb1_vbus1: regulator@110 { 743 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 744 reg = <0x110 0x10>; 745 clock-names = "link"; 746 clocks = <&sys_clk 13>; 747 reset-names = "link"; 748 resets = <&sys_rst 13>; 749 }; 750 751 usb1_hsphy0: hs-phy@200 { 752 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 753 reg = <0x200 0x10>; 754 #phy-cells = <0>; 755 clock-names = "link", "phy", "phy-ext"; 756 clocks = <&sys_clk 13>, <&sys_clk 20>, 757 <&sys_clk 14>; 758 reset-names = "link", "phy"; 759 resets = <&sys_rst 13>, <&sys_rst 20>; 760 vbus-supply = <&usb1_vbus0>; 761 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 762 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 763 <&usb_hs_i2>; 764 }; 765 766 usb1_hsphy1: hs-phy@210 { 767 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 768 reg = <0x210 0x10>; 769 #phy-cells = <0>; 770 clock-names = "link", "phy", "phy-ext"; 771 clocks = <&sys_clk 13>, <&sys_clk 20>, 772 <&sys_clk 14>; 773 reset-names = "link", "phy"; 774 resets = <&sys_rst 13>, <&sys_rst 20>; 775 vbus-supply = <&usb1_vbus1>; 776 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 777 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 778 <&usb_hs_i2>; 779 }; 780 781 usb1_ssphy0: ss-phy@300 { 782 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 783 reg = <0x300 0x10>; 784 #phy-cells = <0>; 785 clock-names = "link", "phy", "phy-ext"; 786 clocks = <&sys_clk 13>, <&sys_clk 21>, 787 <&sys_clk 14>; 788 reset-names = "link", "phy"; 789 resets = <&sys_rst 13>, <&sys_rst 21>; 790 vbus-supply = <&usb1_vbus0>; 791 }; 792 }; 793 794 pcie: pcie@66000000 { 795 compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; 796 status = "disabled"; 797 reg-names = "dbi", "link", "config"; 798 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 799 <0x2fff0000 0x10000>; 800 #address-cells = <3>; 801 #size-cells = <2>; 802 clocks = <&sys_clk 24>; 803 resets = <&sys_rst 24>; 804 num-lanes = <1>; 805 num-viewport = <1>; 806 bus-range = <0x0 0xff>; 807 device_type = "pci"; 808 ranges = 809 /* downstream I/O */ 810 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 811 /* non-prefetchable memory */ 812 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 813 #interrupt-cells = <1>; 814 interrupt-names = "dma", "msi"; 815 interrupts = <0 224 4>, <0 225 4>; 816 interrupt-map-mask = <0 0 0 7>; 817 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 818 <0 0 0 2 &pcie_intc 1>, /* INTB */ 819 <0 0 0 3 &pcie_intc 2>, /* INTC */ 820 <0 0 0 4 &pcie_intc 3>; /* INTD */ 821 phy-names = "pcie-phy"; 822 phys = <&pcie_phy>; 823 824 pcie_intc: legacy-interrupt-controller { 825 interrupt-controller; 826 #interrupt-cells = <1>; 827 interrupt-parent = <&gic>; 828 interrupts = <0 226 4>; 829 }; 830 }; 831 832 pcie_phy: phy@66038000 { 833 compatible = "socionext,uniphier-pxs3-pcie-phy"; 834 reg = <0x66038000 0x4000>; 835 #phy-cells = <0>; 836 clocks = <&sys_clk 24>; 837 resets = <&sys_rst 24>; 838 socionext,syscon = <&soc_glue>; 839 }; 840 841 nand: nand-controller@68000000 { 842 compatible = "socionext,uniphier-denali-nand-v5b"; 843 status = "disabled"; 844 reg-names = "nand_data", "denali_reg"; 845 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 interrupts = <0 65 4>; 849 pinctrl-names = "default"; 850 pinctrl-0 = <&pinctrl_nand>; 851 clock-names = "nand", "nand_x", "ecc"; 852 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 853 reset-names = "nand", "reg"; 854 resets = <&sys_rst 2>, <&sys_rst 2>; 855 }; 856 }; 857}; 858 859#include "uniphier-pinctrl.dtsi" 860