1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Hisilicon Hibmc SoC drm driver 3 * 4 * Based on the bochs drm driver. 5 * 6 * Copyright (c) 2016 Huawei Limited. 7 * 8 * Author: 9 * Rongrong Zou <zourongrong@huawei.com> 10 * Rongrong Zou <zourongrong@gmail.com> 11 * Jianhua Li <lijianhua@huawei.com> 12 */ 13 14 #include <linux/delay.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_fourcc.h> 19 #include <drm/drm_gem_vram_helper.h> 20 #include <drm/drm_plane_helper.h> 21 #include <drm/drm_print.h> 22 #include <drm/drm_probe_helper.h> 23 #include <drm/drm_vblank.h> 24 25 #include "hibmc_drm_drv.h" 26 #include "hibmc_drm_regs.h" 27 28 struct hibmc_display_panel_pll { 29 unsigned long M; 30 unsigned long N; 31 unsigned long OD; 32 unsigned long POD; 33 }; 34 35 struct hibmc_dislay_pll_config { 36 unsigned long hdisplay; 37 unsigned long vdisplay; 38 u32 pll1_config_value; 39 u32 pll2_config_value; 40 }; 41 42 static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { 43 {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, 44 {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, 45 {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, 46 {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, 47 {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, 48 {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, 49 {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 50 {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 51 {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, 52 {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, 53 {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, 54 {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, 55 {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, 56 }; 57 58 #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1))) 59 60 static int hibmc_plane_atomic_check(struct drm_plane *plane, 61 struct drm_plane_state *state) 62 { 63 struct drm_framebuffer *fb = state->fb; 64 struct drm_crtc *crtc = state->crtc; 65 struct drm_crtc_state *crtc_state; 66 u32 src_w = state->src_w >> 16; 67 u32 src_h = state->src_h >> 16; 68 69 if (!crtc || !fb) 70 return 0; 71 72 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 73 if (IS_ERR(crtc_state)) 74 return PTR_ERR(crtc_state); 75 76 if (src_w != state->crtc_w || src_h != state->crtc_h) { 77 DRM_DEBUG_ATOMIC("scale not support\n"); 78 return -EINVAL; 79 } 80 81 if (state->crtc_x < 0 || state->crtc_y < 0) { 82 DRM_DEBUG_ATOMIC("crtc_x/y of drm_plane state is invalid\n"); 83 return -EINVAL; 84 } 85 86 if (!crtc_state->enable) 87 return 0; 88 89 if (state->crtc_x + state->crtc_w > 90 crtc_state->adjusted_mode.hdisplay || 91 state->crtc_y + state->crtc_h > 92 crtc_state->adjusted_mode.vdisplay) { 93 DRM_DEBUG_ATOMIC("visible portion of plane is invalid\n"); 94 return -EINVAL; 95 } 96 97 if (state->fb->pitches[0] % 128 != 0) { 98 DRM_DEBUG_ATOMIC("wrong stride with 128-byte aligned\n"); 99 return -EINVAL; 100 } 101 return 0; 102 } 103 104 static void hibmc_plane_atomic_update(struct drm_plane *plane, 105 struct drm_plane_state *old_state) 106 { 107 struct drm_plane_state *state = plane->state; 108 u32 reg; 109 s64 gpu_addr = 0; 110 unsigned int line_l; 111 struct hibmc_drm_private *priv = plane->dev->dev_private; 112 struct drm_gem_vram_object *gbo; 113 114 if (!state->fb) 115 return; 116 117 gbo = drm_gem_vram_of_gem(state->fb->obj[0]); 118 119 gpu_addr = drm_gem_vram_offset(gbo); 120 if (WARN_ON_ONCE(gpu_addr < 0)) 121 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */ 122 123 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); 124 125 reg = state->fb->width * (state->fb->format->cpp[0]); 126 127 line_l = state->fb->pitches[0]; 128 writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) | 129 HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l), 130 priv->mmio + HIBMC_CRT_FB_WIDTH); 131 132 /* SET PIXEL FORMAT */ 133 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 134 reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK; 135 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT, 136 state->fb->format->cpp[0] * 8 / 16); 137 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 138 } 139 140 static const u32 channel_formats1[] = { 141 DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, DRM_FORMAT_RGB888, 142 DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, 143 DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRA8888, DRM_FORMAT_ARGB8888, 144 DRM_FORMAT_ABGR8888 145 }; 146 147 static struct drm_plane_funcs hibmc_plane_funcs = { 148 .update_plane = drm_atomic_helper_update_plane, 149 .disable_plane = drm_atomic_helper_disable_plane, 150 .destroy = drm_plane_cleanup, 151 .reset = drm_atomic_helper_plane_reset, 152 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 153 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 154 }; 155 156 static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = { 157 .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, 158 .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, 159 .atomic_check = hibmc_plane_atomic_check, 160 .atomic_update = hibmc_plane_atomic_update, 161 }; 162 163 static struct drm_plane *hibmc_plane_init(struct hibmc_drm_private *priv) 164 { 165 struct drm_device *dev = priv->dev; 166 struct drm_plane *plane; 167 int ret = 0; 168 169 plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL); 170 if (!plane) { 171 DRM_ERROR("failed to alloc memory when init plane\n"); 172 return ERR_PTR(-ENOMEM); 173 } 174 /* 175 * plane init 176 * TODO: Now only support primary plane, overlay planes 177 * need to do. 178 */ 179 ret = drm_universal_plane_init(dev, plane, 1, &hibmc_plane_funcs, 180 channel_formats1, 181 ARRAY_SIZE(channel_formats1), 182 NULL, 183 DRM_PLANE_TYPE_PRIMARY, 184 NULL); 185 if (ret) { 186 DRM_ERROR("failed to init plane: %d\n", ret); 187 return ERR_PTR(ret); 188 } 189 190 drm_plane_helper_add(plane, &hibmc_plane_helper_funcs); 191 return plane; 192 } 193 194 static void hibmc_crtc_dpms(struct drm_crtc *crtc, int dpms) 195 { 196 struct hibmc_drm_private *priv = crtc->dev->dev_private; 197 unsigned int reg; 198 199 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 200 reg &= ~HIBMC_CRT_DISP_CTL_DPMS_MASK; 201 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms); 202 reg &= ~HIBMC_CRT_DISP_CTL_TIMING_MASK; 203 if (dpms == HIBMC_CRT_DPMS_ON) 204 reg |= HIBMC_CRT_DISP_CTL_TIMING(1); 205 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 206 } 207 208 static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, 209 struct drm_crtc_state *old_state) 210 { 211 unsigned int reg; 212 struct hibmc_drm_private *priv = crtc->dev->dev_private; 213 214 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 215 216 /* Enable display power gate & LOCALMEM power gate*/ 217 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 218 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 219 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 220 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 221 reg |= HIBMC_CURR_GATE_DISPLAY(1); 222 hibmc_set_current_gate(priv, reg); 223 drm_crtc_vblank_on(crtc); 224 hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_ON); 225 } 226 227 static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, 228 struct drm_crtc_state *old_state) 229 { 230 unsigned int reg; 231 struct hibmc_drm_private *priv = crtc->dev->dev_private; 232 233 hibmc_crtc_dpms(crtc, HIBMC_CRT_DPMS_OFF); 234 drm_crtc_vblank_off(crtc); 235 236 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_SLEEP); 237 238 /* Enable display power gate & LOCALMEM power gate*/ 239 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 240 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 241 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 242 reg |= HIBMC_CURR_GATE_LOCALMEM(0); 243 reg |= HIBMC_CURR_GATE_DISPLAY(0); 244 hibmc_set_current_gate(priv, reg); 245 } 246 247 static enum drm_mode_status 248 hibmc_crtc_mode_valid(struct drm_crtc *crtc, 249 const struct drm_display_mode *mode) 250 { 251 int i = 0; 252 int vrefresh = drm_mode_vrefresh(mode); 253 254 if (vrefresh < 59 || vrefresh > 61) 255 return MODE_NOCLOCK; 256 257 for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { 258 if (hibmc_pll_table[i].hdisplay == mode->hdisplay && 259 hibmc_pll_table[i].vdisplay == mode->vdisplay) 260 return MODE_OK; 261 } 262 263 return MODE_BAD; 264 } 265 266 static unsigned int format_pll_reg(void) 267 { 268 unsigned int pllreg = 0; 269 struct hibmc_display_panel_pll pll = {0}; 270 271 /* 272 * Note that all PLL's have the same format. Here, 273 * we just use Panel PLL parameter to work out the bit 274 * fields in the register.On returning a 32 bit number, the value can 275 * be applied to any PLL in the calling function. 276 */ 277 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0); 278 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1); 279 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0); 280 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); 281 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); 282 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); 283 pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); 284 285 return pllreg; 286 } 287 288 static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll) 289 { 290 u32 val; 291 struct hibmc_drm_private *priv = dev->dev_private; 292 293 val = readl(priv->mmio + CRT_PLL1_HS); 294 val &= ~(CRT_PLL1_HS_OUTER_BYPASS(1)); 295 writel(val, priv->mmio + CRT_PLL1_HS); 296 297 val = CRT_PLL1_HS_INTER_BYPASS(1) | CRT_PLL1_HS_POWERON(1); 298 writel(val, priv->mmio + CRT_PLL1_HS); 299 300 writel(pll, priv->mmio + CRT_PLL1_HS); 301 302 usleep_range(1000, 2000); 303 304 val = pll & ~(CRT_PLL1_HS_POWERON(1)); 305 writel(val, priv->mmio + CRT_PLL1_HS); 306 307 usleep_range(1000, 2000); 308 309 val &= ~(CRT_PLL1_HS_INTER_BYPASS(1)); 310 writel(val, priv->mmio + CRT_PLL1_HS); 311 312 usleep_range(1000, 2000); 313 314 val |= CRT_PLL1_HS_OUTER_BYPASS(1); 315 writel(val, priv->mmio + CRT_PLL1_HS); 316 } 317 318 static void get_pll_config(unsigned long x, unsigned long y, 319 u32 *pll1, u32 *pll2) 320 { 321 int i; 322 int count = ARRAY_SIZE(hibmc_pll_table); 323 324 for (i = 0; i < count; i++) { 325 if (hibmc_pll_table[i].hdisplay == x && 326 hibmc_pll_table[i].vdisplay == y) { 327 *pll1 = hibmc_pll_table[i].pll1_config_value; 328 *pll2 = hibmc_pll_table[i].pll2_config_value; 329 return; 330 } 331 } 332 333 /* if found none, we use default value */ 334 *pll1 = CRT_PLL1_HS_25MHZ; 335 *pll2 = CRT_PLL2_HS_25MHZ; 336 } 337 338 /* 339 * This function takes care the extra registers and bit fields required to 340 * setup a mode in board. 341 * Explanation about Display Control register: 342 * FPGA only supports 7 predefined pixel clocks, and clock select is 343 * in bit 4:0 of new register 0x802a8. 344 */ 345 static unsigned int display_ctrl_adjust(struct drm_device *dev, 346 struct drm_display_mode *mode, 347 unsigned int ctrl) 348 { 349 unsigned long x, y; 350 u32 pll1; /* bit[31:0] of PLL */ 351 u32 pll2; /* bit[63:32] of PLL */ 352 struct hibmc_drm_private *priv = dev->dev_private; 353 354 x = mode->hdisplay; 355 y = mode->vdisplay; 356 357 get_pll_config(x, y, &pll1, &pll2); 358 writel(pll2, priv->mmio + CRT_PLL2_HS); 359 set_vclock_hisilicon(dev, pll1); 360 361 /* 362 * Hisilicon has to set up the top-left and bottom-right 363 * registers as well. 364 * Note that normal chip only use those two register for 365 * auto-centering mode. 366 */ 367 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) | 368 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0), 369 priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL); 370 371 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) | 372 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1), 373 priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR); 374 375 /* 376 * Assume common fields in ctrl have been properly set before 377 * calling this function. 378 * This function only sets the extra fields in ctrl. 379 */ 380 381 /* Set bit 25 of display controller: Select CRT or VGA clock */ 382 ctrl &= ~HIBMC_CRT_DISP_CTL_CRTSELECT_MASK; 383 ctrl &= ~HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK; 384 385 ctrl |= HIBMC_CRT_DISP_CTL_CRTSELECT(HIBMC_CRTSELECT_CRT); 386 387 /* clock_phase_polarity is 0 */ 388 ctrl |= HIBMC_CRT_DISP_CTL_CLOCK_PHASE(0); 389 390 writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL); 391 392 return ctrl; 393 } 394 395 static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc) 396 { 397 unsigned int val; 398 struct drm_display_mode *mode = &crtc->state->mode; 399 struct drm_device *dev = crtc->dev; 400 struct hibmc_drm_private *priv = dev->dev_private; 401 int width = mode->hsync_end - mode->hsync_start; 402 int height = mode->vsync_end - mode->vsync_start; 403 404 writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL); 405 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) | 406 HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1), 407 priv->mmio + HIBMC_CRT_HORZ_TOTAL); 408 409 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) | 410 HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1), 411 priv->mmio + HIBMC_CRT_HORZ_SYNC); 412 413 writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) | 414 HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1), 415 priv->mmio + HIBMC_CRT_VERT_TOTAL); 416 417 writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) | 418 HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1), 419 priv->mmio + HIBMC_CRT_VERT_SYNC); 420 421 val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0); 422 val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0); 423 val |= HIBMC_CRT_DISP_CTL_TIMING(1); 424 val |= HIBMC_CRT_DISP_CTL_PLANE(1); 425 426 display_ctrl_adjust(dev, mode, val); 427 } 428 429 static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, 430 struct drm_crtc_state *old_state) 431 { 432 unsigned int reg; 433 struct drm_device *dev = crtc->dev; 434 struct hibmc_drm_private *priv = dev->dev_private; 435 436 hibmc_set_power_mode(priv, HIBMC_PW_MODE_CTL_MODE_MODE0); 437 438 /* Enable display power gate & LOCALMEM power gate*/ 439 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); 440 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; 441 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; 442 reg |= HIBMC_CURR_GATE_DISPLAY(1); 443 reg |= HIBMC_CURR_GATE_LOCALMEM(1); 444 hibmc_set_current_gate(priv, reg); 445 446 /* We can add more initialization as needed. */ 447 } 448 449 static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc, 450 struct drm_crtc_state *old_state) 451 452 { 453 unsigned long flags; 454 455 spin_lock_irqsave(&crtc->dev->event_lock, flags); 456 if (crtc->state->event) 457 drm_crtc_send_vblank_event(crtc, crtc->state->event); 458 crtc->state->event = NULL; 459 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 460 } 461 462 static int hibmc_crtc_enable_vblank(struct drm_crtc *crtc) 463 { 464 struct hibmc_drm_private *priv = crtc->dev->dev_private; 465 466 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(1), 467 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 468 469 return 0; 470 } 471 472 static void hibmc_crtc_disable_vblank(struct drm_crtc *crtc) 473 { 474 struct hibmc_drm_private *priv = crtc->dev->dev_private; 475 476 writel(HIBMC_RAW_INTERRUPT_EN_VBLANK(0), 477 priv->mmio + HIBMC_RAW_INTERRUPT_EN); 478 } 479 480 static void hibmc_crtc_load_lut(struct drm_crtc *crtc) 481 { 482 struct hibmc_drm_private *priv = crtc->dev->dev_private; 483 void __iomem *mmio = priv->mmio; 484 u16 *r, *g, *b; 485 unsigned int reg; 486 int i; 487 488 r = crtc->gamma_store; 489 g = r + crtc->gamma_size; 490 b = g + crtc->gamma_size; 491 492 for (i = 0; i < crtc->gamma_size; i++) { 493 unsigned int offset = i << 2; 494 u8 red = *r++ >> 8; 495 u8 green = *g++ >> 8; 496 u8 blue = *b++ >> 8; 497 u32 rgb = (red << 16) | (green << 8) | blue; 498 499 writel(rgb, mmio + HIBMC_CRT_PALETTE + offset); 500 } 501 502 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); 503 reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1); 504 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); 505 } 506 507 static int hibmc_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 508 u16 *blue, uint32_t size, 509 struct drm_modeset_acquire_ctx *ctx) 510 { 511 hibmc_crtc_load_lut(crtc); 512 513 return 0; 514 } 515 516 static const struct drm_crtc_funcs hibmc_crtc_funcs = { 517 .page_flip = drm_atomic_helper_page_flip, 518 .set_config = drm_atomic_helper_set_config, 519 .destroy = drm_crtc_cleanup, 520 .reset = drm_atomic_helper_crtc_reset, 521 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 522 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 523 .enable_vblank = hibmc_crtc_enable_vblank, 524 .disable_vblank = hibmc_crtc_disable_vblank, 525 .gamma_set = hibmc_crtc_gamma_set, 526 }; 527 528 static const struct drm_crtc_helper_funcs hibmc_crtc_helper_funcs = { 529 .mode_set_nofb = hibmc_crtc_mode_set_nofb, 530 .atomic_begin = hibmc_crtc_atomic_begin, 531 .atomic_flush = hibmc_crtc_atomic_flush, 532 .atomic_enable = hibmc_crtc_atomic_enable, 533 .atomic_disable = hibmc_crtc_atomic_disable, 534 .mode_valid = hibmc_crtc_mode_valid, 535 }; 536 537 int hibmc_de_init(struct hibmc_drm_private *priv) 538 { 539 struct drm_device *dev = priv->dev; 540 struct drm_crtc *crtc; 541 struct drm_plane *plane; 542 int ret; 543 544 plane = hibmc_plane_init(priv); 545 if (IS_ERR(plane)) { 546 DRM_ERROR("failed to create plane: %ld\n", PTR_ERR(plane)); 547 return PTR_ERR(plane); 548 } 549 550 crtc = devm_kzalloc(dev->dev, sizeof(*crtc), GFP_KERNEL); 551 if (!crtc) { 552 DRM_ERROR("failed to alloc memory when init crtc\n"); 553 return -ENOMEM; 554 } 555 556 ret = drm_crtc_init_with_planes(dev, crtc, plane, 557 NULL, &hibmc_crtc_funcs, NULL); 558 if (ret) { 559 DRM_ERROR("failed to init crtc: %d\n", ret); 560 return ret; 561 } 562 563 ret = drm_mode_crtc_set_gamma_size(crtc, 256); 564 if (ret) { 565 DRM_ERROR("failed to set gamma size: %d\n", ret); 566 return ret; 567 } 568 drm_crtc_helper_add(crtc, &hibmc_crtc_helper_funcs); 569 570 return 0; 571 } 572