1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/netdevice.h> 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/rtnetlink.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/cpumask.h> 13 14 #include "ionic.h" 15 #include "ionic_bus.h" 16 #include "ionic_lif.h" 17 #include "ionic_txrx.h" 18 #include "ionic_ethtool.h" 19 #include "ionic_debugfs.h" 20 21 /* queuetype support level */ 22 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 23 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 24 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 25 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 26 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 27 * 1 = ... with Tx SG version 1 28 */ 29 }; 30 31 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode); 32 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr); 33 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr); 34 static void ionic_link_status_check(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 38 39 static int ionic_start_queues(struct ionic_lif *lif); 40 static void ionic_stop_queues(struct ionic_lif *lif); 41 static void ionic_lif_queue_identify(struct ionic_lif *lif); 42 43 static void ionic_lif_deferred_work(struct work_struct *work) 44 { 45 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 46 struct ionic_deferred *def = &lif->deferred; 47 struct ionic_deferred_work *w = NULL; 48 49 spin_lock_bh(&def->lock); 50 if (!list_empty(&def->list)) { 51 w = list_first_entry(&def->list, 52 struct ionic_deferred_work, list); 53 list_del(&w->list); 54 } 55 spin_unlock_bh(&def->lock); 56 57 if (w) { 58 switch (w->type) { 59 case IONIC_DW_TYPE_RX_MODE: 60 ionic_lif_rx_mode(lif, w->rx_mode); 61 break; 62 case IONIC_DW_TYPE_RX_ADDR_ADD: 63 ionic_lif_addr_add(lif, w->addr); 64 break; 65 case IONIC_DW_TYPE_RX_ADDR_DEL: 66 ionic_lif_addr_del(lif, w->addr); 67 break; 68 case IONIC_DW_TYPE_LINK_STATUS: 69 ionic_link_status_check(lif); 70 break; 71 case IONIC_DW_TYPE_LIF_RESET: 72 if (w->fw_status) 73 ionic_lif_handle_fw_up(lif); 74 else 75 ionic_lif_handle_fw_down(lif); 76 break; 77 default: 78 break; 79 } 80 kfree(w); 81 schedule_work(&def->work); 82 } 83 } 84 85 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 86 struct ionic_deferred_work *work) 87 { 88 spin_lock_bh(&def->lock); 89 list_add_tail(&work->list, &def->list); 90 spin_unlock_bh(&def->lock); 91 schedule_work(&def->work); 92 } 93 94 static void ionic_link_status_check(struct ionic_lif *lif) 95 { 96 struct net_device *netdev = lif->netdev; 97 u16 link_status; 98 bool link_up; 99 100 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 101 return; 102 103 link_status = le16_to_cpu(lif->info->status.link_status); 104 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 105 106 if (link_up) { 107 if (!netif_carrier_ok(netdev)) { 108 u32 link_speed; 109 110 ionic_port_identify(lif->ionic); 111 link_speed = le32_to_cpu(lif->info->status.link_speed); 112 netdev_info(netdev, "Link up - %d Gbps\n", 113 link_speed / 1000); 114 netif_carrier_on(netdev); 115 } 116 117 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 118 mutex_lock(&lif->queue_lock); 119 ionic_start_queues(lif); 120 mutex_unlock(&lif->queue_lock); 121 } 122 } else { 123 if (netif_carrier_ok(netdev)) { 124 netdev_info(netdev, "Link down\n"); 125 netif_carrier_off(netdev); 126 } 127 128 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 129 mutex_lock(&lif->queue_lock); 130 ionic_stop_queues(lif); 131 mutex_unlock(&lif->queue_lock); 132 } 133 } 134 135 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 136 } 137 138 void ionic_link_status_check_request(struct ionic_lif *lif) 139 { 140 struct ionic_deferred_work *work; 141 142 /* we only need one request outstanding at a time */ 143 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 144 return; 145 146 if (in_interrupt()) { 147 work = kzalloc(sizeof(*work), GFP_ATOMIC); 148 if (!work) 149 return; 150 151 work->type = IONIC_DW_TYPE_LINK_STATUS; 152 ionic_lif_deferred_enqueue(&lif->deferred, work); 153 } else { 154 ionic_link_status_check(lif); 155 } 156 } 157 158 static irqreturn_t ionic_isr(int irq, void *data) 159 { 160 struct napi_struct *napi = data; 161 162 napi_schedule_irqoff(napi); 163 164 return IRQ_HANDLED; 165 } 166 167 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 168 { 169 struct ionic_intr_info *intr = &qcq->intr; 170 struct device *dev = lif->ionic->dev; 171 struct ionic_queue *q = &qcq->q; 172 const char *name; 173 174 if (lif->registered) 175 name = lif->netdev->name; 176 else 177 name = dev_name(dev); 178 179 snprintf(intr->name, sizeof(intr->name), 180 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 181 182 return devm_request_irq(dev, intr->vector, ionic_isr, 183 0, intr->name, &qcq->napi); 184 } 185 186 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 187 { 188 struct ionic *ionic = lif->ionic; 189 int index; 190 191 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 192 if (index == ionic->nintrs) { 193 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 194 __func__, index, ionic->nintrs); 195 return -ENOSPC; 196 } 197 198 set_bit(index, ionic->intrs); 199 ionic_intr_init(&ionic->idev, intr, index); 200 201 return 0; 202 } 203 204 static void ionic_intr_free(struct ionic *ionic, int index) 205 { 206 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 207 clear_bit(index, ionic->intrs); 208 } 209 210 static int ionic_qcq_enable(struct ionic_qcq *qcq) 211 { 212 struct ionic_queue *q = &qcq->q; 213 struct ionic_lif *lif = q->lif; 214 struct ionic_dev *idev; 215 struct device *dev; 216 217 struct ionic_admin_ctx ctx = { 218 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 219 .cmd.q_control = { 220 .opcode = IONIC_CMD_Q_CONTROL, 221 .lif_index = cpu_to_le16(lif->index), 222 .type = q->type, 223 .index = cpu_to_le32(q->index), 224 .oper = IONIC_Q_ENABLE, 225 }, 226 }; 227 228 idev = &lif->ionic->idev; 229 dev = lif->ionic->dev; 230 231 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 232 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 233 234 if (qcq->flags & IONIC_QCQ_F_INTR) { 235 irq_set_affinity_hint(qcq->intr.vector, 236 &qcq->intr.affinity_mask); 237 napi_enable(&qcq->napi); 238 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 239 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 240 IONIC_INTR_MASK_CLEAR); 241 } 242 243 return ionic_adminq_post_wait(lif, &ctx); 244 } 245 246 static int ionic_qcq_disable(struct ionic_qcq *qcq) 247 { 248 struct ionic_queue *q = &qcq->q; 249 struct ionic_lif *lif = q->lif; 250 struct ionic_dev *idev; 251 struct device *dev; 252 253 struct ionic_admin_ctx ctx = { 254 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 255 .cmd.q_control = { 256 .opcode = IONIC_CMD_Q_CONTROL, 257 .lif_index = cpu_to_le16(lif->index), 258 .type = q->type, 259 .index = cpu_to_le32(q->index), 260 .oper = IONIC_Q_DISABLE, 261 }, 262 }; 263 264 idev = &lif->ionic->idev; 265 dev = lif->ionic->dev; 266 267 dev_dbg(dev, "q_disable.index %d q_disable.qtype %d\n", 268 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 269 270 if (qcq->flags & IONIC_QCQ_F_INTR) { 271 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 272 IONIC_INTR_MASK_SET); 273 synchronize_irq(qcq->intr.vector); 274 irq_set_affinity_hint(qcq->intr.vector, NULL); 275 napi_disable(&qcq->napi); 276 } 277 278 return ionic_adminq_post_wait(lif, &ctx); 279 } 280 281 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 282 { 283 struct ionic_dev *idev = &lif->ionic->idev; 284 285 if (!qcq) 286 return; 287 288 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 289 return; 290 291 if (qcq->flags & IONIC_QCQ_F_INTR) { 292 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 293 IONIC_INTR_MASK_SET); 294 netif_napi_del(&qcq->napi); 295 } 296 297 qcq->flags &= ~IONIC_QCQ_F_INITED; 298 } 299 300 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 301 { 302 struct device *dev = lif->ionic->dev; 303 304 if (!qcq) 305 return; 306 307 ionic_debugfs_del_qcq(qcq); 308 309 dma_free_coherent(dev, qcq->total_size, qcq->base, qcq->base_pa); 310 qcq->base = NULL; 311 qcq->base_pa = 0; 312 313 if (qcq->flags & IONIC_QCQ_F_INTR) { 314 irq_set_affinity_hint(qcq->intr.vector, NULL); 315 devm_free_irq(dev, qcq->intr.vector, &qcq->napi); 316 qcq->intr.vector = 0; 317 ionic_intr_free(lif->ionic, qcq->intr.index); 318 } 319 320 devm_kfree(dev, qcq->cq.info); 321 qcq->cq.info = NULL; 322 devm_kfree(dev, qcq->q.info); 323 qcq->q.info = NULL; 324 devm_kfree(dev, qcq); 325 } 326 327 static void ionic_qcqs_free(struct ionic_lif *lif) 328 { 329 struct device *dev = lif->ionic->dev; 330 unsigned int i; 331 332 if (lif->notifyqcq) { 333 ionic_qcq_free(lif, lif->notifyqcq); 334 lif->notifyqcq = NULL; 335 } 336 337 if (lif->adminqcq) { 338 ionic_qcq_free(lif, lif->adminqcq); 339 lif->adminqcq = NULL; 340 } 341 342 if (lif->rxqcqs) { 343 for (i = 0; i < lif->nxqs; i++) 344 if (lif->rxqcqs[i].stats) 345 devm_kfree(dev, lif->rxqcqs[i].stats); 346 devm_kfree(dev, lif->rxqcqs); 347 lif->rxqcqs = NULL; 348 } 349 350 if (lif->txqcqs) { 351 for (i = 0; i < lif->nxqs; i++) 352 if (lif->txqcqs[i].stats) 353 devm_kfree(dev, lif->txqcqs[i].stats); 354 devm_kfree(dev, lif->txqcqs); 355 lif->txqcqs = NULL; 356 } 357 } 358 359 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 360 struct ionic_qcq *n_qcq) 361 { 362 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 363 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 364 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 365 } 366 367 n_qcq->intr.vector = src_qcq->intr.vector; 368 n_qcq->intr.index = src_qcq->intr.index; 369 } 370 371 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 372 unsigned int index, 373 const char *name, unsigned int flags, 374 unsigned int num_descs, unsigned int desc_size, 375 unsigned int cq_desc_size, 376 unsigned int sg_desc_size, 377 unsigned int pid, struct ionic_qcq **qcq) 378 { 379 struct ionic_dev *idev = &lif->ionic->idev; 380 u32 q_size, cq_size, sg_size, total_size; 381 struct device *dev = lif->ionic->dev; 382 void *q_base, *cq_base, *sg_base; 383 dma_addr_t cq_base_pa = 0; 384 dma_addr_t sg_base_pa = 0; 385 dma_addr_t q_base_pa = 0; 386 struct ionic_qcq *new; 387 int err; 388 389 *qcq = NULL; 390 391 q_size = num_descs * desc_size; 392 cq_size = num_descs * cq_desc_size; 393 sg_size = num_descs * sg_desc_size; 394 395 total_size = ALIGN(q_size, PAGE_SIZE) + ALIGN(cq_size, PAGE_SIZE); 396 /* Note: aligning q_size/cq_size is not enough due to cq_base 397 * address aligning as q_base could be not aligned to the page. 398 * Adding PAGE_SIZE. 399 */ 400 total_size += PAGE_SIZE; 401 if (flags & IONIC_QCQ_F_SG) { 402 total_size += ALIGN(sg_size, PAGE_SIZE); 403 total_size += PAGE_SIZE; 404 } 405 406 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 407 if (!new) { 408 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 409 err = -ENOMEM; 410 goto err_out; 411 } 412 413 new->flags = flags; 414 415 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 416 GFP_KERNEL); 417 if (!new->q.info) { 418 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 419 err = -ENOMEM; 420 goto err_out; 421 } 422 423 new->q.type = type; 424 425 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 426 desc_size, sg_desc_size, pid); 427 if (err) { 428 netdev_err(lif->netdev, "Cannot initialize queue\n"); 429 goto err_out; 430 } 431 432 if (flags & IONIC_QCQ_F_INTR) { 433 err = ionic_intr_alloc(lif, &new->intr); 434 if (err) { 435 netdev_warn(lif->netdev, "no intr for %s: %d\n", 436 name, err); 437 goto err_out; 438 } 439 440 err = ionic_bus_get_irq(lif->ionic, new->intr.index); 441 if (err < 0) { 442 netdev_warn(lif->netdev, "no vector for %s: %d\n", 443 name, err); 444 goto err_out_free_intr; 445 } 446 new->intr.vector = err; 447 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index, 448 IONIC_INTR_MASK_SET); 449 450 err = ionic_request_irq(lif, new); 451 if (err) { 452 netdev_warn(lif->netdev, "irq request failed %d\n", err); 453 goto err_out_free_intr; 454 } 455 456 new->intr.cpu = cpumask_local_spread(new->intr.index, 457 dev_to_node(dev)); 458 if (new->intr.cpu != -1) 459 cpumask_set_cpu(new->intr.cpu, 460 &new->intr.affinity_mask); 461 } else { 462 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 463 } 464 465 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 466 GFP_KERNEL); 467 if (!new->cq.info) { 468 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 469 err = -ENOMEM; 470 goto err_out_free_irq; 471 } 472 473 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 474 if (err) { 475 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 476 goto err_out_free_irq; 477 } 478 479 new->base = dma_alloc_coherent(dev, total_size, &new->base_pa, 480 GFP_KERNEL); 481 if (!new->base) { 482 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 483 err = -ENOMEM; 484 goto err_out_free_irq; 485 } 486 487 new->total_size = total_size; 488 489 q_base = new->base; 490 q_base_pa = new->base_pa; 491 492 cq_base = (void *)ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); 493 cq_base_pa = ALIGN(q_base_pa + q_size, PAGE_SIZE); 494 495 if (flags & IONIC_QCQ_F_SG) { 496 sg_base = (void *)ALIGN((uintptr_t)cq_base + cq_size, 497 PAGE_SIZE); 498 sg_base_pa = ALIGN(cq_base_pa + cq_size, PAGE_SIZE); 499 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 500 } 501 502 ionic_q_map(&new->q, q_base, q_base_pa); 503 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 504 ionic_cq_bind(&new->cq, &new->q); 505 506 *qcq = new; 507 508 return 0; 509 510 err_out_free_irq: 511 if (flags & IONIC_QCQ_F_INTR) 512 devm_free_irq(dev, new->intr.vector, &new->napi); 513 err_out_free_intr: 514 if (flags & IONIC_QCQ_F_INTR) 515 ionic_intr_free(lif->ionic, new->intr.index); 516 err_out: 517 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 518 return err; 519 } 520 521 static int ionic_qcqs_alloc(struct ionic_lif *lif) 522 { 523 struct device *dev = lif->ionic->dev; 524 unsigned int q_list_size; 525 unsigned int flags; 526 int err; 527 int i; 528 529 flags = IONIC_QCQ_F_INTR; 530 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 531 IONIC_ADMINQ_LENGTH, 532 sizeof(struct ionic_admin_cmd), 533 sizeof(struct ionic_admin_comp), 534 0, lif->kern_pid, &lif->adminqcq); 535 if (err) 536 return err; 537 ionic_debugfs_add_qcq(lif, lif->adminqcq); 538 539 if (lif->ionic->nnqs_per_lif) { 540 flags = IONIC_QCQ_F_NOTIFYQ; 541 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 542 flags, IONIC_NOTIFYQ_LENGTH, 543 sizeof(struct ionic_notifyq_cmd), 544 sizeof(union ionic_notifyq_comp), 545 0, lif->kern_pid, &lif->notifyqcq); 546 if (err) 547 goto err_out_free_adminqcq; 548 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 549 550 /* Let the notifyq ride on the adminq interrupt */ 551 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 552 } 553 554 q_list_size = sizeof(*lif->txqcqs) * lif->nxqs; 555 err = -ENOMEM; 556 lif->txqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL); 557 if (!lif->txqcqs) 558 goto err_out_free_notifyqcq; 559 for (i = 0; i < lif->nxqs; i++) { 560 lif->txqcqs[i].stats = devm_kzalloc(dev, 561 sizeof(struct ionic_q_stats), 562 GFP_KERNEL); 563 if (!lif->txqcqs[i].stats) 564 goto err_out_free_tx_stats; 565 } 566 567 lif->rxqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL); 568 if (!lif->rxqcqs) 569 goto err_out_free_tx_stats; 570 for (i = 0; i < lif->nxqs; i++) { 571 lif->rxqcqs[i].stats = devm_kzalloc(dev, 572 sizeof(struct ionic_q_stats), 573 GFP_KERNEL); 574 if (!lif->rxqcqs[i].stats) 575 goto err_out_free_rx_stats; 576 } 577 578 return 0; 579 580 err_out_free_rx_stats: 581 for (i = 0; i < lif->nxqs; i++) 582 if (lif->rxqcqs[i].stats) 583 devm_kfree(dev, lif->rxqcqs[i].stats); 584 devm_kfree(dev, lif->rxqcqs); 585 lif->rxqcqs = NULL; 586 err_out_free_tx_stats: 587 for (i = 0; i < lif->nxqs; i++) 588 if (lif->txqcqs[i].stats) 589 devm_kfree(dev, lif->txqcqs[i].stats); 590 devm_kfree(dev, lif->txqcqs); 591 lif->txqcqs = NULL; 592 err_out_free_notifyqcq: 593 if (lif->notifyqcq) { 594 ionic_qcq_free(lif, lif->notifyqcq); 595 lif->notifyqcq = NULL; 596 } 597 err_out_free_adminqcq: 598 ionic_qcq_free(lif, lif->adminqcq); 599 lif->adminqcq = NULL; 600 601 return err; 602 } 603 604 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 605 { 606 struct device *dev = lif->ionic->dev; 607 struct ionic_queue *q = &qcq->q; 608 struct ionic_cq *cq = &qcq->cq; 609 struct ionic_admin_ctx ctx = { 610 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 611 .cmd.q_init = { 612 .opcode = IONIC_CMD_Q_INIT, 613 .lif_index = cpu_to_le16(lif->index), 614 .type = q->type, 615 .ver = lif->qtype_info[q->type].version, 616 .index = cpu_to_le32(q->index), 617 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 618 IONIC_QINIT_F_SG), 619 .pid = cpu_to_le16(q->pid), 620 .ring_size = ilog2(q->num_descs), 621 .ring_base = cpu_to_le64(q->base_pa), 622 .cq_ring_base = cpu_to_le64(cq->base_pa), 623 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 624 }, 625 }; 626 unsigned int intr_index; 627 int err; 628 629 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 630 intr_index = qcq->intr.index; 631 else 632 intr_index = lif->rxqcqs[q->index].qcq->intr.index; 633 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 634 635 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 636 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 637 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 638 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 639 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 640 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 641 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 642 643 q->tail = q->info; 644 q->head = q->tail; 645 cq->tail = cq->info; 646 647 err = ionic_adminq_post_wait(lif, &ctx); 648 if (err) 649 return err; 650 651 q->hw_type = ctx.comp.q_init.hw_type; 652 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 653 q->dbval = IONIC_DBELL_QID(q->hw_index); 654 655 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 656 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 657 658 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 659 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 660 NAPI_POLL_WEIGHT); 661 662 qcq->flags |= IONIC_QCQ_F_INITED; 663 664 return 0; 665 } 666 667 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 668 { 669 struct device *dev = lif->ionic->dev; 670 struct ionic_queue *q = &qcq->q; 671 struct ionic_cq *cq = &qcq->cq; 672 struct ionic_admin_ctx ctx = { 673 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 674 .cmd.q_init = { 675 .opcode = IONIC_CMD_Q_INIT, 676 .lif_index = cpu_to_le16(lif->index), 677 .type = q->type, 678 .ver = lif->qtype_info[q->type].version, 679 .index = cpu_to_le32(q->index), 680 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 681 IONIC_QINIT_F_SG), 682 .intr_index = cpu_to_le16(cq->bound_intr->index), 683 .pid = cpu_to_le16(q->pid), 684 .ring_size = ilog2(q->num_descs), 685 .ring_base = cpu_to_le64(q->base_pa), 686 .cq_ring_base = cpu_to_le64(cq->base_pa), 687 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 688 }, 689 }; 690 int err; 691 692 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 693 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 694 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 695 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 696 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 697 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 698 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 699 700 q->tail = q->info; 701 q->head = q->tail; 702 cq->tail = cq->info; 703 704 err = ionic_adminq_post_wait(lif, &ctx); 705 if (err) 706 return err; 707 708 q->hw_type = ctx.comp.q_init.hw_type; 709 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 710 q->dbval = IONIC_DBELL_QID(q->hw_index); 711 712 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 713 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 714 715 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 716 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 717 NAPI_POLL_WEIGHT); 718 else 719 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 720 NAPI_POLL_WEIGHT); 721 722 qcq->flags |= IONIC_QCQ_F_INITED; 723 724 return 0; 725 } 726 727 static bool ionic_notifyq_service(struct ionic_cq *cq, 728 struct ionic_cq_info *cq_info) 729 { 730 union ionic_notifyq_comp *comp = cq_info->cq_desc; 731 struct ionic_deferred_work *work; 732 struct net_device *netdev; 733 struct ionic_queue *q; 734 struct ionic_lif *lif; 735 u64 eid; 736 737 q = cq->bound_q; 738 lif = q->info[0].cb_arg; 739 netdev = lif->netdev; 740 eid = le64_to_cpu(comp->event.eid); 741 742 /* Have we run out of new completions to process? */ 743 if ((s64)(eid - lif->last_eid) <= 0) 744 return false; 745 746 lif->last_eid = eid; 747 748 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 749 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 750 comp, sizeof(*comp), true); 751 752 switch (le16_to_cpu(comp->event.ecode)) { 753 case IONIC_EVENT_LINK_CHANGE: 754 ionic_link_status_check_request(lif); 755 break; 756 case IONIC_EVENT_RESET: 757 work = kzalloc(sizeof(*work), GFP_ATOMIC); 758 if (!work) { 759 netdev_err(lif->netdev, "%s OOM\n", __func__); 760 } else { 761 work->type = IONIC_DW_TYPE_LIF_RESET; 762 ionic_lif_deferred_enqueue(&lif->deferred, work); 763 } 764 break; 765 default: 766 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 767 comp->event.ecode, eid); 768 break; 769 } 770 771 return true; 772 } 773 774 static int ionic_notifyq_clean(struct ionic_lif *lif, int budget) 775 { 776 struct ionic_dev *idev = &lif->ionic->idev; 777 struct ionic_cq *cq = &lif->notifyqcq->cq; 778 u32 work_done; 779 780 work_done = ionic_cq_service(cq, budget, ionic_notifyq_service, 781 NULL, NULL); 782 if (work_done) 783 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 784 work_done, IONIC_INTR_CRED_RESET_COALESCE); 785 786 return work_done; 787 } 788 789 static bool ionic_adminq_service(struct ionic_cq *cq, 790 struct ionic_cq_info *cq_info) 791 { 792 struct ionic_admin_comp *comp = cq_info->cq_desc; 793 794 if (!color_match(comp->color, cq->done_color)) 795 return false; 796 797 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 798 799 return true; 800 } 801 802 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 803 { 804 struct ionic_lif *lif = napi_to_cq(napi)->lif; 805 int n_work = 0; 806 int a_work = 0; 807 808 if (likely(lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)) 809 n_work = ionic_notifyq_clean(lif, budget); 810 a_work = ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL); 811 812 return max(n_work, a_work); 813 } 814 815 void ionic_get_stats64(struct net_device *netdev, 816 struct rtnl_link_stats64 *ns) 817 { 818 struct ionic_lif *lif = netdev_priv(netdev); 819 struct ionic_lif_stats *ls; 820 821 memset(ns, 0, sizeof(*ns)); 822 ls = &lif->info->stats; 823 824 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 825 le64_to_cpu(ls->rx_mcast_packets) + 826 le64_to_cpu(ls->rx_bcast_packets); 827 828 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 829 le64_to_cpu(ls->tx_mcast_packets) + 830 le64_to_cpu(ls->tx_bcast_packets); 831 832 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 833 le64_to_cpu(ls->rx_mcast_bytes) + 834 le64_to_cpu(ls->rx_bcast_bytes); 835 836 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 837 le64_to_cpu(ls->tx_mcast_bytes) + 838 le64_to_cpu(ls->tx_bcast_bytes); 839 840 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 841 le64_to_cpu(ls->rx_mcast_drop_packets) + 842 le64_to_cpu(ls->rx_bcast_drop_packets); 843 844 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 845 le64_to_cpu(ls->tx_mcast_drop_packets) + 846 le64_to_cpu(ls->tx_bcast_drop_packets); 847 848 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 849 850 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 851 852 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 853 le64_to_cpu(ls->rx_queue_disabled) + 854 le64_to_cpu(ls->rx_desc_fetch_error) + 855 le64_to_cpu(ls->rx_desc_data_error); 856 857 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 858 le64_to_cpu(ls->tx_queue_disabled) + 859 le64_to_cpu(ls->tx_desc_fetch_error) + 860 le64_to_cpu(ls->tx_desc_data_error); 861 862 ns->rx_errors = ns->rx_over_errors + 863 ns->rx_missed_errors; 864 865 ns->tx_errors = ns->tx_aborted_errors; 866 } 867 868 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 869 { 870 struct ionic_admin_ctx ctx = { 871 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 872 .cmd.rx_filter_add = { 873 .opcode = IONIC_CMD_RX_FILTER_ADD, 874 .lif_index = cpu_to_le16(lif->index), 875 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 876 }, 877 }; 878 struct ionic_rx_filter *f; 879 int err; 880 881 /* don't bother if we already have it */ 882 spin_lock_bh(&lif->rx_filters.lock); 883 f = ionic_rx_filter_by_addr(lif, addr); 884 spin_unlock_bh(&lif->rx_filters.lock); 885 if (f) 886 return 0; 887 888 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 889 890 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 891 err = ionic_adminq_post_wait(lif, &ctx); 892 if (err && err != -EEXIST) 893 return err; 894 895 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 896 } 897 898 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 899 { 900 struct ionic_admin_ctx ctx = { 901 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 902 .cmd.rx_filter_del = { 903 .opcode = IONIC_CMD_RX_FILTER_DEL, 904 .lif_index = cpu_to_le16(lif->index), 905 }, 906 }; 907 struct ionic_rx_filter *f; 908 int err; 909 910 spin_lock_bh(&lif->rx_filters.lock); 911 f = ionic_rx_filter_by_addr(lif, addr); 912 if (!f) { 913 spin_unlock_bh(&lif->rx_filters.lock); 914 return -ENOENT; 915 } 916 917 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 918 addr, f->filter_id); 919 920 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 921 ionic_rx_filter_free(lif, f); 922 spin_unlock_bh(&lif->rx_filters.lock); 923 924 err = ionic_adminq_post_wait(lif, &ctx); 925 if (err && err != -EEXIST) 926 return err; 927 928 return 0; 929 } 930 931 static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add) 932 { 933 struct ionic *ionic = lif->ionic; 934 struct ionic_deferred_work *work; 935 unsigned int nmfilters; 936 unsigned int nufilters; 937 938 if (add) { 939 /* Do we have space for this filter? We test the counters 940 * here before checking the need for deferral so that we 941 * can return an overflow error to the stack. 942 */ 943 nmfilters = le32_to_cpu(ionic->ident.lif.eth.max_mcast_filters); 944 nufilters = le32_to_cpu(ionic->ident.lif.eth.max_ucast_filters); 945 946 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters)) 947 lif->nmcast++; 948 else if (!is_multicast_ether_addr(addr) && 949 lif->nucast < nufilters) 950 lif->nucast++; 951 else 952 return -ENOSPC; 953 } else { 954 if (is_multicast_ether_addr(addr) && lif->nmcast) 955 lif->nmcast--; 956 else if (!is_multicast_ether_addr(addr) && lif->nucast) 957 lif->nucast--; 958 } 959 960 if (in_interrupt()) { 961 work = kzalloc(sizeof(*work), GFP_ATOMIC); 962 if (!work) { 963 netdev_err(lif->netdev, "%s OOM\n", __func__); 964 return -ENOMEM; 965 } 966 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD : 967 IONIC_DW_TYPE_RX_ADDR_DEL; 968 memcpy(work->addr, addr, ETH_ALEN); 969 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n", 970 add ? "add" : "del", addr); 971 ionic_lif_deferred_enqueue(&lif->deferred, work); 972 } else { 973 netdev_dbg(lif->netdev, "rx_filter %s %pM\n", 974 add ? "add" : "del", addr); 975 if (add) 976 return ionic_lif_addr_add(lif, addr); 977 else 978 return ionic_lif_addr_del(lif, addr); 979 } 980 981 return 0; 982 } 983 984 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 985 { 986 return ionic_lif_addr(netdev_priv(netdev), addr, true); 987 } 988 989 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 990 { 991 return ionic_lif_addr(netdev_priv(netdev), addr, false); 992 } 993 994 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 995 { 996 struct ionic_admin_ctx ctx = { 997 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 998 .cmd.rx_mode_set = { 999 .opcode = IONIC_CMD_RX_MODE_SET, 1000 .lif_index = cpu_to_le16(lif->index), 1001 .rx_mode = cpu_to_le16(rx_mode), 1002 }, 1003 }; 1004 char buf[128]; 1005 int err; 1006 int i; 1007 #define REMAIN(__x) (sizeof(buf) - (__x)) 1008 1009 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1010 lif->rx_mode, rx_mode); 1011 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1012 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1013 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1014 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1015 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1016 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1017 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1018 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1019 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1020 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1021 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf); 1022 1023 err = ionic_adminq_post_wait(lif, &ctx); 1024 if (err) 1025 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n", 1026 rx_mode, err); 1027 else 1028 lif->rx_mode = rx_mode; 1029 } 1030 1031 static void _ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 1032 { 1033 struct ionic_deferred_work *work; 1034 1035 if (in_interrupt()) { 1036 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1037 if (!work) { 1038 netdev_err(lif->netdev, "%s OOM\n", __func__); 1039 return; 1040 } 1041 work->type = IONIC_DW_TYPE_RX_MODE; 1042 work->rx_mode = rx_mode; 1043 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1044 ionic_lif_deferred_enqueue(&lif->deferred, work); 1045 } else { 1046 ionic_lif_rx_mode(lif, rx_mode); 1047 } 1048 } 1049 1050 static void ionic_set_rx_mode(struct net_device *netdev) 1051 { 1052 struct ionic_lif *lif = netdev_priv(netdev); 1053 struct ionic_identity *ident; 1054 unsigned int nfilters; 1055 unsigned int rx_mode; 1056 1057 ident = &lif->ionic->ident; 1058 1059 rx_mode = IONIC_RX_MODE_F_UNICAST; 1060 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1061 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1062 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1063 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1064 1065 /* sync unicast addresses 1066 * next check to see if we're in an overflow state 1067 * if so, we track that we overflowed and enable NIC PROMISC 1068 * else if the overflow is set and not needed 1069 * we remove our overflow flag and check the netdev flags 1070 * to see if we can disable NIC PROMISC 1071 */ 1072 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1073 nfilters = le32_to_cpu(ident->lif.eth.max_ucast_filters); 1074 if (netdev_uc_count(netdev) + 1 > nfilters) { 1075 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1076 lif->uc_overflow = true; 1077 } else if (lif->uc_overflow) { 1078 lif->uc_overflow = false; 1079 if (!(netdev->flags & IFF_PROMISC)) 1080 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1081 } 1082 1083 /* same for multicast */ 1084 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1085 nfilters = le32_to_cpu(ident->lif.eth.max_mcast_filters); 1086 if (netdev_mc_count(netdev) > nfilters) { 1087 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1088 lif->mc_overflow = true; 1089 } else if (lif->mc_overflow) { 1090 lif->mc_overflow = false; 1091 if (!(netdev->flags & IFF_ALLMULTI)) 1092 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1093 } 1094 1095 if (lif->rx_mode != rx_mode) 1096 _ionic_lif_rx_mode(lif, rx_mode); 1097 } 1098 1099 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1100 { 1101 u64 wanted = 0; 1102 1103 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1104 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1105 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1106 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1107 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1108 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1109 if (features & NETIF_F_RXHASH) 1110 wanted |= IONIC_ETH_HW_RX_HASH; 1111 if (features & NETIF_F_RXCSUM) 1112 wanted |= IONIC_ETH_HW_RX_CSUM; 1113 if (features & NETIF_F_SG) 1114 wanted |= IONIC_ETH_HW_TX_SG; 1115 if (features & NETIF_F_HW_CSUM) 1116 wanted |= IONIC_ETH_HW_TX_CSUM; 1117 if (features & NETIF_F_TSO) 1118 wanted |= IONIC_ETH_HW_TSO; 1119 if (features & NETIF_F_TSO6) 1120 wanted |= IONIC_ETH_HW_TSO_IPV6; 1121 if (features & NETIF_F_TSO_ECN) 1122 wanted |= IONIC_ETH_HW_TSO_ECN; 1123 if (features & NETIF_F_GSO_GRE) 1124 wanted |= IONIC_ETH_HW_TSO_GRE; 1125 if (features & NETIF_F_GSO_GRE_CSUM) 1126 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1127 if (features & NETIF_F_GSO_IPXIP4) 1128 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1129 if (features & NETIF_F_GSO_IPXIP6) 1130 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1131 if (features & NETIF_F_GSO_UDP_TUNNEL) 1132 wanted |= IONIC_ETH_HW_TSO_UDP; 1133 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1134 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1135 1136 return cpu_to_le64(wanted); 1137 } 1138 1139 static int ionic_set_nic_features(struct ionic_lif *lif, 1140 netdev_features_t features) 1141 { 1142 struct device *dev = lif->ionic->dev; 1143 struct ionic_admin_ctx ctx = { 1144 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1145 .cmd.lif_setattr = { 1146 .opcode = IONIC_CMD_LIF_SETATTR, 1147 .index = cpu_to_le16(lif->index), 1148 .attr = IONIC_LIF_ATTR_FEATURES, 1149 }, 1150 }; 1151 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1152 IONIC_ETH_HW_VLAN_RX_STRIP | 1153 IONIC_ETH_HW_VLAN_RX_FILTER; 1154 u64 old_hw_features; 1155 int err; 1156 1157 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1158 err = ionic_adminq_post_wait(lif, &ctx); 1159 if (err) 1160 return err; 1161 1162 old_hw_features = lif->hw_features; 1163 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1164 ctx.comp.lif_setattr.features); 1165 1166 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1167 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1168 1169 if ((vlan_flags & features) && 1170 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1171 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1172 1173 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1174 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1175 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1176 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1177 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1178 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1179 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1180 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1181 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1182 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1183 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1184 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1185 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1186 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1187 if (lif->hw_features & IONIC_ETH_HW_TSO) 1188 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1189 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1190 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1191 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1192 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1193 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1194 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1195 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1196 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1197 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1198 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1199 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1200 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1201 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1202 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1203 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1204 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1205 1206 return 0; 1207 } 1208 1209 static int ionic_init_nic_features(struct ionic_lif *lif) 1210 { 1211 struct net_device *netdev = lif->netdev; 1212 netdev_features_t features; 1213 int err; 1214 1215 /* set up what we expect to support by default */ 1216 features = NETIF_F_HW_VLAN_CTAG_TX | 1217 NETIF_F_HW_VLAN_CTAG_RX | 1218 NETIF_F_HW_VLAN_CTAG_FILTER | 1219 NETIF_F_RXHASH | 1220 NETIF_F_SG | 1221 NETIF_F_HW_CSUM | 1222 NETIF_F_RXCSUM | 1223 NETIF_F_TSO | 1224 NETIF_F_TSO6 | 1225 NETIF_F_TSO_ECN; 1226 1227 err = ionic_set_nic_features(lif, features); 1228 if (err) 1229 return err; 1230 1231 /* tell the netdev what we actually can support */ 1232 netdev->features |= NETIF_F_HIGHDMA; 1233 1234 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1235 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1236 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1237 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1238 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1239 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1240 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1241 netdev->hw_features |= NETIF_F_RXHASH; 1242 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1243 netdev->hw_features |= NETIF_F_SG; 1244 1245 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1246 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1247 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1248 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1249 if (lif->hw_features & IONIC_ETH_HW_TSO) 1250 netdev->hw_enc_features |= NETIF_F_TSO; 1251 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1252 netdev->hw_enc_features |= NETIF_F_TSO6; 1253 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1254 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1255 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1256 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1257 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1258 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1259 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1260 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1261 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1262 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1263 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1264 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1265 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1266 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1267 1268 netdev->hw_features |= netdev->hw_enc_features; 1269 netdev->features |= netdev->hw_features; 1270 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1271 1272 netdev->priv_flags |= IFF_UNICAST_FLT | 1273 IFF_LIVE_ADDR_CHANGE; 1274 1275 return 0; 1276 } 1277 1278 static int ionic_set_features(struct net_device *netdev, 1279 netdev_features_t features) 1280 { 1281 struct ionic_lif *lif = netdev_priv(netdev); 1282 int err; 1283 1284 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1285 __func__, (u64)lif->netdev->features, (u64)features); 1286 1287 err = ionic_set_nic_features(lif, features); 1288 1289 return err; 1290 } 1291 1292 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1293 { 1294 struct sockaddr *addr = sa; 1295 u8 *mac; 1296 int err; 1297 1298 mac = (u8 *)addr->sa_data; 1299 if (ether_addr_equal(netdev->dev_addr, mac)) 1300 return 0; 1301 1302 err = eth_prepare_mac_addr_change(netdev, addr); 1303 if (err) 1304 return err; 1305 1306 if (!is_zero_ether_addr(netdev->dev_addr)) { 1307 netdev_info(netdev, "deleting mac addr %pM\n", 1308 netdev->dev_addr); 1309 ionic_addr_del(netdev, netdev->dev_addr); 1310 } 1311 1312 eth_commit_mac_addr_change(netdev, addr); 1313 netdev_info(netdev, "updating mac addr %pM\n", mac); 1314 1315 return ionic_addr_add(netdev, mac); 1316 } 1317 1318 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1319 { 1320 struct ionic_lif *lif = netdev_priv(netdev); 1321 struct ionic_admin_ctx ctx = { 1322 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1323 .cmd.lif_setattr = { 1324 .opcode = IONIC_CMD_LIF_SETATTR, 1325 .index = cpu_to_le16(lif->index), 1326 .attr = IONIC_LIF_ATTR_MTU, 1327 .mtu = cpu_to_le32(new_mtu), 1328 }, 1329 }; 1330 int err; 1331 1332 err = ionic_adminq_post_wait(lif, &ctx); 1333 if (err) 1334 return err; 1335 1336 netdev->mtu = new_mtu; 1337 err = ionic_reset_queues(lif, NULL, NULL); 1338 1339 return err; 1340 } 1341 1342 static void ionic_tx_timeout_work(struct work_struct *ws) 1343 { 1344 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1345 1346 netdev_info(lif->netdev, "Tx Timeout recovery\n"); 1347 1348 rtnl_lock(); 1349 ionic_reset_queues(lif, NULL, NULL); 1350 rtnl_unlock(); 1351 } 1352 1353 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1354 { 1355 struct ionic_lif *lif = netdev_priv(netdev); 1356 1357 schedule_work(&lif->tx_timeout_work); 1358 } 1359 1360 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1361 u16 vid) 1362 { 1363 struct ionic_lif *lif = netdev_priv(netdev); 1364 struct ionic_admin_ctx ctx = { 1365 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1366 .cmd.rx_filter_add = { 1367 .opcode = IONIC_CMD_RX_FILTER_ADD, 1368 .lif_index = cpu_to_le16(lif->index), 1369 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1370 .vlan.vlan = cpu_to_le16(vid), 1371 }, 1372 }; 1373 int err; 1374 1375 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1376 err = ionic_adminq_post_wait(lif, &ctx); 1377 if (err) 1378 return err; 1379 1380 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 1381 } 1382 1383 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1384 u16 vid) 1385 { 1386 struct ionic_lif *lif = netdev_priv(netdev); 1387 struct ionic_admin_ctx ctx = { 1388 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1389 .cmd.rx_filter_del = { 1390 .opcode = IONIC_CMD_RX_FILTER_DEL, 1391 .lif_index = cpu_to_le16(lif->index), 1392 }, 1393 }; 1394 struct ionic_rx_filter *f; 1395 1396 spin_lock_bh(&lif->rx_filters.lock); 1397 1398 f = ionic_rx_filter_by_vlan(lif, vid); 1399 if (!f) { 1400 spin_unlock_bh(&lif->rx_filters.lock); 1401 return -ENOENT; 1402 } 1403 1404 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1405 vid, f->filter_id); 1406 1407 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1408 ionic_rx_filter_free(lif, f); 1409 spin_unlock_bh(&lif->rx_filters.lock); 1410 1411 return ionic_adminq_post_wait(lif, &ctx); 1412 } 1413 1414 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1415 const u8 *key, const u32 *indir) 1416 { 1417 struct ionic_admin_ctx ctx = { 1418 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1419 .cmd.lif_setattr = { 1420 .opcode = IONIC_CMD_LIF_SETATTR, 1421 .attr = IONIC_LIF_ATTR_RSS, 1422 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1423 }, 1424 }; 1425 unsigned int i, tbl_sz; 1426 1427 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1428 lif->rss_types = types; 1429 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1430 } 1431 1432 if (key) 1433 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1434 1435 if (indir) { 1436 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1437 for (i = 0; i < tbl_sz; i++) 1438 lif->rss_ind_tbl[i] = indir[i]; 1439 } 1440 1441 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1442 IONIC_RSS_HASH_KEY_SIZE); 1443 1444 return ionic_adminq_post_wait(lif, &ctx); 1445 } 1446 1447 static int ionic_lif_rss_init(struct ionic_lif *lif) 1448 { 1449 unsigned int tbl_sz; 1450 unsigned int i; 1451 1452 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1453 IONIC_RSS_TYPE_IPV4_TCP | 1454 IONIC_RSS_TYPE_IPV4_UDP | 1455 IONIC_RSS_TYPE_IPV6 | 1456 IONIC_RSS_TYPE_IPV6_TCP | 1457 IONIC_RSS_TYPE_IPV6_UDP; 1458 1459 /* Fill indirection table with 'default' values */ 1460 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1461 for (i = 0; i < tbl_sz; i++) 1462 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1463 1464 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1465 } 1466 1467 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1468 { 1469 int tbl_sz; 1470 1471 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1472 memset(lif->rss_ind_tbl, 0, tbl_sz); 1473 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1474 1475 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1476 } 1477 1478 static void ionic_txrx_disable(struct ionic_lif *lif) 1479 { 1480 unsigned int i; 1481 int err; 1482 1483 if (lif->txqcqs) { 1484 for (i = 0; i < lif->nxqs; i++) { 1485 err = ionic_qcq_disable(lif->txqcqs[i].qcq); 1486 if (err == -ETIMEDOUT) 1487 break; 1488 } 1489 } 1490 1491 if (lif->rxqcqs) { 1492 for (i = 0; i < lif->nxqs; i++) { 1493 err = ionic_qcq_disable(lif->rxqcqs[i].qcq); 1494 if (err == -ETIMEDOUT) 1495 break; 1496 } 1497 } 1498 } 1499 1500 static void ionic_txrx_deinit(struct ionic_lif *lif) 1501 { 1502 unsigned int i; 1503 1504 if (lif->txqcqs) { 1505 for (i = 0; i < lif->nxqs; i++) { 1506 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1507 ionic_tx_flush(&lif->txqcqs[i].qcq->cq); 1508 ionic_tx_empty(&lif->txqcqs[i].qcq->q); 1509 } 1510 } 1511 1512 if (lif->rxqcqs) { 1513 for (i = 0; i < lif->nxqs; i++) { 1514 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq); 1515 ionic_rx_flush(&lif->rxqcqs[i].qcq->cq); 1516 ionic_rx_empty(&lif->rxqcqs[i].qcq->q); 1517 } 1518 } 1519 lif->rx_mode = 0; 1520 } 1521 1522 static void ionic_txrx_free(struct ionic_lif *lif) 1523 { 1524 unsigned int i; 1525 1526 if (lif->txqcqs) { 1527 for (i = 0; i < lif->nxqs; i++) { 1528 ionic_qcq_free(lif, lif->txqcqs[i].qcq); 1529 lif->txqcqs[i].qcq = NULL; 1530 } 1531 } 1532 1533 if (lif->rxqcqs) { 1534 for (i = 0; i < lif->nxqs; i++) { 1535 ionic_qcq_free(lif, lif->rxqcqs[i].qcq); 1536 lif->rxqcqs[i].qcq = NULL; 1537 } 1538 } 1539 } 1540 1541 static int ionic_txrx_alloc(struct ionic_lif *lif) 1542 { 1543 unsigned int sg_desc_sz; 1544 unsigned int flags; 1545 unsigned int i; 1546 int err = 0; 1547 1548 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1549 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1550 sizeof(struct ionic_txq_sg_desc_v1)) 1551 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1552 else 1553 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1554 1555 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1556 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1557 flags |= IONIC_QCQ_F_INTR; 1558 for (i = 0; i < lif->nxqs; i++) { 1559 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1560 lif->ntxq_descs, 1561 sizeof(struct ionic_txq_desc), 1562 sizeof(struct ionic_txq_comp), 1563 sg_desc_sz, 1564 lif->kern_pid, &lif->txqcqs[i].qcq); 1565 if (err) 1566 goto err_out; 1567 1568 if (flags & IONIC_QCQ_F_INTR) 1569 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1570 lif->txqcqs[i].qcq->intr.index, 1571 lif->tx_coalesce_hw); 1572 1573 lif->txqcqs[i].qcq->stats = lif->txqcqs[i].stats; 1574 ionic_debugfs_add_qcq(lif, lif->txqcqs[i].qcq); 1575 } 1576 1577 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1578 for (i = 0; i < lif->nxqs; i++) { 1579 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1580 lif->nrxq_descs, 1581 sizeof(struct ionic_rxq_desc), 1582 sizeof(struct ionic_rxq_comp), 1583 sizeof(struct ionic_rxq_sg_desc), 1584 lif->kern_pid, &lif->rxqcqs[i].qcq); 1585 if (err) 1586 goto err_out; 1587 1588 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1589 lif->rxqcqs[i].qcq->intr.index, 1590 lif->rx_coalesce_hw); 1591 1592 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1593 ionic_link_qcq_interrupts(lif->rxqcqs[i].qcq, 1594 lif->txqcqs[i].qcq); 1595 1596 lif->rxqcqs[i].qcq->stats = lif->rxqcqs[i].stats; 1597 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i].qcq); 1598 } 1599 1600 return 0; 1601 1602 err_out: 1603 ionic_txrx_free(lif); 1604 1605 return err; 1606 } 1607 1608 static int ionic_txrx_init(struct ionic_lif *lif) 1609 { 1610 unsigned int i; 1611 int err; 1612 1613 for (i = 0; i < lif->nxqs; i++) { 1614 err = ionic_lif_txq_init(lif, lif->txqcqs[i].qcq); 1615 if (err) 1616 goto err_out; 1617 1618 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i].qcq); 1619 if (err) { 1620 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1621 goto err_out; 1622 } 1623 } 1624 1625 if (lif->netdev->features & NETIF_F_RXHASH) 1626 ionic_lif_rss_init(lif); 1627 1628 ionic_set_rx_mode(lif->netdev); 1629 1630 return 0; 1631 1632 err_out: 1633 while (i--) { 1634 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1635 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq); 1636 } 1637 1638 return err; 1639 } 1640 1641 static int ionic_txrx_enable(struct ionic_lif *lif) 1642 { 1643 int i, err; 1644 1645 for (i = 0; i < lif->nxqs; i++) { 1646 ionic_rx_fill(&lif->rxqcqs[i].qcq->q); 1647 err = ionic_qcq_enable(lif->rxqcqs[i].qcq); 1648 if (err) 1649 goto err_out; 1650 1651 err = ionic_qcq_enable(lif->txqcqs[i].qcq); 1652 if (err) { 1653 if (err != -ETIMEDOUT) 1654 ionic_qcq_disable(lif->rxqcqs[i].qcq); 1655 goto err_out; 1656 } 1657 } 1658 1659 return 0; 1660 1661 err_out: 1662 while (i--) { 1663 err = ionic_qcq_disable(lif->txqcqs[i].qcq); 1664 if (err == -ETIMEDOUT) 1665 break; 1666 err = ionic_qcq_disable(lif->rxqcqs[i].qcq); 1667 if (err == -ETIMEDOUT) 1668 break; 1669 } 1670 1671 return err; 1672 } 1673 1674 static int ionic_start_queues(struct ionic_lif *lif) 1675 { 1676 int err; 1677 1678 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 1679 return 0; 1680 1681 err = ionic_txrx_enable(lif); 1682 if (err) { 1683 clear_bit(IONIC_LIF_F_UP, lif->state); 1684 return err; 1685 } 1686 netif_tx_wake_all_queues(lif->netdev); 1687 1688 return 0; 1689 } 1690 1691 int ionic_open(struct net_device *netdev) 1692 { 1693 struct ionic_lif *lif = netdev_priv(netdev); 1694 int err; 1695 1696 err = ionic_txrx_alloc(lif); 1697 if (err) 1698 return err; 1699 1700 err = ionic_txrx_init(lif); 1701 if (err) 1702 goto err_out; 1703 1704 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 1705 if (err) 1706 goto err_txrx_deinit; 1707 1708 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 1709 if (err) 1710 goto err_txrx_deinit; 1711 1712 /* don't start the queues until we have link */ 1713 if (netif_carrier_ok(netdev)) { 1714 err = ionic_start_queues(lif); 1715 if (err) 1716 goto err_txrx_deinit; 1717 } 1718 1719 return 0; 1720 1721 err_txrx_deinit: 1722 ionic_txrx_deinit(lif); 1723 err_out: 1724 ionic_txrx_free(lif); 1725 return err; 1726 } 1727 1728 static void ionic_stop_queues(struct ionic_lif *lif) 1729 { 1730 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 1731 return; 1732 1733 netif_tx_disable(lif->netdev); 1734 ionic_txrx_disable(lif); 1735 } 1736 1737 int ionic_stop(struct net_device *netdev) 1738 { 1739 struct ionic_lif *lif = netdev_priv(netdev); 1740 1741 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1742 return 0; 1743 1744 ionic_stop_queues(lif); 1745 ionic_txrx_deinit(lif); 1746 ionic_txrx_free(lif); 1747 1748 return 0; 1749 } 1750 1751 static int ionic_get_vf_config(struct net_device *netdev, 1752 int vf, struct ifla_vf_info *ivf) 1753 { 1754 struct ionic_lif *lif = netdev_priv(netdev); 1755 struct ionic *ionic = lif->ionic; 1756 int ret = 0; 1757 1758 if (!netif_device_present(netdev)) 1759 return -EBUSY; 1760 1761 down_read(&ionic->vf_op_lock); 1762 1763 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1764 ret = -EINVAL; 1765 } else { 1766 ivf->vf = vf; 1767 ivf->vlan = ionic->vfs[vf].vlanid; 1768 ivf->qos = 0; 1769 ivf->spoofchk = ionic->vfs[vf].spoofchk; 1770 ivf->linkstate = ionic->vfs[vf].linkstate; 1771 ivf->max_tx_rate = ionic->vfs[vf].maxrate; 1772 ivf->trusted = ionic->vfs[vf].trusted; 1773 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 1774 } 1775 1776 up_read(&ionic->vf_op_lock); 1777 return ret; 1778 } 1779 1780 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 1781 struct ifla_vf_stats *vf_stats) 1782 { 1783 struct ionic_lif *lif = netdev_priv(netdev); 1784 struct ionic *ionic = lif->ionic; 1785 struct ionic_lif_stats *vs; 1786 int ret = 0; 1787 1788 if (!netif_device_present(netdev)) 1789 return -EBUSY; 1790 1791 down_read(&ionic->vf_op_lock); 1792 1793 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1794 ret = -EINVAL; 1795 } else { 1796 memset(vf_stats, 0, sizeof(*vf_stats)); 1797 vs = &ionic->vfs[vf].stats; 1798 1799 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 1800 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 1801 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 1802 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 1803 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 1804 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 1805 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 1806 le64_to_cpu(vs->rx_mcast_drop_packets) + 1807 le64_to_cpu(vs->rx_bcast_drop_packets); 1808 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 1809 le64_to_cpu(vs->tx_mcast_drop_packets) + 1810 le64_to_cpu(vs->tx_bcast_drop_packets); 1811 } 1812 1813 up_read(&ionic->vf_op_lock); 1814 return ret; 1815 } 1816 1817 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 1818 { 1819 struct ionic_lif *lif = netdev_priv(netdev); 1820 struct ionic *ionic = lif->ionic; 1821 int ret; 1822 1823 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 1824 return -EINVAL; 1825 1826 if (!netif_device_present(netdev)) 1827 return -EBUSY; 1828 1829 down_write(&ionic->vf_op_lock); 1830 1831 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1832 ret = -EINVAL; 1833 } else { 1834 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 1835 if (!ret) 1836 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 1837 } 1838 1839 up_write(&ionic->vf_op_lock); 1840 return ret; 1841 } 1842 1843 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1844 u8 qos, __be16 proto) 1845 { 1846 struct ionic_lif *lif = netdev_priv(netdev); 1847 struct ionic *ionic = lif->ionic; 1848 int ret; 1849 1850 /* until someday when we support qos */ 1851 if (qos) 1852 return -EINVAL; 1853 1854 if (vlan > 4095) 1855 return -EINVAL; 1856 1857 if (proto != htons(ETH_P_8021Q)) 1858 return -EPROTONOSUPPORT; 1859 1860 if (!netif_device_present(netdev)) 1861 return -EBUSY; 1862 1863 down_write(&ionic->vf_op_lock); 1864 1865 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1866 ret = -EINVAL; 1867 } else { 1868 ret = ionic_set_vf_config(ionic, vf, 1869 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 1870 if (!ret) 1871 ionic->vfs[vf].vlanid = vlan; 1872 } 1873 1874 up_write(&ionic->vf_op_lock); 1875 return ret; 1876 } 1877 1878 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 1879 int tx_min, int tx_max) 1880 { 1881 struct ionic_lif *lif = netdev_priv(netdev); 1882 struct ionic *ionic = lif->ionic; 1883 int ret; 1884 1885 /* setting the min just seems silly */ 1886 if (tx_min) 1887 return -EINVAL; 1888 1889 if (!netif_device_present(netdev)) 1890 return -EBUSY; 1891 1892 down_write(&ionic->vf_op_lock); 1893 1894 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1895 ret = -EINVAL; 1896 } else { 1897 ret = ionic_set_vf_config(ionic, vf, 1898 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 1899 if (!ret) 1900 lif->ionic->vfs[vf].maxrate = tx_max; 1901 } 1902 1903 up_write(&ionic->vf_op_lock); 1904 return ret; 1905 } 1906 1907 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 1908 { 1909 struct ionic_lif *lif = netdev_priv(netdev); 1910 struct ionic *ionic = lif->ionic; 1911 u8 data = set; /* convert to u8 for config */ 1912 int ret; 1913 1914 if (!netif_device_present(netdev)) 1915 return -EBUSY; 1916 1917 down_write(&ionic->vf_op_lock); 1918 1919 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1920 ret = -EINVAL; 1921 } else { 1922 ret = ionic_set_vf_config(ionic, vf, 1923 IONIC_VF_ATTR_SPOOFCHK, &data); 1924 if (!ret) 1925 ionic->vfs[vf].spoofchk = data; 1926 } 1927 1928 up_write(&ionic->vf_op_lock); 1929 return ret; 1930 } 1931 1932 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 1933 { 1934 struct ionic_lif *lif = netdev_priv(netdev); 1935 struct ionic *ionic = lif->ionic; 1936 u8 data = set; /* convert to u8 for config */ 1937 int ret; 1938 1939 if (!netif_device_present(netdev)) 1940 return -EBUSY; 1941 1942 down_write(&ionic->vf_op_lock); 1943 1944 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1945 ret = -EINVAL; 1946 } else { 1947 ret = ionic_set_vf_config(ionic, vf, 1948 IONIC_VF_ATTR_TRUST, &data); 1949 if (!ret) 1950 ionic->vfs[vf].trusted = data; 1951 } 1952 1953 up_write(&ionic->vf_op_lock); 1954 return ret; 1955 } 1956 1957 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 1958 { 1959 struct ionic_lif *lif = netdev_priv(netdev); 1960 struct ionic *ionic = lif->ionic; 1961 u8 data; 1962 int ret; 1963 1964 switch (set) { 1965 case IFLA_VF_LINK_STATE_ENABLE: 1966 data = IONIC_VF_LINK_STATUS_UP; 1967 break; 1968 case IFLA_VF_LINK_STATE_DISABLE: 1969 data = IONIC_VF_LINK_STATUS_DOWN; 1970 break; 1971 case IFLA_VF_LINK_STATE_AUTO: 1972 data = IONIC_VF_LINK_STATUS_AUTO; 1973 break; 1974 default: 1975 return -EINVAL; 1976 } 1977 1978 if (!netif_device_present(netdev)) 1979 return -EBUSY; 1980 1981 down_write(&ionic->vf_op_lock); 1982 1983 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1984 ret = -EINVAL; 1985 } else { 1986 ret = ionic_set_vf_config(ionic, vf, 1987 IONIC_VF_ATTR_LINKSTATE, &data); 1988 if (!ret) 1989 ionic->vfs[vf].linkstate = set; 1990 } 1991 1992 up_write(&ionic->vf_op_lock); 1993 return ret; 1994 } 1995 1996 static const struct net_device_ops ionic_netdev_ops = { 1997 .ndo_open = ionic_open, 1998 .ndo_stop = ionic_stop, 1999 .ndo_start_xmit = ionic_start_xmit, 2000 .ndo_get_stats64 = ionic_get_stats64, 2001 .ndo_set_rx_mode = ionic_set_rx_mode, 2002 .ndo_set_features = ionic_set_features, 2003 .ndo_set_mac_address = ionic_set_mac_address, 2004 .ndo_validate_addr = eth_validate_addr, 2005 .ndo_tx_timeout = ionic_tx_timeout, 2006 .ndo_change_mtu = ionic_change_mtu, 2007 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2008 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2009 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2010 .ndo_set_vf_trust = ionic_set_vf_trust, 2011 .ndo_set_vf_mac = ionic_set_vf_mac, 2012 .ndo_set_vf_rate = ionic_set_vf_rate, 2013 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2014 .ndo_get_vf_config = ionic_get_vf_config, 2015 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2016 .ndo_get_vf_stats = ionic_get_vf_stats, 2017 }; 2018 2019 int ionic_reset_queues(struct ionic_lif *lif, ionic_reset_cb cb, void *arg) 2020 { 2021 bool running; 2022 int err = 0; 2023 2024 mutex_lock(&lif->queue_lock); 2025 running = netif_running(lif->netdev); 2026 if (running) { 2027 netif_device_detach(lif->netdev); 2028 err = ionic_stop(lif->netdev); 2029 if (err) 2030 goto reset_out; 2031 } 2032 2033 if (cb) 2034 cb(lif, arg); 2035 2036 if (running) { 2037 err = ionic_open(lif->netdev); 2038 netif_device_attach(lif->netdev); 2039 } 2040 2041 reset_out: 2042 mutex_unlock(&lif->queue_lock); 2043 2044 return err; 2045 } 2046 2047 static struct ionic_lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index) 2048 { 2049 struct device *dev = ionic->dev; 2050 union ionic_lif_identity *lid; 2051 struct net_device *netdev; 2052 struct ionic_lif *lif; 2053 int tbl_sz; 2054 int err; 2055 2056 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2057 if (!lid) 2058 return ERR_PTR(-ENOMEM); 2059 2060 netdev = alloc_etherdev_mqs(sizeof(*lif), 2061 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2062 if (!netdev) { 2063 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2064 err = -ENOMEM; 2065 goto err_out_free_lid; 2066 } 2067 2068 SET_NETDEV_DEV(netdev, dev); 2069 2070 lif = netdev_priv(netdev); 2071 lif->netdev = netdev; 2072 ionic->master_lif = lif; 2073 netdev->netdev_ops = &ionic_netdev_ops; 2074 ionic_ethtool_set_ops(netdev); 2075 2076 netdev->watchdog_timeo = 2 * HZ; 2077 netif_carrier_off(netdev); 2078 2079 lif->identity = lid; 2080 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2081 ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2082 lif->netdev->min_mtu = le32_to_cpu(lif->identity->eth.min_frame_size); 2083 lif->netdev->max_mtu = 2084 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2085 2086 lif->neqs = ionic->neqs_per_lif; 2087 lif->nxqs = ionic->ntxqs_per_lif; 2088 2089 lif->ionic = ionic; 2090 lif->index = index; 2091 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2092 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2093 lif->tx_budget = IONIC_TX_BUDGET_DEFAULT; 2094 2095 /* Convert the default coalesce value to actual hw resolution */ 2096 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2097 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2098 lif->rx_coalesce_usecs); 2099 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2100 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2101 2102 snprintf(lif->name, sizeof(lif->name), "lif%u", index); 2103 2104 spin_lock_init(&lif->adminq_lock); 2105 2106 spin_lock_init(&lif->deferred.lock); 2107 INIT_LIST_HEAD(&lif->deferred.list); 2108 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2109 2110 /* allocate lif info */ 2111 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2112 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2113 &lif->info_pa, GFP_KERNEL); 2114 if (!lif->info) { 2115 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2116 err = -ENOMEM; 2117 goto err_out_free_netdev; 2118 } 2119 2120 ionic_debugfs_add_lif(lif); 2121 2122 /* allocate queues */ 2123 err = ionic_qcqs_alloc(lif); 2124 if (err) 2125 goto err_out_free_lif_info; 2126 2127 /* allocate rss indirection table */ 2128 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2129 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2130 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2131 &lif->rss_ind_tbl_pa, 2132 GFP_KERNEL); 2133 2134 if (!lif->rss_ind_tbl) { 2135 err = -ENOMEM; 2136 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2137 goto err_out_free_qcqs; 2138 } 2139 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2140 2141 list_add_tail(&lif->list, &ionic->lifs); 2142 2143 return lif; 2144 2145 err_out_free_qcqs: 2146 ionic_qcqs_free(lif); 2147 err_out_free_lif_info: 2148 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2149 lif->info = NULL; 2150 lif->info_pa = 0; 2151 err_out_free_netdev: 2152 free_netdev(lif->netdev); 2153 lif = NULL; 2154 err_out_free_lid: 2155 kfree(lid); 2156 2157 return ERR_PTR(err); 2158 } 2159 2160 int ionic_lifs_alloc(struct ionic *ionic) 2161 { 2162 struct ionic_lif *lif; 2163 2164 INIT_LIST_HEAD(&ionic->lifs); 2165 2166 /* only build the first lif, others are for later features */ 2167 set_bit(0, ionic->lifbits); 2168 2169 lif = ionic_lif_alloc(ionic, 0); 2170 if (IS_ERR_OR_NULL(lif)) { 2171 clear_bit(0, ionic->lifbits); 2172 return -ENOMEM; 2173 } 2174 2175 ionic_lif_queue_identify(lif); 2176 2177 return 0; 2178 } 2179 2180 static void ionic_lif_reset(struct ionic_lif *lif) 2181 { 2182 struct ionic_dev *idev = &lif->ionic->idev; 2183 2184 mutex_lock(&lif->ionic->dev_cmd_lock); 2185 ionic_dev_cmd_lif_reset(idev, lif->index); 2186 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2187 mutex_unlock(&lif->ionic->dev_cmd_lock); 2188 } 2189 2190 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2191 { 2192 struct ionic *ionic = lif->ionic; 2193 2194 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2195 return; 2196 2197 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2198 2199 netif_device_detach(lif->netdev); 2200 2201 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2202 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2203 mutex_lock(&lif->queue_lock); 2204 ionic_stop_queues(lif); 2205 mutex_unlock(&lif->queue_lock); 2206 } 2207 2208 if (netif_running(lif->netdev)) { 2209 ionic_txrx_deinit(lif); 2210 ionic_txrx_free(lif); 2211 } 2212 ionic_lifs_deinit(ionic); 2213 ionic_reset(ionic); 2214 ionic_qcqs_free(lif); 2215 2216 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2217 } 2218 2219 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2220 { 2221 struct ionic *ionic = lif->ionic; 2222 int err; 2223 2224 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2225 return; 2226 2227 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2228 2229 ionic_init_devinfo(ionic); 2230 ionic_port_init(ionic); 2231 err = ionic_qcqs_alloc(lif); 2232 if (err) 2233 goto err_out; 2234 2235 err = ionic_lifs_init(ionic); 2236 if (err) 2237 goto err_qcqs_free; 2238 2239 if (lif->registered) 2240 ionic_lif_set_netdev_info(lif); 2241 2242 ionic_rx_filter_replay(lif); 2243 2244 if (netif_running(lif->netdev)) { 2245 err = ionic_txrx_alloc(lif); 2246 if (err) 2247 goto err_lifs_deinit; 2248 2249 err = ionic_txrx_init(lif); 2250 if (err) 2251 goto err_txrx_free; 2252 } 2253 2254 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2255 ionic_link_status_check_request(lif); 2256 netif_device_attach(lif->netdev); 2257 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2258 2259 return; 2260 2261 err_txrx_free: 2262 ionic_txrx_free(lif); 2263 err_lifs_deinit: 2264 ionic_lifs_deinit(ionic); 2265 err_qcqs_free: 2266 ionic_qcqs_free(lif); 2267 err_out: 2268 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2269 } 2270 2271 static void ionic_lif_free(struct ionic_lif *lif) 2272 { 2273 struct device *dev = lif->ionic->dev; 2274 2275 /* free rss indirection table */ 2276 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2277 lif->rss_ind_tbl_pa); 2278 lif->rss_ind_tbl = NULL; 2279 lif->rss_ind_tbl_pa = 0; 2280 2281 /* free queues */ 2282 ionic_qcqs_free(lif); 2283 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2284 ionic_lif_reset(lif); 2285 2286 /* free lif info */ 2287 kfree(lif->identity); 2288 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2289 lif->info = NULL; 2290 lif->info_pa = 0; 2291 2292 /* unmap doorbell page */ 2293 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2294 lif->kern_dbpage = NULL; 2295 kfree(lif->dbid_inuse); 2296 lif->dbid_inuse = NULL; 2297 2298 /* free netdev & lif */ 2299 ionic_debugfs_del_lif(lif); 2300 list_del(&lif->list); 2301 free_netdev(lif->netdev); 2302 } 2303 2304 void ionic_lifs_free(struct ionic *ionic) 2305 { 2306 struct list_head *cur, *tmp; 2307 struct ionic_lif *lif; 2308 2309 list_for_each_safe(cur, tmp, &ionic->lifs) { 2310 lif = list_entry(cur, struct ionic_lif, list); 2311 2312 ionic_lif_free(lif); 2313 } 2314 } 2315 2316 static void ionic_lif_deinit(struct ionic_lif *lif) 2317 { 2318 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2319 return; 2320 2321 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2322 cancel_work_sync(&lif->deferred.work); 2323 cancel_work_sync(&lif->tx_timeout_work); 2324 ionic_rx_filters_deinit(lif); 2325 if (lif->netdev->features & NETIF_F_RXHASH) 2326 ionic_lif_rss_deinit(lif); 2327 } 2328 2329 napi_disable(&lif->adminqcq->napi); 2330 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2331 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2332 2333 mutex_destroy(&lif->queue_lock); 2334 ionic_lif_reset(lif); 2335 } 2336 2337 void ionic_lifs_deinit(struct ionic *ionic) 2338 { 2339 struct list_head *cur, *tmp; 2340 struct ionic_lif *lif; 2341 2342 list_for_each_safe(cur, tmp, &ionic->lifs) { 2343 lif = list_entry(cur, struct ionic_lif, list); 2344 ionic_lif_deinit(lif); 2345 } 2346 } 2347 2348 static int ionic_lif_adminq_init(struct ionic_lif *lif) 2349 { 2350 struct device *dev = lif->ionic->dev; 2351 struct ionic_q_init_comp comp; 2352 struct ionic_dev *idev; 2353 struct ionic_qcq *qcq; 2354 struct ionic_queue *q; 2355 int err; 2356 2357 idev = &lif->ionic->idev; 2358 qcq = lif->adminqcq; 2359 q = &qcq->q; 2360 2361 mutex_lock(&lif->ionic->dev_cmd_lock); 2362 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2363 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2364 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2365 mutex_unlock(&lif->ionic->dev_cmd_lock); 2366 if (err) { 2367 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2368 return err; 2369 } 2370 2371 q->hw_type = comp.hw_type; 2372 q->hw_index = le32_to_cpu(comp.hw_index); 2373 q->dbval = IONIC_DBELL_QID(q->hw_index); 2374 2375 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2376 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2377 2378 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2379 NAPI_POLL_WEIGHT); 2380 2381 napi_enable(&qcq->napi); 2382 2383 if (qcq->flags & IONIC_QCQ_F_INTR) 2384 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 2385 IONIC_INTR_MASK_CLEAR); 2386 2387 qcq->flags |= IONIC_QCQ_F_INITED; 2388 2389 return 0; 2390 } 2391 2392 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 2393 { 2394 struct ionic_qcq *qcq = lif->notifyqcq; 2395 struct device *dev = lif->ionic->dev; 2396 struct ionic_queue *q = &qcq->q; 2397 int err; 2398 2399 struct ionic_admin_ctx ctx = { 2400 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2401 .cmd.q_init = { 2402 .opcode = IONIC_CMD_Q_INIT, 2403 .lif_index = cpu_to_le16(lif->index), 2404 .type = q->type, 2405 .ver = lif->qtype_info[q->type].version, 2406 .index = cpu_to_le32(q->index), 2407 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 2408 IONIC_QINIT_F_ENA), 2409 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 2410 .pid = cpu_to_le16(q->pid), 2411 .ring_size = ilog2(q->num_descs), 2412 .ring_base = cpu_to_le64(q->base_pa), 2413 } 2414 }; 2415 2416 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 2417 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 2418 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 2419 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 2420 2421 err = ionic_adminq_post_wait(lif, &ctx); 2422 if (err) 2423 return err; 2424 2425 lif->last_eid = 0; 2426 q->hw_type = ctx.comp.q_init.hw_type; 2427 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 2428 q->dbval = IONIC_DBELL_QID(q->hw_index); 2429 2430 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 2431 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 2432 2433 /* preset the callback info */ 2434 q->info[0].cb_arg = lif; 2435 2436 qcq->flags |= IONIC_QCQ_F_INITED; 2437 2438 return 0; 2439 } 2440 2441 static int ionic_station_set(struct ionic_lif *lif) 2442 { 2443 struct net_device *netdev = lif->netdev; 2444 struct ionic_admin_ctx ctx = { 2445 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2446 .cmd.lif_getattr = { 2447 .opcode = IONIC_CMD_LIF_GETATTR, 2448 .index = cpu_to_le16(lif->index), 2449 .attr = IONIC_LIF_ATTR_MAC, 2450 }, 2451 }; 2452 struct sockaddr addr; 2453 int err; 2454 2455 err = ionic_adminq_post_wait(lif, &ctx); 2456 if (err) 2457 return err; 2458 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 2459 ctx.comp.lif_getattr.mac); 2460 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 2461 return 0; 2462 2463 if (!is_zero_ether_addr(netdev->dev_addr)) { 2464 /* If the netdev mac is non-zero and doesn't match the default 2465 * device address, it was set by something earlier and we're 2466 * likely here again after a fw-upgrade reset. We need to be 2467 * sure the netdev mac is in our filter list. 2468 */ 2469 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 2470 netdev->dev_addr)) 2471 ionic_lif_addr(lif, netdev->dev_addr, true); 2472 } else { 2473 /* Update the netdev mac with the device's mac */ 2474 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 2475 addr.sa_family = AF_INET; 2476 err = eth_prepare_mac_addr_change(netdev, &addr); 2477 if (err) { 2478 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 2479 addr.sa_data, err); 2480 return 0; 2481 } 2482 2483 eth_commit_mac_addr_change(netdev, &addr); 2484 } 2485 2486 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 2487 netdev->dev_addr); 2488 ionic_lif_addr(lif, netdev->dev_addr, true); 2489 2490 return 0; 2491 } 2492 2493 static int ionic_lif_init(struct ionic_lif *lif) 2494 { 2495 struct ionic_dev *idev = &lif->ionic->idev; 2496 struct device *dev = lif->ionic->dev; 2497 struct ionic_lif_init_comp comp; 2498 int dbpage_num; 2499 int err; 2500 2501 mutex_lock(&lif->ionic->dev_cmd_lock); 2502 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 2503 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2504 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2505 mutex_unlock(&lif->ionic->dev_cmd_lock); 2506 if (err) 2507 return err; 2508 2509 lif->hw_index = le16_to_cpu(comp.hw_index); 2510 mutex_init(&lif->queue_lock); 2511 2512 /* now that we have the hw_index we can figure out our doorbell page */ 2513 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 2514 if (!lif->dbid_count) { 2515 dev_err(dev, "No doorbell pages, aborting\n"); 2516 return -EINVAL; 2517 } 2518 2519 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 2520 if (!lif->dbid_inuse) { 2521 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 2522 return -ENOMEM; 2523 } 2524 2525 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 2526 set_bit(0, lif->dbid_inuse); 2527 lif->kern_pid = 0; 2528 2529 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 2530 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 2531 if (!lif->kern_dbpage) { 2532 dev_err(dev, "Cannot map dbpage, aborting\n"); 2533 err = -ENOMEM; 2534 goto err_out_free_dbid; 2535 } 2536 2537 err = ionic_lif_adminq_init(lif); 2538 if (err) 2539 goto err_out_adminq_deinit; 2540 2541 if (lif->ionic->nnqs_per_lif) { 2542 err = ionic_lif_notifyq_init(lif); 2543 if (err) 2544 goto err_out_notifyq_deinit; 2545 } 2546 2547 err = ionic_init_nic_features(lif); 2548 if (err) 2549 goto err_out_notifyq_deinit; 2550 2551 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2552 err = ionic_rx_filters_init(lif); 2553 if (err) 2554 goto err_out_notifyq_deinit; 2555 } 2556 2557 err = ionic_station_set(lif); 2558 if (err) 2559 goto err_out_notifyq_deinit; 2560 2561 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 2562 2563 set_bit(IONIC_LIF_F_INITED, lif->state); 2564 2565 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 2566 2567 return 0; 2568 2569 err_out_notifyq_deinit: 2570 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2571 err_out_adminq_deinit: 2572 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2573 ionic_lif_reset(lif); 2574 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2575 lif->kern_dbpage = NULL; 2576 err_out_free_dbid: 2577 kfree(lif->dbid_inuse); 2578 lif->dbid_inuse = NULL; 2579 2580 return err; 2581 } 2582 2583 int ionic_lifs_init(struct ionic *ionic) 2584 { 2585 struct list_head *cur, *tmp; 2586 struct ionic_lif *lif; 2587 int err; 2588 2589 list_for_each_safe(cur, tmp, &ionic->lifs) { 2590 lif = list_entry(cur, struct ionic_lif, list); 2591 err = ionic_lif_init(lif); 2592 if (err) 2593 return err; 2594 } 2595 2596 return 0; 2597 } 2598 2599 static void ionic_lif_notify_work(struct work_struct *ws) 2600 { 2601 } 2602 2603 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 2604 { 2605 struct ionic_admin_ctx ctx = { 2606 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2607 .cmd.lif_setattr = { 2608 .opcode = IONIC_CMD_LIF_SETATTR, 2609 .index = cpu_to_le16(lif->index), 2610 .attr = IONIC_LIF_ATTR_NAME, 2611 }, 2612 }; 2613 2614 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 2615 sizeof(ctx.cmd.lif_setattr.name)); 2616 2617 ionic_adminq_post_wait(lif, &ctx); 2618 } 2619 2620 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 2621 { 2622 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 2623 return NULL; 2624 2625 return netdev_priv(netdev); 2626 } 2627 2628 static int ionic_lif_notify(struct notifier_block *nb, 2629 unsigned long event, void *info) 2630 { 2631 struct net_device *ndev = netdev_notifier_info_to_dev(info); 2632 struct ionic *ionic = container_of(nb, struct ionic, nb); 2633 struct ionic_lif *lif = ionic_netdev_lif(ndev); 2634 2635 if (!lif || lif->ionic != ionic) 2636 return NOTIFY_DONE; 2637 2638 switch (event) { 2639 case NETDEV_CHANGENAME: 2640 ionic_lif_set_netdev_info(lif); 2641 break; 2642 } 2643 2644 return NOTIFY_DONE; 2645 } 2646 2647 int ionic_lifs_register(struct ionic *ionic) 2648 { 2649 int err; 2650 2651 INIT_WORK(&ionic->nb_work, ionic_lif_notify_work); 2652 2653 ionic->nb.notifier_call = ionic_lif_notify; 2654 2655 err = register_netdevice_notifier(&ionic->nb); 2656 if (err) 2657 ionic->nb.notifier_call = NULL; 2658 2659 /* only register LIF0 for now */ 2660 err = register_netdev(ionic->master_lif->netdev); 2661 if (err) { 2662 dev_err(ionic->dev, "Cannot register net device, aborting\n"); 2663 return err; 2664 } 2665 ionic->master_lif->registered = true; 2666 ionic_lif_set_netdev_info(ionic->master_lif); 2667 2668 return 0; 2669 } 2670 2671 void ionic_lifs_unregister(struct ionic *ionic) 2672 { 2673 if (ionic->nb.notifier_call) { 2674 unregister_netdevice_notifier(&ionic->nb); 2675 cancel_work_sync(&ionic->nb_work); 2676 ionic->nb.notifier_call = NULL; 2677 } 2678 2679 /* There is only one lif ever registered in the 2680 * current model, so don't bother searching the 2681 * ionic->lif for candidates to unregister 2682 */ 2683 if (ionic->master_lif && 2684 ionic->master_lif->netdev->reg_state == NETREG_REGISTERED) 2685 unregister_netdev(ionic->master_lif->netdev); 2686 } 2687 2688 static void ionic_lif_queue_identify(struct ionic_lif *lif) 2689 { 2690 struct ionic *ionic = lif->ionic; 2691 union ionic_q_identity *q_ident; 2692 struct ionic_dev *idev; 2693 int qtype; 2694 int err; 2695 2696 idev = &lif->ionic->idev; 2697 q_ident = (union ionic_q_identity *)&idev->dev_cmd_regs->data; 2698 2699 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 2700 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 2701 2702 /* filter out the ones we know about */ 2703 switch (qtype) { 2704 case IONIC_QTYPE_ADMINQ: 2705 case IONIC_QTYPE_NOTIFYQ: 2706 case IONIC_QTYPE_RXQ: 2707 case IONIC_QTYPE_TXQ: 2708 break; 2709 default: 2710 continue; 2711 } 2712 2713 memset(qti, 0, sizeof(*qti)); 2714 2715 mutex_lock(&ionic->dev_cmd_lock); 2716 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 2717 ionic_qtype_versions[qtype]); 2718 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2719 if (!err) { 2720 qti->version = q_ident->version; 2721 qti->supported = q_ident->supported; 2722 qti->features = le64_to_cpu(q_ident->features); 2723 qti->desc_sz = le16_to_cpu(q_ident->desc_sz); 2724 qti->comp_sz = le16_to_cpu(q_ident->comp_sz); 2725 qti->sg_desc_sz = le16_to_cpu(q_ident->sg_desc_sz); 2726 qti->max_sg_elems = le16_to_cpu(q_ident->max_sg_elems); 2727 qti->sg_desc_stride = le16_to_cpu(q_ident->sg_desc_stride); 2728 } 2729 mutex_unlock(&ionic->dev_cmd_lock); 2730 2731 if (err == -EINVAL) { 2732 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 2733 continue; 2734 } else if (err == -EIO) { 2735 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 2736 return; 2737 } else if (err) { 2738 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 2739 qtype, err); 2740 return; 2741 } 2742 2743 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 2744 qtype, qti->version); 2745 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 2746 qtype, qti->supported); 2747 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 2748 qtype, qti->features); 2749 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 2750 qtype, qti->desc_sz); 2751 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 2752 qtype, qti->comp_sz); 2753 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 2754 qtype, qti->sg_desc_sz); 2755 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 2756 qtype, qti->max_sg_elems); 2757 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 2758 qtype, qti->sg_desc_stride); 2759 } 2760 } 2761 2762 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 2763 union ionic_lif_identity *lid) 2764 { 2765 struct ionic_dev *idev = &ionic->idev; 2766 size_t sz; 2767 int err; 2768 2769 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 2770 2771 mutex_lock(&ionic->dev_cmd_lock); 2772 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 2773 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2774 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 2775 mutex_unlock(&ionic->dev_cmd_lock); 2776 if (err) 2777 return (err); 2778 2779 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 2780 le64_to_cpu(lid->capabilities)); 2781 2782 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 2783 le32_to_cpu(lid->eth.max_ucast_filters)); 2784 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 2785 le32_to_cpu(lid->eth.max_mcast_filters)); 2786 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 2787 le64_to_cpu(lid->eth.config.features)); 2788 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 2789 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 2790 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 2791 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 2792 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 2793 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 2794 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 2795 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 2796 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 2797 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 2798 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 2799 le32_to_cpu(lid->eth.config.mtu)); 2800 2801 return 0; 2802 } 2803 2804 int ionic_lifs_size(struct ionic *ionic) 2805 { 2806 struct ionic_identity *ident = &ionic->ident; 2807 unsigned int nintrs, dev_nintrs; 2808 union ionic_lif_config *lc; 2809 unsigned int ntxqs_per_lif; 2810 unsigned int nrxqs_per_lif; 2811 unsigned int neqs_per_lif; 2812 unsigned int nnqs_per_lif; 2813 unsigned int nxqs, neqs; 2814 unsigned int min_intrs; 2815 int err; 2816 2817 lc = &ident->lif.eth.config; 2818 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 2819 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 2820 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 2821 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 2822 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 2823 2824 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 2825 nxqs = min(nxqs, num_online_cpus()); 2826 neqs = min(neqs_per_lif, num_online_cpus()); 2827 2828 try_again: 2829 /* interrupt usage: 2830 * 1 for master lif adminq/notifyq 2831 * 1 for each CPU for master lif TxRx queue pairs 2832 * whatever's left is for RDMA queues 2833 */ 2834 nintrs = 1 + nxqs + neqs; 2835 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 2836 2837 if (nintrs > dev_nintrs) 2838 goto try_fewer; 2839 2840 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 2841 if (err < 0 && err != -ENOSPC) { 2842 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 2843 return err; 2844 } 2845 if (err == -ENOSPC) 2846 goto try_fewer; 2847 2848 if (err != nintrs) { 2849 ionic_bus_free_irq_vectors(ionic); 2850 goto try_fewer; 2851 } 2852 2853 ionic->nnqs_per_lif = nnqs_per_lif; 2854 ionic->neqs_per_lif = neqs; 2855 ionic->ntxqs_per_lif = nxqs; 2856 ionic->nrxqs_per_lif = nxqs; 2857 ionic->nintrs = nintrs; 2858 2859 ionic_debugfs_add_sizes(ionic); 2860 2861 return 0; 2862 2863 try_fewer: 2864 if (nnqs_per_lif > 1) { 2865 nnqs_per_lif >>= 1; 2866 goto try_again; 2867 } 2868 if (neqs > 1) { 2869 neqs >>= 1; 2870 goto try_again; 2871 } 2872 if (nxqs > 1) { 2873 nxqs >>= 1; 2874 goto try_again; 2875 } 2876 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 2877 return -ENOSPC; 2878 } 2879