1 // SPDX-License-Identifier: GPL-2.0-only 2 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ 3 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 4 * 5 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> 6 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> 7 * 8 * Ani Joshi / Jeff Garzik 9 * - Code cleanup 10 * 11 * Michel Danzer <michdaen@iiic.ethz.ch> 12 * - 15/16 bit cleanup 13 * - fix panning 14 * 15 * Benjamin Herrenschmidt 16 * - pmac-specific PM stuff 17 * - various fixes & cleanups 18 * 19 * Andreas Hundt <andi@convergence.de> 20 * - FB_ACTIVATE fixes 21 * 22 * Paul Mackerras <paulus@samba.org> 23 * - Convert to new framebuffer API, 24 * fix colormap setting at 16 bits/pixel (565) 25 * 26 * Paul Mundt 27 * - PCI hotplug 28 * 29 * Jon Smirl <jonsmirl@yahoo.com> 30 * - PCI ID update 31 * - replace ROM BIOS search 32 * 33 * Based off of Geert's atyfb.c and vfb.c. 34 * 35 * TODO: 36 * - monitor sensing (DDC) 37 * - virtual display 38 * - other platform support (only ppc/x86 supported) 39 * - hardware cursor support 40 * 41 * Please cc: your patches to brad@neruo.com. 42 */ 43 44 /* 45 * A special note of gratitude to ATI's devrel for providing documentation, 46 * example code and hardware. Thanks Nitya. -atong and brad 47 */ 48 49 50 #include <linux/module.h> 51 #include <linux/moduleparam.h> 52 #include <linux/kernel.h> 53 #include <linux/errno.h> 54 #include <linux/string.h> 55 #include <linux/mm.h> 56 #include <linux/vmalloc.h> 57 #include <linux/delay.h> 58 #include <linux/interrupt.h> 59 #include <linux/uaccess.h> 60 #include <linux/fb.h> 61 #include <linux/init.h> 62 #include <linux/pci.h> 63 #include <linux/ioport.h> 64 #include <linux/console.h> 65 #include <linux/backlight.h> 66 #include <asm/io.h> 67 68 #ifdef CONFIG_PPC_PMAC 69 #include <asm/machdep.h> 70 #include <asm/pmac_feature.h> 71 #include <asm/prom.h> 72 #include "../macmodes.h" 73 #endif 74 75 #ifdef CONFIG_PMAC_BACKLIGHT 76 #include <asm/backlight.h> 77 #endif 78 79 #ifdef CONFIG_BOOTX_TEXT 80 #include <asm/btext.h> 81 #endif /* CONFIG_BOOTX_TEXT */ 82 83 #include <video/aty128.h> 84 85 /* Debug flag */ 86 #undef DEBUG 87 88 #ifdef DEBUG 89 #define DBG(fmt, args...) \ 90 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args); 91 #else 92 #define DBG(fmt, args...) 93 #endif 94 95 #ifndef CONFIG_PPC_PMAC 96 /* default mode */ 97 static const struct fb_var_screeninfo default_var = { 98 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 99 640, 480, 640, 480, 0, 0, 8, 0, 100 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 101 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 102 0, FB_VMODE_NONINTERLACED 103 }; 104 105 #else /* CONFIG_PPC_PMAC */ 106 /* default to 1024x768 at 75Hz on PPC - this will work 107 * on the iMac, the usual 640x480 @ 60Hz doesn't. */ 108 static const struct fb_var_screeninfo default_var = { 109 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ 110 1024, 768, 1024, 768, 0, 0, 8, 0, 111 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 112 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, 113 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 114 FB_VMODE_NONINTERLACED 115 }; 116 #endif /* CONFIG_PPC_PMAC */ 117 118 /* default modedb mode */ 119 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ 120 static const struct fb_videomode defaultmode = { 121 .refresh = 60, 122 .xres = 640, 123 .yres = 480, 124 .pixclock = 39722, 125 .left_margin = 48, 126 .right_margin = 16, 127 .upper_margin = 33, 128 .lower_margin = 10, 129 .hsync_len = 96, 130 .vsync_len = 2, 131 .sync = 0, 132 .vmode = FB_VMODE_NONINTERLACED 133 }; 134 135 /* Chip generations */ 136 enum { 137 rage_128, 138 rage_128_pci, 139 rage_128_pro, 140 rage_128_pro_pci, 141 rage_M3, 142 rage_M3_pci, 143 rage_M4, 144 rage_128_ultra, 145 }; 146 147 /* Must match above enum */ 148 static char * const r128_family[] = { 149 "AGP", 150 "PCI", 151 "PRO AGP", 152 "PRO PCI", 153 "M3 AGP", 154 "M3 PCI", 155 "M4 AGP", 156 "Ultra AGP", 157 }; 158 159 /* 160 * PCI driver prototypes 161 */ 162 static int aty128_probe(struct pci_dev *pdev, 163 const struct pci_device_id *ent); 164 static void aty128_remove(struct pci_dev *pdev); 165 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state); 166 static int aty128_pci_resume(struct pci_dev *pdev); 167 static int aty128_do_resume(struct pci_dev *pdev); 168 169 /* supported Rage128 chipsets */ 170 static const struct pci_device_id aty128_pci_tbl[] = { 171 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, 172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, 173 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, 174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, 175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, 198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, 200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, 202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, 204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, 206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, 208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, 210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, 212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, 214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, 216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, 218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, 220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, 222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, 224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, 226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, 228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, 230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, 232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, 234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, 236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, 238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, 240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, 242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, 244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, 246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, 248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, 250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, 252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, 254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, 256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, 258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, 260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, 262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, 264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 265 { 0, } 266 }; 267 268 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); 269 270 static struct pci_driver aty128fb_driver = { 271 .name = "aty128fb", 272 .id_table = aty128_pci_tbl, 273 .probe = aty128_probe, 274 .remove = aty128_remove, 275 .suspend = aty128_pci_suspend, 276 .resume = aty128_pci_resume, 277 }; 278 279 /* packed BIOS settings */ 280 #ifndef CONFIG_PPC 281 typedef struct { 282 u8 clock_chip_type; 283 u8 struct_size; 284 u8 accelerator_entry; 285 u8 VGA_entry; 286 u16 VGA_table_offset; 287 u16 POST_table_offset; 288 u16 XCLK; 289 u16 MCLK; 290 u8 num_PLL_blocks; 291 u8 size_PLL_blocks; 292 u16 PCLK_ref_freq; 293 u16 PCLK_ref_divider; 294 u32 PCLK_min_freq; 295 u32 PCLK_max_freq; 296 u16 MCLK_ref_freq; 297 u16 MCLK_ref_divider; 298 u32 MCLK_min_freq; 299 u32 MCLK_max_freq; 300 u16 XCLK_ref_freq; 301 u16 XCLK_ref_divider; 302 u32 XCLK_min_freq; 303 u32 XCLK_max_freq; 304 } __attribute__ ((packed)) PLL_BLOCK; 305 #endif /* !CONFIG_PPC */ 306 307 /* onboard memory information */ 308 struct aty128_meminfo { 309 u8 ML; 310 u8 MB; 311 u8 Trcd; 312 u8 Trp; 313 u8 Twr; 314 u8 CL; 315 u8 Tr2w; 316 u8 LoopLatency; 317 u8 DspOn; 318 u8 Rloop; 319 const char *name; 320 }; 321 322 /* various memory configurations */ 323 static const struct aty128_meminfo sdr_128 = { 324 .ML = 4, 325 .MB = 4, 326 .Trcd = 3, 327 .Trp = 3, 328 .Twr = 1, 329 .CL = 3, 330 .Tr2w = 1, 331 .LoopLatency = 16, 332 .DspOn = 30, 333 .Rloop = 16, 334 .name = "128-bit SDR SGRAM (1:1)", 335 }; 336 337 static const struct aty128_meminfo sdr_sgram = { 338 .ML = 4, 339 .MB = 4, 340 .Trcd = 1, 341 .Trp = 2, 342 .Twr = 1, 343 .CL = 2, 344 .Tr2w = 1, 345 .LoopLatency = 16, 346 .DspOn = 24, 347 .Rloop = 16, 348 .name = "64-bit SDR SGRAM (2:1)", 349 }; 350 351 static const struct aty128_meminfo ddr_sgram = { 352 .ML = 4, 353 .MB = 4, 354 .Trcd = 3, 355 .Trp = 3, 356 .Twr = 2, 357 .CL = 3, 358 .Tr2w = 1, 359 .LoopLatency = 16, 360 .DspOn = 31, 361 .Rloop = 16, 362 .name = "64-bit DDR SGRAM", 363 }; 364 365 static const struct fb_fix_screeninfo aty128fb_fix = { 366 .id = "ATY Rage128", 367 .type = FB_TYPE_PACKED_PIXELS, 368 .visual = FB_VISUAL_PSEUDOCOLOR, 369 .xpanstep = 8, 370 .ypanstep = 1, 371 .mmio_len = 0x2000, 372 .accel = FB_ACCEL_ATI_RAGE128, 373 }; 374 375 static char *mode_option = NULL; 376 377 #ifdef CONFIG_PPC_PMAC 378 static int default_vmode = VMODE_1024_768_60; 379 static int default_cmode = CMODE_8; 380 #endif 381 382 static int default_crt_on = 0; 383 static int default_lcd_on = 1; 384 static bool mtrr = true; 385 386 #ifdef CONFIG_FB_ATY128_BACKLIGHT 387 #ifdef CONFIG_PMAC_BACKLIGHT 388 static int backlight = 1; 389 #else 390 static int backlight = 0; 391 #endif 392 #endif 393 394 /* PLL constants */ 395 struct aty128_constants { 396 u32 ref_clk; 397 u32 ppll_min; 398 u32 ppll_max; 399 u32 ref_divider; 400 u32 xclk; 401 u32 fifo_width; 402 u32 fifo_depth; 403 }; 404 405 struct aty128_crtc { 406 u32 gen_cntl; 407 u32 h_total, h_sync_strt_wid; 408 u32 v_total, v_sync_strt_wid; 409 u32 pitch; 410 u32 offset, offset_cntl; 411 u32 xoffset, yoffset; 412 u32 vxres, vyres; 413 u32 depth, bpp; 414 }; 415 416 struct aty128_pll { 417 u32 post_divider; 418 u32 feedback_divider; 419 u32 vclk; 420 }; 421 422 struct aty128_ddafifo { 423 u32 dda_config; 424 u32 dda_on_off; 425 }; 426 427 /* register values for a specific mode */ 428 struct aty128fb_par { 429 struct aty128_crtc crtc; 430 struct aty128_pll pll; 431 struct aty128_ddafifo fifo_reg; 432 u32 accel_flags; 433 struct aty128_constants constants; /* PLL and others */ 434 void __iomem *regbase; /* remapped mmio */ 435 u32 vram_size; /* onboard video ram */ 436 int chip_gen; 437 const struct aty128_meminfo *mem; /* onboard mem info */ 438 int wc_cookie; 439 int blitter_may_be_busy; 440 int fifo_slots; /* free slots in FIFO (64 max) */ 441 442 int crt_on, lcd_on; 443 struct pci_dev *pdev; 444 struct fb_info *next; 445 int asleep; 446 int lock_blank; 447 448 u8 red[32]; /* see aty128fb_setcolreg */ 449 u8 green[64]; 450 u8 blue[32]; 451 u32 pseudo_palette[16]; /* used for TRUECOLOR */ 452 }; 453 454 455 #define round_div(n, d) ((n+(d/2))/d) 456 457 static int aty128fb_check_var(struct fb_var_screeninfo *var, 458 struct fb_info *info); 459 static int aty128fb_set_par(struct fb_info *info); 460 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 461 u_int transp, struct fb_info *info); 462 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 463 struct fb_info *fb); 464 static int aty128fb_blank(int blank, struct fb_info *fb); 465 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); 466 static int aty128fb_sync(struct fb_info *info); 467 468 /* 469 * Internal routines 470 */ 471 472 static int aty128_encode_var(struct fb_var_screeninfo *var, 473 const struct aty128fb_par *par); 474 static int aty128_decode_var(struct fb_var_screeninfo *var, 475 struct aty128fb_par *par); 476 static void aty128_timings(struct aty128fb_par *par); 477 static void aty128_init_engine(struct aty128fb_par *par); 478 static void aty128_reset_engine(const struct aty128fb_par *par); 479 static void aty128_flush_pixel_cache(const struct aty128fb_par *par); 480 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); 481 static void wait_for_fifo(u16 entries, struct aty128fb_par *par); 482 static void wait_for_idle(struct aty128fb_par *par); 483 static u32 depth_to_dst(u32 depth); 484 485 #ifdef CONFIG_FB_ATY128_BACKLIGHT 486 static void aty128_bl_set_power(struct fb_info *info, int power); 487 #endif 488 489 #define BIOS_IN8(v) (readb(bios + (v))) 490 #define BIOS_IN16(v) (readb(bios + (v)) | \ 491 (readb(bios + (v) + 1) << 8)) 492 #define BIOS_IN32(v) (readb(bios + (v)) | \ 493 (readb(bios + (v) + 1) << 8) | \ 494 (readb(bios + (v) + 2) << 16) | \ 495 (readb(bios + (v) + 3) << 24)) 496 497 498 static const struct fb_ops aty128fb_ops = { 499 .owner = THIS_MODULE, 500 .fb_check_var = aty128fb_check_var, 501 .fb_set_par = aty128fb_set_par, 502 .fb_setcolreg = aty128fb_setcolreg, 503 .fb_pan_display = aty128fb_pan_display, 504 .fb_blank = aty128fb_blank, 505 .fb_ioctl = aty128fb_ioctl, 506 .fb_sync = aty128fb_sync, 507 .fb_fillrect = cfb_fillrect, 508 .fb_copyarea = cfb_copyarea, 509 .fb_imageblit = cfb_imageblit, 510 }; 511 512 /* 513 * Functions to read from/write to the mmio registers 514 * - endian conversions may possibly be avoided by 515 * using the other register aperture. TODO. 516 */ 517 static inline u32 _aty_ld_le32(volatile unsigned int regindex, 518 const struct aty128fb_par *par) 519 { 520 return readl (par->regbase + regindex); 521 } 522 523 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 524 const struct aty128fb_par *par) 525 { 526 writel (val, par->regbase + regindex); 527 } 528 529 static inline u8 _aty_ld_8(unsigned int regindex, 530 const struct aty128fb_par *par) 531 { 532 return readb (par->regbase + regindex); 533 } 534 535 static inline void _aty_st_8(unsigned int regindex, u8 val, 536 const struct aty128fb_par *par) 537 { 538 writeb (val, par->regbase + regindex); 539 } 540 541 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) 542 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) 543 #define aty_ld_8(regindex) _aty_ld_8(regindex, par) 544 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) 545 546 /* 547 * Functions to read from/write to the pll registers 548 */ 549 550 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) 551 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) 552 553 554 static u32 _aty_ld_pll(unsigned int pll_index, 555 const struct aty128fb_par *par) 556 { 557 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); 558 return aty_ld_le32(CLOCK_CNTL_DATA); 559 } 560 561 562 static void _aty_st_pll(unsigned int pll_index, u32 val, 563 const struct aty128fb_par *par) 564 { 565 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); 566 aty_st_le32(CLOCK_CNTL_DATA, val); 567 } 568 569 570 /* return true when the PLL has completed an atomic update */ 571 static int aty_pll_readupdate(const struct aty128fb_par *par) 572 { 573 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); 574 } 575 576 577 static void aty_pll_wait_readupdate(const struct aty128fb_par *par) 578 { 579 unsigned long timeout = jiffies + HZ/100; // should be more than enough 580 int reset = 1; 581 582 while (time_before(jiffies, timeout)) 583 if (aty_pll_readupdate(par)) { 584 reset = 0; 585 break; 586 } 587 588 if (reset) /* reset engine?? */ 589 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); 590 } 591 592 593 /* tell PLL to update */ 594 static void aty_pll_writeupdate(const struct aty128fb_par *par) 595 { 596 aty_pll_wait_readupdate(par); 597 598 aty_st_pll(PPLL_REF_DIV, 599 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); 600 } 601 602 603 /* write to the scratch register to test r/w functionality */ 604 static int register_test(const struct aty128fb_par *par) 605 { 606 u32 val; 607 int flag = 0; 608 609 val = aty_ld_le32(BIOS_0_SCRATCH); 610 611 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); 612 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { 613 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); 614 615 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) 616 flag = 1; 617 } 618 619 aty_st_le32(BIOS_0_SCRATCH, val); // restore value 620 return flag; 621 } 622 623 624 /* 625 * Accelerator engine functions 626 */ 627 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) 628 { 629 int i; 630 631 for (;;) { 632 for (i = 0; i < 2000000; i++) { 633 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; 634 if (par->fifo_slots >= entries) 635 return; 636 } 637 aty128_reset_engine(par); 638 } 639 } 640 641 642 static void wait_for_idle(struct aty128fb_par *par) 643 { 644 int i; 645 646 do_wait_for_fifo(64, par); 647 648 for (;;) { 649 for (i = 0; i < 2000000; i++) { 650 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { 651 aty128_flush_pixel_cache(par); 652 par->blitter_may_be_busy = 0; 653 return; 654 } 655 } 656 aty128_reset_engine(par); 657 } 658 } 659 660 661 static void wait_for_fifo(u16 entries, struct aty128fb_par *par) 662 { 663 if (par->fifo_slots < entries) 664 do_wait_for_fifo(64, par); 665 par->fifo_slots -= entries; 666 } 667 668 669 static void aty128_flush_pixel_cache(const struct aty128fb_par *par) 670 { 671 int i; 672 u32 tmp; 673 674 tmp = aty_ld_le32(PC_NGUI_CTLSTAT); 675 tmp &= ~(0x00ff); 676 tmp |= 0x00ff; 677 aty_st_le32(PC_NGUI_CTLSTAT, tmp); 678 679 for (i = 0; i < 2000000; i++) 680 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) 681 break; 682 } 683 684 685 static void aty128_reset_engine(const struct aty128fb_par *par) 686 { 687 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; 688 689 aty128_flush_pixel_cache(par); 690 691 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); 692 mclk_cntl = aty_ld_pll(MCLK_CNTL); 693 694 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); 695 696 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); 697 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); 698 aty_ld_le32(GEN_RESET_CNTL); 699 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); 700 aty_ld_le32(GEN_RESET_CNTL); 701 702 aty_st_pll(MCLK_CNTL, mclk_cntl); 703 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); 704 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); 705 706 /* use old pio mode */ 707 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); 708 709 DBG("engine reset"); 710 } 711 712 713 static void aty128_init_engine(struct aty128fb_par *par) 714 { 715 u32 pitch_value; 716 717 wait_for_idle(par); 718 719 /* 3D scaler not spoken here */ 720 wait_for_fifo(1, par); 721 aty_st_le32(SCALE_3D_CNTL, 0x00000000); 722 723 aty128_reset_engine(par); 724 725 pitch_value = par->crtc.pitch; 726 if (par->crtc.bpp == 24) { 727 pitch_value = pitch_value * 3; 728 } 729 730 wait_for_fifo(4, par); 731 /* setup engine offset registers */ 732 aty_st_le32(DEFAULT_OFFSET, 0x00000000); 733 734 /* setup engine pitch registers */ 735 aty_st_le32(DEFAULT_PITCH, pitch_value); 736 737 /* set the default scissor register to max dimensions */ 738 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); 739 740 /* set the drawing controls registers */ 741 aty_st_le32(DP_GUI_MASTER_CNTL, 742 GMC_SRC_PITCH_OFFSET_DEFAULT | 743 GMC_DST_PITCH_OFFSET_DEFAULT | 744 GMC_SRC_CLIP_DEFAULT | 745 GMC_DST_CLIP_DEFAULT | 746 GMC_BRUSH_SOLIDCOLOR | 747 (depth_to_dst(par->crtc.depth) << 8) | 748 GMC_SRC_DSTCOLOR | 749 GMC_BYTE_ORDER_MSB_TO_LSB | 750 GMC_DP_CONVERSION_TEMP_6500 | 751 ROP3_PATCOPY | 752 GMC_DP_SRC_RECT | 753 GMC_3D_FCN_EN_CLR | 754 GMC_DST_CLR_CMP_FCN_CLEAR | 755 GMC_AUX_CLIP_CLEAR | 756 GMC_WRITE_MASK_SET); 757 758 wait_for_fifo(8, par); 759 /* clear the line drawing registers */ 760 aty_st_le32(DST_BRES_ERR, 0); 761 aty_st_le32(DST_BRES_INC, 0); 762 aty_st_le32(DST_BRES_DEC, 0); 763 764 /* set brush color registers */ 765 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ 766 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ 767 768 /* set source color registers */ 769 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ 770 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ 771 772 /* default write mask */ 773 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); 774 775 /* Wait for all the writes to be completed before returning */ 776 wait_for_idle(par); 777 } 778 779 780 /* convert depth values to their register representation */ 781 static u32 depth_to_dst(u32 depth) 782 { 783 if (depth <= 8) 784 return DST_8BPP; 785 else if (depth <= 15) 786 return DST_15BPP; 787 else if (depth == 16) 788 return DST_16BPP; 789 else if (depth <= 24) 790 return DST_24BPP; 791 else if (depth <= 32) 792 return DST_32BPP; 793 794 return -EINVAL; 795 } 796 797 /* 798 * PLL informations retreival 799 */ 800 801 802 #ifndef __sparc__ 803 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par, 804 struct pci_dev *dev) 805 { 806 u16 dptr; 807 u8 rom_type; 808 void __iomem *bios; 809 size_t rom_size; 810 811 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ 812 unsigned int temp; 813 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 814 temp &= 0x00ffffffu; 815 temp |= 0x04 << 24; 816 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); 817 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 818 819 bios = pci_map_rom(dev, &rom_size); 820 821 if (!bios) { 822 printk(KERN_ERR "aty128fb: ROM failed to map\n"); 823 return NULL; 824 } 825 826 /* Very simple test to make sure it appeared */ 827 if (BIOS_IN16(0) != 0xaa55) { 828 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " 829 " be 0xaa55\n", BIOS_IN16(0)); 830 goto failed; 831 } 832 833 /* Look for the PCI data to check the ROM type */ 834 dptr = BIOS_IN16(0x18); 835 836 /* Check the PCI data signature. If it's wrong, we still assume a normal 837 * x86 ROM for now, until I've verified this works everywhere. 838 * The goal here is more to phase out Open Firmware images. 839 * 840 * Currently, we only look at the first PCI data, we could iteratre and 841 * deal with them all, and we should use fb_bios_start relative to start 842 * of image and not relative start of ROM, but so far, I never found a 843 * dual-image ATI card. 844 * 845 * typedef struct { 846 * u32 signature; + 0x00 847 * u16 vendor; + 0x04 848 * u16 device; + 0x06 849 * u16 reserved_1; + 0x08 850 * u16 dlen; + 0x0a 851 * u8 drevision; + 0x0c 852 * u8 class_hi; + 0x0d 853 * u16 class_lo; + 0x0e 854 * u16 ilen; + 0x10 855 * u16 irevision; + 0x12 856 * u8 type; + 0x14 857 * u8 indicator; + 0x15 858 * u16 reserved_2; + 0x16 859 * } pci_data_t; 860 */ 861 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 862 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", 863 BIOS_IN32(dptr)); 864 goto anyway; 865 } 866 rom_type = BIOS_IN8(dptr + 0x14); 867 switch(rom_type) { 868 case 0: 869 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); 870 break; 871 case 1: 872 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); 873 goto failed; 874 case 2: 875 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); 876 goto failed; 877 default: 878 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", 879 rom_type); 880 goto failed; 881 } 882 anyway: 883 return bios; 884 885 failed: 886 pci_unmap_rom(dev, bios); 887 return NULL; 888 } 889 890 static void aty128_get_pllinfo(struct aty128fb_par *par, 891 unsigned char __iomem *bios) 892 { 893 unsigned int bios_hdr; 894 unsigned int bios_pll; 895 896 bios_hdr = BIOS_IN16(0x48); 897 bios_pll = BIOS_IN16(bios_hdr + 0x30); 898 899 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); 900 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); 901 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); 902 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); 903 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); 904 905 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", 906 par->constants.ppll_max, par->constants.ppll_min, 907 par->constants.xclk, par->constants.ref_divider, 908 par->constants.ref_clk); 909 910 } 911 912 #ifdef CONFIG_X86 913 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par) 914 { 915 /* I simplified this code as we used to miss the signatures in 916 * a lot of case. It's now closer to XFree, we just don't check 917 * for signatures at all... Something better will have to be done 918 * if we end up having conflicts 919 */ 920 u32 segstart; 921 unsigned char __iomem *rom_base = NULL; 922 923 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 924 rom_base = ioremap(segstart, 0x10000); 925 if (rom_base == NULL) 926 return NULL; 927 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 928 break; 929 iounmap(rom_base); 930 rom_base = NULL; 931 } 932 return rom_base; 933 } 934 #endif 935 #endif /* ndef(__sparc__) */ 936 937 /* fill in known card constants if pll_block is not available */ 938 static void aty128_timings(struct aty128fb_par *par) 939 { 940 #ifdef CONFIG_PPC 941 /* instead of a table lookup, assume OF has properly 942 * setup the PLL registers and use their values 943 * to set the XCLK values and reference divider values */ 944 945 u32 x_mpll_ref_fb_div; 946 u32 xclk_cntl; 947 u32 Nx, M; 948 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; 949 #endif 950 951 if (!par->constants.ref_clk) 952 par->constants.ref_clk = 2950; 953 954 #ifdef CONFIG_PPC 955 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); 956 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; 957 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; 958 M = x_mpll_ref_fb_div & 0x0000ff; 959 960 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), 961 (M * PostDivSet[xclk_cntl])); 962 963 par->constants.ref_divider = 964 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 965 #endif 966 967 if (!par->constants.ref_divider) { 968 par->constants.ref_divider = 0x3b; 969 970 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); 971 aty_pll_writeupdate(par); 972 } 973 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); 974 aty_pll_writeupdate(par); 975 976 /* from documentation */ 977 if (!par->constants.ppll_min) 978 par->constants.ppll_min = 12500; 979 if (!par->constants.ppll_max) 980 par->constants.ppll_max = 25000; /* 23000 on some cards? */ 981 if (!par->constants.xclk) 982 par->constants.xclk = 0x1d4d; /* same as mclk */ 983 984 par->constants.fifo_width = 128; 985 par->constants.fifo_depth = 32; 986 987 switch (aty_ld_le32(MEM_CNTL) & 0x3) { 988 case 0: 989 par->mem = &sdr_128; 990 break; 991 case 1: 992 par->mem = &sdr_sgram; 993 break; 994 case 2: 995 par->mem = &ddr_sgram; 996 break; 997 default: 998 par->mem = &sdr_sgram; 999 } 1000 } 1001 1002 1003 1004 /* 1005 * CRTC programming 1006 */ 1007 1008 /* Program the CRTC registers */ 1009 static void aty128_set_crtc(const struct aty128_crtc *crtc, 1010 const struct aty128fb_par *par) 1011 { 1012 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); 1013 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); 1014 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1015 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); 1016 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1017 aty_st_le32(CRTC_PITCH, crtc->pitch); 1018 aty_st_le32(CRTC_OFFSET, crtc->offset); 1019 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); 1020 /* Disable ATOMIC updating. Is this the right place? */ 1021 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); 1022 } 1023 1024 1025 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, 1026 struct aty128_crtc *crtc, 1027 const struct aty128fb_par *par) 1028 { 1029 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; 1030 u32 left, right, upper, lower, hslen, vslen, sync, vmode; 1031 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; 1032 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1033 u32 depth, bytpp; 1034 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; 1035 1036 /* input */ 1037 xres = var->xres; 1038 yres = var->yres; 1039 vxres = var->xres_virtual; 1040 vyres = var->yres_virtual; 1041 xoffset = var->xoffset; 1042 yoffset = var->yoffset; 1043 bpp = var->bits_per_pixel; 1044 left = var->left_margin; 1045 right = var->right_margin; 1046 upper = var->upper_margin; 1047 lower = var->lower_margin; 1048 hslen = var->hsync_len; 1049 vslen = var->vsync_len; 1050 sync = var->sync; 1051 vmode = var->vmode; 1052 1053 if (bpp != 16) 1054 depth = bpp; 1055 else 1056 depth = (var->green.length == 6) ? 16 : 15; 1057 1058 /* check for mode eligibility 1059 * accept only non interlaced modes */ 1060 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 1061 return -EINVAL; 1062 1063 /* convert (and round up) and validate */ 1064 xres = (xres + 7) & ~7; 1065 xoffset = (xoffset + 7) & ~7; 1066 1067 if (vxres < xres + xoffset) 1068 vxres = xres + xoffset; 1069 1070 if (vyres < yres + yoffset) 1071 vyres = yres + yoffset; 1072 1073 /* convert depth into ATI register depth */ 1074 dst = depth_to_dst(depth); 1075 1076 if (dst == -EINVAL) { 1077 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); 1078 return -EINVAL; 1079 } 1080 1081 /* convert register depth to bytes per pixel */ 1082 bytpp = mode_bytpp[dst]; 1083 1084 /* make sure there is enough video ram for the mode */ 1085 if ((u32)(vxres * vyres * bytpp) > par->vram_size) { 1086 printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); 1087 return -EINVAL; 1088 } 1089 1090 h_disp = (xres >> 3) - 1; 1091 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; 1092 1093 v_disp = yres - 1; 1094 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; 1095 1096 /* check to make sure h_total and v_total are in range */ 1097 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { 1098 printk(KERN_ERR "aty128fb: invalid width ranges\n"); 1099 return -EINVAL; 1100 } 1101 1102 h_sync_wid = (hslen + 7) >> 3; 1103 if (h_sync_wid == 0) 1104 h_sync_wid = 1; 1105 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ 1106 h_sync_wid = 0x3f; 1107 1108 h_sync_strt = (h_disp << 3) + right; 1109 1110 v_sync_wid = vslen; 1111 if (v_sync_wid == 0) 1112 v_sync_wid = 1; 1113 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ 1114 v_sync_wid = 0x1f; 1115 1116 v_sync_strt = v_disp + lower; 1117 1118 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1119 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1120 1121 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1122 1123 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); 1124 1125 crtc->h_total = h_total | (h_disp << 16); 1126 crtc->v_total = v_total | (v_disp << 16); 1127 1128 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | 1129 (h_sync_pol << 23); 1130 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | 1131 (v_sync_pol << 23); 1132 1133 crtc->pitch = vxres >> 3; 1134 1135 crtc->offset = 0; 1136 1137 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 1138 crtc->offset_cntl = 0x00010000; 1139 else 1140 crtc->offset_cntl = 0; 1141 1142 crtc->vxres = vxres; 1143 crtc->vyres = vyres; 1144 crtc->xoffset = xoffset; 1145 crtc->yoffset = yoffset; 1146 crtc->depth = depth; 1147 crtc->bpp = bpp; 1148 1149 return 0; 1150 } 1151 1152 1153 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) 1154 { 1155 1156 /* fill in pixel info */ 1157 var->red.msb_right = 0; 1158 var->green.msb_right = 0; 1159 var->blue.offset = 0; 1160 var->blue.msb_right = 0; 1161 var->transp.offset = 0; 1162 var->transp.length = 0; 1163 var->transp.msb_right = 0; 1164 switch (pix_width) { 1165 case CRTC_PIX_WIDTH_8BPP: 1166 var->bits_per_pixel = 8; 1167 var->red.offset = 0; 1168 var->red.length = 8; 1169 var->green.offset = 0; 1170 var->green.length = 8; 1171 var->blue.length = 8; 1172 break; 1173 case CRTC_PIX_WIDTH_15BPP: 1174 var->bits_per_pixel = 16; 1175 var->red.offset = 10; 1176 var->red.length = 5; 1177 var->green.offset = 5; 1178 var->green.length = 5; 1179 var->blue.length = 5; 1180 break; 1181 case CRTC_PIX_WIDTH_16BPP: 1182 var->bits_per_pixel = 16; 1183 var->red.offset = 11; 1184 var->red.length = 5; 1185 var->green.offset = 5; 1186 var->green.length = 6; 1187 var->blue.length = 5; 1188 break; 1189 case CRTC_PIX_WIDTH_24BPP: 1190 var->bits_per_pixel = 24; 1191 var->red.offset = 16; 1192 var->red.length = 8; 1193 var->green.offset = 8; 1194 var->green.length = 8; 1195 var->blue.length = 8; 1196 break; 1197 case CRTC_PIX_WIDTH_32BPP: 1198 var->bits_per_pixel = 32; 1199 var->red.offset = 16; 1200 var->red.length = 8; 1201 var->green.offset = 8; 1202 var->green.length = 8; 1203 var->blue.length = 8; 1204 var->transp.offset = 24; 1205 var->transp.length = 8; 1206 break; 1207 default: 1208 printk(KERN_ERR "aty128fb: Invalid pixel width\n"); 1209 return -EINVAL; 1210 } 1211 1212 return 0; 1213 } 1214 1215 1216 static int aty128_crtc_to_var(const struct aty128_crtc *crtc, 1217 struct fb_var_screeninfo *var) 1218 { 1219 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; 1220 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; 1221 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1222 u32 pix_width; 1223 1224 /* fun with masking */ 1225 h_total = crtc->h_total & 0x1ff; 1226 h_disp = (crtc->h_total >> 16) & 0xff; 1227 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; 1228 h_sync_dly = crtc->h_sync_strt_wid & 0x7; 1229 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; 1230 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; 1231 v_total = crtc->v_total & 0x7ff; 1232 v_disp = (crtc->v_total >> 16) & 0x7ff; 1233 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1234 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1235 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; 1236 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1237 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1238 1239 /* do conversions */ 1240 xres = (h_disp + 1) << 3; 1241 yres = v_disp + 1; 1242 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; 1243 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; 1244 hslen = h_sync_wid << 3; 1245 upper = v_total - v_sync_strt - v_sync_wid; 1246 lower = v_sync_strt - v_disp; 1247 vslen = v_sync_wid; 1248 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1249 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1250 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1251 1252 aty128_pix_width_to_var(pix_width, var); 1253 1254 var->xres = xres; 1255 var->yres = yres; 1256 var->xres_virtual = crtc->vxres; 1257 var->yres_virtual = crtc->vyres; 1258 var->xoffset = crtc->xoffset; 1259 var->yoffset = crtc->yoffset; 1260 var->left_margin = left; 1261 var->right_margin = right; 1262 var->upper_margin = upper; 1263 var->lower_margin = lower; 1264 var->hsync_len = hslen; 1265 var->vsync_len = vslen; 1266 var->sync = sync; 1267 var->vmode = FB_VMODE_NONINTERLACED; 1268 1269 return 0; 1270 } 1271 1272 static void aty128_set_crt_enable(struct aty128fb_par *par, int on) 1273 { 1274 if (on) { 1275 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | 1276 CRT_CRTC_ON); 1277 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | 1278 DAC_PALETTE2_SNOOP_EN)); 1279 } else 1280 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & 1281 ~CRT_CRTC_ON); 1282 } 1283 1284 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) 1285 { 1286 u32 reg; 1287 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1288 struct fb_info *info = pci_get_drvdata(par->pdev); 1289 #endif 1290 1291 if (on) { 1292 reg = aty_ld_le32(LVDS_GEN_CNTL); 1293 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; 1294 reg &= ~LVDS_DISPLAY_DIS; 1295 aty_st_le32(LVDS_GEN_CNTL, reg); 1296 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1297 aty128_bl_set_power(info, FB_BLANK_UNBLANK); 1298 #endif 1299 } else { 1300 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1301 aty128_bl_set_power(info, FB_BLANK_POWERDOWN); 1302 #endif 1303 reg = aty_ld_le32(LVDS_GEN_CNTL); 1304 reg |= LVDS_DISPLAY_DIS; 1305 aty_st_le32(LVDS_GEN_CNTL, reg); 1306 mdelay(100); 1307 reg &= ~(LVDS_ON /*| LVDS_EN*/); 1308 aty_st_le32(LVDS_GEN_CNTL, reg); 1309 } 1310 } 1311 1312 static void aty128_set_pll(struct aty128_pll *pll, 1313 const struct aty128fb_par *par) 1314 { 1315 u32 div3; 1316 1317 unsigned char post_conv[] = /* register values for post dividers */ 1318 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; 1319 1320 /* select PPLL_DIV_3 */ 1321 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); 1322 1323 /* reset PLL */ 1324 aty_st_pll(PPLL_CNTL, 1325 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); 1326 1327 /* write the reference divider */ 1328 aty_pll_wait_readupdate(par); 1329 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); 1330 aty_pll_writeupdate(par); 1331 1332 div3 = aty_ld_pll(PPLL_DIV_3); 1333 div3 &= ~PPLL_FB3_DIV_MASK; 1334 div3 |= pll->feedback_divider; 1335 div3 &= ~PPLL_POST3_DIV_MASK; 1336 div3 |= post_conv[pll->post_divider] << 16; 1337 1338 /* write feedback and post dividers */ 1339 aty_pll_wait_readupdate(par); 1340 aty_st_pll(PPLL_DIV_3, div3); 1341 aty_pll_writeupdate(par); 1342 1343 aty_pll_wait_readupdate(par); 1344 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ 1345 aty_pll_writeupdate(par); 1346 1347 /* clear the reset, just in case */ 1348 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); 1349 } 1350 1351 1352 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, 1353 const struct aty128fb_par *par) 1354 { 1355 const struct aty128_constants c = par->constants; 1356 unsigned char post_dividers[] = {1,2,4,8,3,6,12}; 1357 u32 output_freq; 1358 u32 vclk; /* in .01 MHz */ 1359 int i = 0; 1360 u32 n, d; 1361 1362 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ 1363 1364 /* adjust pixel clock if necessary */ 1365 if (vclk > c.ppll_max) 1366 vclk = c.ppll_max; 1367 if (vclk * 12 < c.ppll_min) 1368 vclk = c.ppll_min/12; 1369 1370 /* now, find an acceptable divider */ 1371 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { 1372 output_freq = post_dividers[i] * vclk; 1373 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { 1374 pll->post_divider = post_dividers[i]; 1375 break; 1376 } 1377 } 1378 1379 if (i == ARRAY_SIZE(post_dividers)) 1380 return -EINVAL; 1381 1382 /* calculate feedback divider */ 1383 n = c.ref_divider * output_freq; 1384 d = c.ref_clk; 1385 1386 pll->feedback_divider = round_div(n, d); 1387 pll->vclk = vclk; 1388 1389 DBG("post %d feedback %d vlck %d output %d ref_divider %d " 1390 "vclk_per: %d\n", pll->post_divider, 1391 pll->feedback_divider, vclk, output_freq, 1392 c.ref_divider, period_in_ps); 1393 1394 return 0; 1395 } 1396 1397 1398 static int aty128_pll_to_var(const struct aty128_pll *pll, 1399 struct fb_var_screeninfo *var) 1400 { 1401 var->pixclock = 100000000 / pll->vclk; 1402 1403 return 0; 1404 } 1405 1406 1407 static void aty128_set_fifo(const struct aty128_ddafifo *dsp, 1408 const struct aty128fb_par *par) 1409 { 1410 aty_st_le32(DDA_CONFIG, dsp->dda_config); 1411 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); 1412 } 1413 1414 1415 static int aty128_ddafifo(struct aty128_ddafifo *dsp, 1416 const struct aty128_pll *pll, 1417 u32 depth, 1418 const struct aty128fb_par *par) 1419 { 1420 const struct aty128_meminfo *m = par->mem; 1421 u32 xclk = par->constants.xclk; 1422 u32 fifo_width = par->constants.fifo_width; 1423 u32 fifo_depth = par->constants.fifo_depth; 1424 s32 x, b, p, ron, roff; 1425 u32 n, d, bpp; 1426 1427 /* round up to multiple of 8 */ 1428 bpp = (depth+7) & ~7; 1429 1430 n = xclk * fifo_width; 1431 d = pll->vclk * bpp; 1432 x = round_div(n, d); 1433 1434 ron = 4 * m->MB + 1435 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + 1436 2 * m->Trp + 1437 m->Twr + 1438 m->CL + 1439 m->Tr2w + 1440 x; 1441 1442 DBG("x %x\n", x); 1443 1444 b = 0; 1445 while (x) { 1446 x >>= 1; 1447 b++; 1448 } 1449 p = b + 1; 1450 1451 ron <<= (11 - p); 1452 1453 n <<= (11 - p); 1454 x = round_div(n, d); 1455 roff = x * (fifo_depth - 4); 1456 1457 if ((ron + m->Rloop) >= roff) { 1458 printk(KERN_ERR "aty128fb: Mode out of range!\n"); 1459 return -EINVAL; 1460 } 1461 1462 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", 1463 p, m->Rloop, x, ron, roff); 1464 1465 dsp->dda_config = p << 16 | m->Rloop << 20 | x; 1466 dsp->dda_on_off = ron << 16 | roff; 1467 1468 return 0; 1469 } 1470 1471 1472 /* 1473 * This actually sets the video mode. 1474 */ 1475 static int aty128fb_set_par(struct fb_info *info) 1476 { 1477 struct aty128fb_par *par = info->par; 1478 u32 config; 1479 int err; 1480 1481 if ((err = aty128_decode_var(&info->var, par)) != 0) 1482 return err; 1483 1484 if (par->blitter_may_be_busy) 1485 wait_for_idle(par); 1486 1487 /* clear all registers that may interfere with mode setting */ 1488 aty_st_le32(OVR_CLR, 0); 1489 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); 1490 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); 1491 aty_st_le32(OV0_SCALE_CNTL, 0); 1492 aty_st_le32(MPP_TB_CONFIG, 0); 1493 aty_st_le32(MPP_GP_CONFIG, 0); 1494 aty_st_le32(SUBPIC_CNTL, 0); 1495 aty_st_le32(VIPH_CONTROL, 0); 1496 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ 1497 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ 1498 aty_st_le32(CAP0_TRIG_CNTL, 0); 1499 aty_st_le32(CAP1_TRIG_CNTL, 0); 1500 1501 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ 1502 1503 aty128_set_crtc(&par->crtc, par); 1504 aty128_set_pll(&par->pll, par); 1505 aty128_set_fifo(&par->fifo_reg, par); 1506 1507 config = aty_ld_le32(CNFG_CNTL) & ~3; 1508 1509 #if defined(__BIG_ENDIAN) 1510 if (par->crtc.bpp == 32) 1511 config |= 2; /* make aperture do 32 bit swapping */ 1512 else if (par->crtc.bpp == 16) 1513 config |= 1; /* make aperture do 16 bit swapping */ 1514 #endif 1515 1516 aty_st_le32(CNFG_CNTL, config); 1517 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1518 1519 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1520 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR 1521 : FB_VISUAL_DIRECTCOLOR; 1522 1523 if (par->chip_gen == rage_M3) { 1524 aty128_set_crt_enable(par, par->crt_on); 1525 aty128_set_lcd_enable(par, par->lcd_on); 1526 } 1527 if (par->accel_flags & FB_ACCELF_TEXT) 1528 aty128_init_engine(par); 1529 1530 #ifdef CONFIG_BOOTX_TEXT 1531 btext_update_display(info->fix.smem_start, 1532 (((par->crtc.h_total>>16) & 0xff)+1)*8, 1533 ((par->crtc.v_total>>16) & 0x7ff)+1, 1534 par->crtc.bpp, 1535 par->crtc.vxres*par->crtc.bpp/8); 1536 #endif /* CONFIG_BOOTX_TEXT */ 1537 1538 return 0; 1539 } 1540 1541 /* 1542 * encode/decode the User Defined Part of the Display 1543 */ 1544 1545 static int aty128_decode_var(struct fb_var_screeninfo *var, 1546 struct aty128fb_par *par) 1547 { 1548 int err; 1549 struct aty128_crtc crtc; 1550 struct aty128_pll pll; 1551 struct aty128_ddafifo fifo_reg; 1552 1553 if ((err = aty128_var_to_crtc(var, &crtc, par))) 1554 return err; 1555 1556 if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) 1557 return err; 1558 1559 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) 1560 return err; 1561 1562 par->crtc = crtc; 1563 par->pll = pll; 1564 par->fifo_reg = fifo_reg; 1565 par->accel_flags = var->accel_flags; 1566 1567 return 0; 1568 } 1569 1570 1571 static int aty128_encode_var(struct fb_var_screeninfo *var, 1572 const struct aty128fb_par *par) 1573 { 1574 int err; 1575 1576 if ((err = aty128_crtc_to_var(&par->crtc, var))) 1577 return err; 1578 1579 if ((err = aty128_pll_to_var(&par->pll, var))) 1580 return err; 1581 1582 var->nonstd = 0; 1583 var->activate = 0; 1584 1585 var->height = -1; 1586 var->width = -1; 1587 var->accel_flags = par->accel_flags; 1588 1589 return 0; 1590 } 1591 1592 1593 static int aty128fb_check_var(struct fb_var_screeninfo *var, 1594 struct fb_info *info) 1595 { 1596 struct aty128fb_par par; 1597 int err; 1598 1599 par = *(struct aty128fb_par *)info->par; 1600 if ((err = aty128_decode_var(var, &par)) != 0) 1601 return err; 1602 aty128_encode_var(var, &par); 1603 return 0; 1604 } 1605 1606 1607 /* 1608 * Pan or Wrap the Display 1609 */ 1610 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 1611 struct fb_info *fb) 1612 { 1613 struct aty128fb_par *par = fb->par; 1614 u32 xoffset, yoffset; 1615 u32 offset; 1616 u32 xres, yres; 1617 1618 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1619 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1620 1621 xoffset = (var->xoffset +7) & ~7; 1622 yoffset = var->yoffset; 1623 1624 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) 1625 return -EINVAL; 1626 1627 par->crtc.xoffset = xoffset; 1628 par->crtc.yoffset = yoffset; 1629 1630 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) 1631 & ~7; 1632 1633 if (par->crtc.bpp == 24) 1634 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ 1635 1636 aty_st_le32(CRTC_OFFSET, offset); 1637 1638 return 0; 1639 } 1640 1641 1642 /* 1643 * Helper function to store a single palette register 1644 */ 1645 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, 1646 struct aty128fb_par *par) 1647 { 1648 if (par->chip_gen == rage_M3) { 1649 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & 1650 ~DAC_PALETTE_ACCESS_CNTL); 1651 } 1652 1653 aty_st_8(PALETTE_INDEX, regno); 1654 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1655 } 1656 1657 static int aty128fb_sync(struct fb_info *info) 1658 { 1659 struct aty128fb_par *par = info->par; 1660 1661 if (par->blitter_may_be_busy) 1662 wait_for_idle(par); 1663 return 0; 1664 } 1665 1666 #ifndef MODULE 1667 static int aty128fb_setup(char *options) 1668 { 1669 char *this_opt; 1670 1671 if (!options || !*options) 1672 return 0; 1673 1674 while ((this_opt = strsep(&options, ",")) != NULL) { 1675 if (!strncmp(this_opt, "lcd:", 4)) { 1676 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); 1677 continue; 1678 } else if (!strncmp(this_opt, "crt:", 4)) { 1679 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); 1680 continue; 1681 } else if (!strncmp(this_opt, "backlight:", 10)) { 1682 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1683 backlight = simple_strtoul(this_opt+10, NULL, 0); 1684 #endif 1685 continue; 1686 } 1687 if(!strncmp(this_opt, "nomtrr", 6)) { 1688 mtrr = false; 1689 continue; 1690 } 1691 #ifdef CONFIG_PPC_PMAC 1692 /* vmode and cmode deprecated */ 1693 if (!strncmp(this_opt, "vmode:", 6)) { 1694 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); 1695 if (vmode > 0 && vmode <= VMODE_MAX) 1696 default_vmode = vmode; 1697 continue; 1698 } else if (!strncmp(this_opt, "cmode:", 6)) { 1699 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); 1700 switch (cmode) { 1701 case 0: 1702 case 8: 1703 default_cmode = CMODE_8; 1704 break; 1705 case 15: 1706 case 16: 1707 default_cmode = CMODE_16; 1708 break; 1709 case 24: 1710 case 32: 1711 default_cmode = CMODE_32; 1712 break; 1713 } 1714 continue; 1715 } 1716 #endif /* CONFIG_PPC_PMAC */ 1717 mode_option = this_opt; 1718 } 1719 return 0; 1720 } 1721 #endif /* MODULE */ 1722 1723 /* Backlight */ 1724 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1725 #define MAX_LEVEL 0xFF 1726 1727 static int aty128_bl_get_level_brightness(struct aty128fb_par *par, 1728 int level) 1729 { 1730 struct fb_info *info = pci_get_drvdata(par->pdev); 1731 int atylevel; 1732 1733 /* Get and convert the value */ 1734 /* No locking of bl_curve since we read a single value */ 1735 atylevel = MAX_LEVEL - 1736 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); 1737 1738 if (atylevel < 0) 1739 atylevel = 0; 1740 else if (atylevel > MAX_LEVEL) 1741 atylevel = MAX_LEVEL; 1742 1743 return atylevel; 1744 } 1745 1746 /* We turn off the LCD completely instead of just dimming the backlight. 1747 * This provides greater power saving and the display is useless without 1748 * backlight anyway 1749 */ 1750 #define BACKLIGHT_LVDS_OFF 1751 /* That one prevents proper CRT output with LCD off */ 1752 #undef BACKLIGHT_DAC_OFF 1753 1754 static int aty128_bl_update_status(struct backlight_device *bd) 1755 { 1756 struct aty128fb_par *par = bl_get_data(bd); 1757 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); 1758 int level; 1759 1760 if (bd->props.power != FB_BLANK_UNBLANK || 1761 bd->props.fb_blank != FB_BLANK_UNBLANK || 1762 !par->lcd_on) 1763 level = 0; 1764 else 1765 level = bd->props.brightness; 1766 1767 reg |= LVDS_BL_MOD_EN | LVDS_BLON; 1768 if (level > 0) { 1769 reg |= LVDS_DIGION; 1770 if (!(reg & LVDS_ON)) { 1771 reg &= ~LVDS_BLON; 1772 aty_st_le32(LVDS_GEN_CNTL, reg); 1773 aty_ld_le32(LVDS_GEN_CNTL); 1774 mdelay(10); 1775 reg |= LVDS_BLON; 1776 aty_st_le32(LVDS_GEN_CNTL, reg); 1777 } 1778 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1779 reg |= (aty128_bl_get_level_brightness(par, level) << 1780 LVDS_BL_MOD_LEVEL_SHIFT); 1781 #ifdef BACKLIGHT_LVDS_OFF 1782 reg |= LVDS_ON | LVDS_EN; 1783 reg &= ~LVDS_DISPLAY_DIS; 1784 #endif 1785 aty_st_le32(LVDS_GEN_CNTL, reg); 1786 #ifdef BACKLIGHT_DAC_OFF 1787 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); 1788 #endif 1789 } else { 1790 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1791 reg |= (aty128_bl_get_level_brightness(par, 0) << 1792 LVDS_BL_MOD_LEVEL_SHIFT); 1793 #ifdef BACKLIGHT_LVDS_OFF 1794 reg |= LVDS_DISPLAY_DIS; 1795 aty_st_le32(LVDS_GEN_CNTL, reg); 1796 aty_ld_le32(LVDS_GEN_CNTL); 1797 udelay(10); 1798 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); 1799 #endif 1800 aty_st_le32(LVDS_GEN_CNTL, reg); 1801 #ifdef BACKLIGHT_DAC_OFF 1802 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); 1803 #endif 1804 } 1805 1806 return 0; 1807 } 1808 1809 static const struct backlight_ops aty128_bl_data = { 1810 .update_status = aty128_bl_update_status, 1811 }; 1812 1813 static void aty128_bl_set_power(struct fb_info *info, int power) 1814 { 1815 if (info->bl_dev) { 1816 info->bl_dev->props.power = power; 1817 backlight_update_status(info->bl_dev); 1818 } 1819 } 1820 1821 static void aty128_bl_init(struct aty128fb_par *par) 1822 { 1823 struct backlight_properties props; 1824 struct fb_info *info = pci_get_drvdata(par->pdev); 1825 struct backlight_device *bd; 1826 char name[12]; 1827 1828 /* Could be extended to Rage128Pro LVDS output too */ 1829 if (par->chip_gen != rage_M3) 1830 return; 1831 1832 #ifdef CONFIG_PMAC_BACKLIGHT 1833 if (!pmac_has_backlight_type("ati")) 1834 return; 1835 #endif 1836 1837 snprintf(name, sizeof(name), "aty128bl%d", info->node); 1838 1839 memset(&props, 0, sizeof(struct backlight_properties)); 1840 props.type = BACKLIGHT_RAW; 1841 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 1842 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data, 1843 &props); 1844 if (IS_ERR(bd)) { 1845 info->bl_dev = NULL; 1846 printk(KERN_WARNING "aty128: Backlight registration failed\n"); 1847 goto error; 1848 } 1849 1850 info->bl_dev = bd; 1851 fb_bl_default_curve(info, 0, 1852 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, 1853 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); 1854 1855 bd->props.brightness = bd->props.max_brightness; 1856 bd->props.power = FB_BLANK_UNBLANK; 1857 backlight_update_status(bd); 1858 1859 printk("aty128: Backlight initialized (%s)\n", name); 1860 1861 return; 1862 1863 error: 1864 return; 1865 } 1866 1867 static void aty128_bl_exit(struct backlight_device *bd) 1868 { 1869 backlight_device_unregister(bd); 1870 printk("aty128: Backlight unloaded\n"); 1871 } 1872 #endif /* CONFIG_FB_ATY128_BACKLIGHT */ 1873 1874 /* 1875 * Initialisation 1876 */ 1877 1878 #ifdef CONFIG_PPC_PMAC__disabled 1879 static void aty128_early_resume(void *data) 1880 { 1881 struct aty128fb_par *par = data; 1882 1883 if (!console_trylock()) 1884 return; 1885 pci_restore_state(par->pdev); 1886 aty128_do_resume(par->pdev); 1887 console_unlock(); 1888 } 1889 #endif /* CONFIG_PPC_PMAC */ 1890 1891 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) 1892 { 1893 struct fb_info *info = pci_get_drvdata(pdev); 1894 struct aty128fb_par *par = info->par; 1895 struct fb_var_screeninfo var; 1896 char video_card[50]; 1897 u8 chip_rev; 1898 u32 dac; 1899 1900 /* Get the chip revision */ 1901 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; 1902 1903 strcpy(video_card, "Rage128 XX "); 1904 video_card[8] = ent->device >> 8; 1905 video_card[9] = ent->device & 0xFF; 1906 1907 /* range check to make sure */ 1908 if (ent->driver_data < ARRAY_SIZE(r128_family)) 1909 strlcat(video_card, r128_family[ent->driver_data], 1910 sizeof(video_card)); 1911 1912 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1913 1914 if (par->vram_size % (1024 * 1024) == 0) 1915 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); 1916 else 1917 printk("%dk %s\n", par->vram_size / 1024, par->mem->name); 1918 1919 par->chip_gen = ent->driver_data; 1920 1921 /* fill in info */ 1922 info->fbops = &aty128fb_ops; 1923 info->flags = FBINFO_FLAG_DEFAULT; 1924 1925 par->lcd_on = default_lcd_on; 1926 par->crt_on = default_crt_on; 1927 1928 var = default_var; 1929 #ifdef CONFIG_PPC_PMAC 1930 if (machine_is(powermac)) { 1931 /* Indicate sleep capability */ 1932 if (par->chip_gen == rage_M3) { 1933 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); 1934 #if 0 /* Disable the early video resume hack for now as it's causing problems, 1935 * among others we now rely on the PCI core restoring the config space 1936 * for us, which isn't the case with that hack, and that code path causes 1937 * various things to be called with interrupts off while they shouldn't. 1938 * I'm leaving the code in as it can be useful for debugging purposes 1939 */ 1940 pmac_set_early_video_resume(aty128_early_resume, par); 1941 #endif 1942 } 1943 1944 /* Find default mode */ 1945 if (mode_option) { 1946 if (!mac_find_mode(&var, info, mode_option, 8)) 1947 var = default_var; 1948 } else { 1949 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1950 default_vmode = VMODE_1024_768_60; 1951 1952 /* iMacs need that resolution 1953 * PowerMac2,1 first r128 iMacs 1954 * PowerMac2,2 summer 2000 iMacs 1955 * PowerMac4,1 january 2001 iMacs "flower power" 1956 */ 1957 if (of_machine_is_compatible("PowerMac2,1") || 1958 of_machine_is_compatible("PowerMac2,2") || 1959 of_machine_is_compatible("PowerMac4,1")) 1960 default_vmode = VMODE_1024_768_75; 1961 1962 /* iBook SE */ 1963 if (of_machine_is_compatible("PowerBook2,2")) 1964 default_vmode = VMODE_800_600_60; 1965 1966 /* PowerBook Firewire (Pismo), iBook Dual USB */ 1967 if (of_machine_is_compatible("PowerBook3,1") || 1968 of_machine_is_compatible("PowerBook4,1")) 1969 default_vmode = VMODE_1024_768_60; 1970 1971 /* PowerBook Titanium */ 1972 if (of_machine_is_compatible("PowerBook3,2")) 1973 default_vmode = VMODE_1152_768_60; 1974 1975 if (default_cmode > 16) 1976 default_cmode = CMODE_32; 1977 else if (default_cmode > 8) 1978 default_cmode = CMODE_16; 1979 else 1980 default_cmode = CMODE_8; 1981 1982 if (mac_vmode_to_var(default_vmode, default_cmode, &var)) 1983 var = default_var; 1984 } 1985 } else 1986 #endif /* CONFIG_PPC_PMAC */ 1987 { 1988 if (mode_option) 1989 if (fb_find_mode(&var, info, mode_option, NULL, 1990 0, &defaultmode, 8) == 0) 1991 var = default_var; 1992 } 1993 1994 var.accel_flags &= ~FB_ACCELF_TEXT; 1995 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ 1996 1997 if (aty128fb_check_var(&var, info)) { 1998 printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); 1999 return 0; 2000 } 2001 2002 /* setup the DAC the way we like it */ 2003 dac = aty_ld_le32(DAC_CNTL); 2004 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); 2005 dac |= DAC_MASK; 2006 if (par->chip_gen == rage_M3) 2007 dac |= DAC_PALETTE2_SNOOP_EN; 2008 aty_st_le32(DAC_CNTL, dac); 2009 2010 /* turn off bus mastering, just in case */ 2011 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); 2012 2013 info->var = var; 2014 fb_alloc_cmap(&info->cmap, 256, 0); 2015 2016 var.activate = FB_ACTIVATE_NOW; 2017 2018 aty128_init_engine(par); 2019 2020 par->pdev = pdev; 2021 par->asleep = 0; 2022 par->lock_blank = 0; 2023 2024 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2025 if (backlight) 2026 aty128_bl_init(par); 2027 #endif 2028 2029 if (register_framebuffer(info) < 0) 2030 return 0; 2031 2032 fb_info(info, "%s frame buffer device on %s\n", 2033 info->fix.id, video_card); 2034 2035 return 1; /* success! */ 2036 } 2037 2038 #ifdef CONFIG_PCI 2039 /* register a card ++ajoshi */ 2040 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2041 { 2042 unsigned long fb_addr, reg_addr; 2043 struct aty128fb_par *par; 2044 struct fb_info *info; 2045 int err; 2046 #ifndef __sparc__ 2047 void __iomem *bios = NULL; 2048 #endif 2049 2050 /* Enable device in PCI config */ 2051 if ((err = pci_enable_device(pdev))) { 2052 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", 2053 err); 2054 return -ENODEV; 2055 } 2056 2057 fb_addr = pci_resource_start(pdev, 0); 2058 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), 2059 "aty128fb FB")) { 2060 printk(KERN_ERR "aty128fb: cannot reserve frame " 2061 "buffer memory\n"); 2062 return -ENODEV; 2063 } 2064 2065 reg_addr = pci_resource_start(pdev, 2); 2066 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), 2067 "aty128fb MMIO")) { 2068 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); 2069 goto err_free_fb; 2070 } 2071 2072 /* We have the resources. Now virtualize them */ 2073 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); 2074 if (!info) 2075 goto err_free_mmio; 2076 2077 par = info->par; 2078 2079 info->pseudo_palette = par->pseudo_palette; 2080 2081 /* Virtualize mmio region */ 2082 info->fix.mmio_start = reg_addr; 2083 par->regbase = pci_ioremap_bar(pdev, 2); 2084 if (!par->regbase) 2085 goto err_free_info; 2086 2087 /* Grab memory size from the card */ 2088 // How does this relate to the resource length from the PCI hardware? 2089 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; 2090 2091 /* Virtualize the framebuffer */ 2092 info->screen_base = ioremap_wc(fb_addr, par->vram_size); 2093 if (!info->screen_base) 2094 goto err_unmap_out; 2095 2096 /* Set up info->fix */ 2097 info->fix = aty128fb_fix; 2098 info->fix.smem_start = fb_addr; 2099 info->fix.smem_len = par->vram_size; 2100 info->fix.mmio_start = reg_addr; 2101 2102 /* If we can't test scratch registers, something is seriously wrong */ 2103 if (!register_test(par)) { 2104 printk(KERN_ERR "aty128fb: Can't write to video register!\n"); 2105 goto err_out; 2106 } 2107 2108 #ifndef __sparc__ 2109 bios = aty128_map_ROM(par, pdev); 2110 #ifdef CONFIG_X86 2111 if (bios == NULL) 2112 bios = aty128_find_mem_vbios(par); 2113 #endif 2114 if (bios == NULL) 2115 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); 2116 else { 2117 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); 2118 aty128_get_pllinfo(par, bios); 2119 pci_unmap_rom(pdev, bios); 2120 } 2121 #endif /* __sparc__ */ 2122 2123 aty128_timings(par); 2124 pci_set_drvdata(pdev, info); 2125 2126 if (!aty128_init(pdev, ent)) 2127 goto err_out; 2128 2129 if (mtrr) 2130 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 2131 par->vram_size); 2132 return 0; 2133 2134 err_out: 2135 iounmap(info->screen_base); 2136 err_unmap_out: 2137 iounmap(par->regbase); 2138 err_free_info: 2139 framebuffer_release(info); 2140 err_free_mmio: 2141 release_mem_region(pci_resource_start(pdev, 2), 2142 pci_resource_len(pdev, 2)); 2143 err_free_fb: 2144 release_mem_region(pci_resource_start(pdev, 0), 2145 pci_resource_len(pdev, 0)); 2146 return -ENODEV; 2147 } 2148 2149 static void aty128_remove(struct pci_dev *pdev) 2150 { 2151 struct fb_info *info = pci_get_drvdata(pdev); 2152 struct aty128fb_par *par; 2153 2154 if (!info) 2155 return; 2156 2157 par = info->par; 2158 2159 unregister_framebuffer(info); 2160 2161 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2162 aty128_bl_exit(info->bl_dev); 2163 #endif 2164 2165 arch_phys_wc_del(par->wc_cookie); 2166 iounmap(par->regbase); 2167 iounmap(info->screen_base); 2168 2169 release_mem_region(pci_resource_start(pdev, 0), 2170 pci_resource_len(pdev, 0)); 2171 release_mem_region(pci_resource_start(pdev, 2), 2172 pci_resource_len(pdev, 2)); 2173 framebuffer_release(info); 2174 } 2175 #endif /* CONFIG_PCI */ 2176 2177 2178 2179 /* 2180 * Blank the display. 2181 */ 2182 static int aty128fb_blank(int blank, struct fb_info *fb) 2183 { 2184 struct aty128fb_par *par = fb->par; 2185 u8 state; 2186 2187 if (par->lock_blank || par->asleep) 2188 return 0; 2189 2190 switch (blank) { 2191 case FB_BLANK_NORMAL: 2192 state = 4; 2193 break; 2194 case FB_BLANK_VSYNC_SUSPEND: 2195 state = 6; 2196 break; 2197 case FB_BLANK_HSYNC_SUSPEND: 2198 state = 5; 2199 break; 2200 case FB_BLANK_POWERDOWN: 2201 state = 7; 2202 break; 2203 case FB_BLANK_UNBLANK: 2204 default: 2205 state = 0; 2206 break; 2207 } 2208 aty_st_8(CRTC_EXT_CNTL+1, state); 2209 2210 if (par->chip_gen == rage_M3) { 2211 aty128_set_crt_enable(par, par->crt_on && !blank); 2212 aty128_set_lcd_enable(par, par->lcd_on && !blank); 2213 } 2214 2215 return 0; 2216 } 2217 2218 /* 2219 * Set a single color register. The values supplied are already 2220 * rounded down to the hardware's capabilities (according to the 2221 * entries in the var structure). Return != 0 for invalid regno. 2222 */ 2223 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2224 u_int transp, struct fb_info *info) 2225 { 2226 struct aty128fb_par *par = info->par; 2227 2228 if (regno > 255 2229 || (par->crtc.depth == 16 && regno > 63) 2230 || (par->crtc.depth == 15 && regno > 31)) 2231 return 1; 2232 2233 red >>= 8; 2234 green >>= 8; 2235 blue >>= 8; 2236 2237 if (regno < 16) { 2238 int i; 2239 u32 *pal = info->pseudo_palette; 2240 2241 switch (par->crtc.depth) { 2242 case 15: 2243 pal[regno] = (regno << 10) | (regno << 5) | regno; 2244 break; 2245 case 16: 2246 pal[regno] = (regno << 11) | (regno << 6) | regno; 2247 break; 2248 case 24: 2249 pal[regno] = (regno << 16) | (regno << 8) | regno; 2250 break; 2251 case 32: 2252 i = (regno << 8) | regno; 2253 pal[regno] = (i << 16) | i; 2254 break; 2255 } 2256 } 2257 2258 if (par->crtc.depth == 16 && regno > 0) { 2259 /* 2260 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we 2261 * have 32 slots for R and B values but 64 slots for G values. 2262 * Thus the R and B values go in one slot but the G value 2263 * goes in a different slot, and we have to avoid disturbing 2264 * the other fields in the slots we touch. 2265 */ 2266 par->green[regno] = green; 2267 if (regno < 32) { 2268 par->red[regno] = red; 2269 par->blue[regno] = blue; 2270 aty128_st_pal(regno * 8, red, par->green[regno*2], 2271 blue, par); 2272 } 2273 red = par->red[regno/2]; 2274 blue = par->blue[regno/2]; 2275 regno <<= 2; 2276 } else if (par->crtc.bpp == 16) 2277 regno <<= 3; 2278 aty128_st_pal(regno, red, green, blue, par); 2279 2280 return 0; 2281 } 2282 2283 #define ATY_MIRROR_LCD_ON 0x00000001 2284 #define ATY_MIRROR_CRT_ON 0x00000002 2285 2286 /* out param: u32* backlight value: 0 to 15 */ 2287 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) 2288 /* in param: u32* backlight value: 0 to 15 */ 2289 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) 2290 2291 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 2292 { 2293 struct aty128fb_par *par = info->par; 2294 u32 value; 2295 int rc; 2296 2297 switch (cmd) { 2298 case FBIO_ATY128_SET_MIRROR: 2299 if (par->chip_gen != rage_M3) 2300 return -EINVAL; 2301 rc = get_user(value, (__u32 __user *)arg); 2302 if (rc) 2303 return rc; 2304 par->lcd_on = (value & 0x01) != 0; 2305 par->crt_on = (value & 0x02) != 0; 2306 if (!par->crt_on && !par->lcd_on) 2307 par->lcd_on = 1; 2308 aty128_set_crt_enable(par, par->crt_on); 2309 aty128_set_lcd_enable(par, par->lcd_on); 2310 return 0; 2311 case FBIO_ATY128_GET_MIRROR: 2312 if (par->chip_gen != rage_M3) 2313 return -EINVAL; 2314 value = (par->crt_on << 1) | par->lcd_on; 2315 return put_user(value, (__u32 __user *)arg); 2316 } 2317 return -EINVAL; 2318 } 2319 2320 static void aty128_set_suspend(struct aty128fb_par *par, int suspend) 2321 { 2322 u32 pmgt; 2323 struct pci_dev *pdev = par->pdev; 2324 2325 if (!par->pdev->pm_cap) 2326 return; 2327 2328 /* Set the chip into the appropriate suspend mode (we use D2, 2329 * D3 would require a complete re-initialisation of the chip, 2330 * including PCI config registers, clocks, AGP configuration, ...) 2331 * 2332 * For resume, the core will have already brought us back to D0 2333 */ 2334 if (suspend) { 2335 /* Make sure CRTC2 is reset. Remove that the day we decide to 2336 * actually use CRTC2 and replace it with real code for disabling 2337 * the CRTC2 output during sleep 2338 */ 2339 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & 2340 ~(CRTC2_EN)); 2341 2342 /* Set the power management mode to be PCI based */ 2343 /* Use this magic value for now */ 2344 pmgt = 0x0c005407; 2345 aty_st_pll(POWER_MANAGEMENT, pmgt); 2346 (void)aty_ld_pll(POWER_MANAGEMENT); 2347 aty_st_le32(BUS_CNTL1, 0x00000010); 2348 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2349 msleep(100); 2350 2351 /* Switch PCI power management to D2 */ 2352 pci_set_power_state(pdev, PCI_D2); 2353 } 2354 } 2355 2356 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state) 2357 { 2358 struct fb_info *info = pci_get_drvdata(pdev); 2359 struct aty128fb_par *par = info->par; 2360 2361 /* Because we may change PCI D state ourselves, we need to 2362 * first save the config space content so the core can 2363 * restore it properly on resume. 2364 */ 2365 pci_save_state(pdev); 2366 2367 /* We don't do anything but D2, for now we return 0, but 2368 * we may want to change that. How do we know if the BIOS 2369 * can properly take care of D3 ? Also, with swsusp, we 2370 * know we'll be rebooted, ... 2371 */ 2372 #ifndef CONFIG_PPC_PMAC 2373 /* HACK ALERT ! Once I find a proper way to say to each driver 2374 * individually what will happen with it's PCI slot, I'll change 2375 * that. On laptops, the AGP slot is just unclocked, so D2 is 2376 * expected, while on desktops, the card is powered off 2377 */ 2378 return 0; 2379 #endif /* CONFIG_PPC_PMAC */ 2380 2381 if (state.event == pdev->dev.power.power_state.event) 2382 return 0; 2383 2384 printk(KERN_DEBUG "aty128fb: suspending...\n"); 2385 2386 console_lock(); 2387 2388 fb_set_suspend(info, 1); 2389 2390 /* Make sure engine is reset */ 2391 wait_for_idle(par); 2392 aty128_reset_engine(par); 2393 wait_for_idle(par); 2394 2395 /* Blank display and LCD */ 2396 aty128fb_blank(FB_BLANK_POWERDOWN, info); 2397 2398 /* Sleep */ 2399 par->asleep = 1; 2400 par->lock_blank = 1; 2401 2402 #ifdef CONFIG_PPC_PMAC 2403 /* On powermac, we have hooks to properly suspend/resume AGP now, 2404 * use them here. We'll ultimately need some generic support here, 2405 * but the generic code isn't quite ready for that yet 2406 */ 2407 pmac_suspend_agp_for_card(pdev); 2408 #endif /* CONFIG_PPC_PMAC */ 2409 2410 /* We need a way to make sure the fbdev layer will _not_ touch the 2411 * framebuffer before we put the chip to suspend state. On 2.4, I 2412 * used dummy fb ops, 2.5 need proper support for this at the 2413 * fbdev level 2414 */ 2415 if (state.event != PM_EVENT_ON) 2416 aty128_set_suspend(par, 1); 2417 2418 console_unlock(); 2419 2420 pdev->dev.power.power_state = state; 2421 2422 return 0; 2423 } 2424 2425 static int aty128_do_resume(struct pci_dev *pdev) 2426 { 2427 struct fb_info *info = pci_get_drvdata(pdev); 2428 struct aty128fb_par *par = info->par; 2429 2430 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2431 return 0; 2432 2433 /* PCI state will have been restored by the core, so 2434 * we should be in D0 now with our config space fully 2435 * restored 2436 */ 2437 2438 /* Wakeup chip */ 2439 aty128_set_suspend(par, 0); 2440 par->asleep = 0; 2441 2442 /* Restore display & engine */ 2443 aty128_reset_engine(par); 2444 wait_for_idle(par); 2445 aty128fb_set_par(info); 2446 fb_pan_display(info, &info->var); 2447 fb_set_cmap(&info->cmap, info); 2448 2449 /* Refresh */ 2450 fb_set_suspend(info, 0); 2451 2452 /* Unblank */ 2453 par->lock_blank = 0; 2454 aty128fb_blank(0, info); 2455 2456 #ifdef CONFIG_PPC_PMAC 2457 /* On powermac, we have hooks to properly suspend/resume AGP now, 2458 * use them here. We'll ultimately need some generic support here, 2459 * but the generic code isn't quite ready for that yet 2460 */ 2461 pmac_resume_agp_for_card(pdev); 2462 #endif /* CONFIG_PPC_PMAC */ 2463 2464 pdev->dev.power.power_state = PMSG_ON; 2465 2466 printk(KERN_DEBUG "aty128fb: resumed !\n"); 2467 2468 return 0; 2469 } 2470 2471 static int aty128_pci_resume(struct pci_dev *pdev) 2472 { 2473 int rc; 2474 2475 console_lock(); 2476 rc = aty128_do_resume(pdev); 2477 console_unlock(); 2478 2479 return rc; 2480 } 2481 2482 2483 static int aty128fb_init(void) 2484 { 2485 #ifndef MODULE 2486 char *option = NULL; 2487 2488 if (fb_get_options("aty128fb", &option)) 2489 return -ENODEV; 2490 aty128fb_setup(option); 2491 #endif 2492 2493 return pci_register_driver(&aty128fb_driver); 2494 } 2495 2496 static void __exit aty128fb_exit(void) 2497 { 2498 pci_unregister_driver(&aty128fb_driver); 2499 } 2500 2501 module_init(aty128fb_init); 2502 2503 module_exit(aty128fb_exit); 2504 2505 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); 2506 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); 2507 MODULE_LICENSE("GPL"); 2508 module_param(mode_option, charp, 0); 2509 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2510 module_param_named(nomtrr, mtrr, invbool, 0); 2511 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); 2512