1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 SolidRun ltd.
4 * Based on Marvell MACCHIATOBin board
5 *
6 * Device Tree file for SolidRun's ClearFog GT 8K
7 */
8
9#include "armada-8040.dtsi"
10
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	model = "SolidRun ClearFog GT 8K";
16	compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17			"marvell,armada-ap806-quad", "marvell,armada-ap806";
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	memory@00000000 {
24		device_type = "memory";
25		reg = <0x0 0x0 0x0 0x80000000>;
26	};
27
28	aliases {
29		ethernet0 = &cp1_eth1;
30		ethernet1 = &cp0_eth0;
31		ethernet2 = &cp1_eth2;
32	};
33
34	v_3_3: regulator-3-3v {
35		compatible = "regulator-fixed";
36		regulator-name = "v_3_3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		regulator-always-on;
40		status = "okay";
41	};
42
43	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
44		compatible = "regulator-fixed";
45		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
46		pinctrl-names = "default";
47		pinctrl-0 = <&cp0_xhci_vbus_pins>;
48		regulator-name = "v_5v0_usb3_hst_vbus";
49		regulator-min-microvolt = <5000000>;
50		regulator-max-microvolt = <5000000>;
51		status = "okay";
52	};
53
54	sfp_cp0_eth0: sfp-cp0-eth0 {
55		compatible = "sff,sfp";
56		i2c-bus = <&cp0_i2c1>;
57		mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
58		tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
59		pinctrl-names = "default";
60		pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
61		maximum-power-milliwatt = <2000>;
62	};
63
64	leds {
65		compatible = "gpio-leds";
66		pinctrl-0 = <&cp0_led0_pins
67			     &cp0_led1_pins>;
68		pinctrl-names = "default";
69		/* No designated function for these LEDs at the moment */
70		led0 {
71			label = "clearfog-gt-8k:green:led0";
72			gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
73			default-state = "on";
74		};
75		led1 {
76			label = "clearfog-gt-8k:green:led1";
77			gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
78			default-state = "on";
79		};
80	};
81
82	keys {
83		compatible = "gpio-keys";
84		pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
85		pinctrl-names = "default";
86
87		button_0 {
88			/* The rear button */
89			label = "Rear Button";
90			gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
91			linux,can-disable;
92			linux,code = <BTN_0>;
93		};
94
95		button_1 {
96			/* The wps button */
97			label = "WPS Button";
98			gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
99			linux,can-disable;
100			linux,code = <KEY_WPS_BUTTON>;
101		};
102	};
103};
104
105&uart0 {
106	status = "okay";
107	pinctrl-0 = <&uart0_pins>;
108	pinctrl-names = "default";
109};
110
111&ap_sdhci0 {
112	bus-width = <8>;
113	no-1-8-v;
114	no-sd;
115	no-sdio;
116	non-removable;
117	status = "okay";
118	vqmmc-supply = <&v_3_3>;
119};
120
121&cp0_i2c0 {
122	clock-frequency = <100000>;
123	pinctrl-names = "default";
124	pinctrl-0 = <&cp0_i2c0_pins>;
125	status = "okay";
126};
127
128&cp0_i2c1 {
129	clock-frequency = <100000>;
130	pinctrl-names = "default";
131	pinctrl-0 = <&cp0_i2c1_pins>;
132	status = "okay";
133};
134
135&cp0_pinctrl {
136	/*
137	 * MPP Bus:
138	 * [0-31] = 0xff: Keep default CP0_shared_pins:
139	 * [11] CLKOUT_MPP_11 (out)
140	 * [23] LINK_RD_IN_CP2CP (in)
141	 * [25] CLKOUT_MPP_25 (out)
142	 * [29] AVS_FB_IN_CP2CP (in)
143	 * [32, 33, 34] pci0/1/2 reset
144	 * [35-38] CP0 I2C1 and I2C0
145	 * [39] GPIO reset button
146	 * [40,41] LED0 and LED1
147	 * [43] 1512 phy reset
148	 * [47] USB VBUS EN (active low)
149	 * [48] FAN PWM
150	 * [49] SFP+ present signal
151	 * [50] TPM interrupt
152	 * [51] WLAN0 disable
153	 * [52] WLAN1 disable
154	 * [53] LTE disable
155	 * [54] NFC reset
156	 * [55] Micro SD card detect
157	 * [56-61] Micro SD
158	 */
159
160	cp0_pci0_reset_pins: pci0-reset-pins {
161		marvell,pins = "mpp32";
162		marvell,function = "gpio";
163	};
164
165	cp0_pci1_reset_pins: pci1-reset-pins {
166		marvell,pins = "mpp33";
167		marvell,function = "gpio";
168	};
169
170	cp0_pci2_reset_pins: pci2-reset-pins {
171		marvell,pins = "mpp34";
172		marvell,function = "gpio";
173	};
174
175	cp0_i2c1_pins: i2c1-pins {
176		marvell,pins = "mpp35", "mpp36";
177		marvell,function = "i2c1";
178	};
179
180	cp0_i2c0_pins: i2c0-pins {
181		marvell,pins = "mpp37", "mpp38";
182		marvell,function = "i2c0";
183	};
184
185	cp0_gpio_reset_pins: gpio-reset-pins {
186		marvell,pins = "mpp39";
187		marvell,function = "gpio";
188	};
189
190	cp0_led0_pins: led0-pins {
191		marvell,pins = "mpp40";
192		marvell,function = "gpio";
193	};
194
195	cp0_led1_pins: led1-pins {
196		marvell,pins = "mpp41";
197		marvell,function = "gpio";
198	};
199
200	cp0_copper_eth_phy_reset: copper-eth-phy-reset {
201		marvell,pins = "mpp43";
202		marvell,function = "gpio";
203	};
204
205	cp0_xhci_vbus_pins: xhci0-vbus-pins {
206		marvell,pins = "mpp47";
207		marvell,function = "gpio";
208	};
209
210	cp0_fan_pwm_pins: fan-pwm-pins {
211		marvell,pins = "mpp48";
212		marvell,function = "gpio";
213	};
214
215	cp0_sfp_present_pins: sfp-present-pins {
216		marvell,pins = "mpp49";
217		marvell,function = "gpio";
218	};
219
220	cp0_tpm_irq_pins: tpm-irq-pins {
221		marvell,pins = "mpp50";
222		marvell,function = "gpio";
223	};
224
225	cp0_wlan_disable_pins: wlan-disable-pins {
226		marvell,pins = "mpp51";
227		marvell,function = "gpio";
228	};
229
230	cp0_sdhci_pins: sdhci-pins {
231		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
232			       "mpp60", "mpp61";
233		marvell,function = "sdio";
234	};
235};
236
237&cp0_pcie0 {
238	pinctrl-names = "default";
239	pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
240	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
241	phys = <&cp0_comphy0 0>;
242	phy-names = "cp0-pcie0-x1-phy";
243	status = "okay";
244};
245
246&cp0_gpio2 {
247	sata_reset {
248		gpio-hog;
249		gpios = <1 GPIO_ACTIVE_HIGH>;
250		output-high;
251	};
252
253	lte_reset {
254		gpio-hog;
255		gpios = <2 GPIO_ACTIVE_LOW>;
256		output-low;
257	};
258
259	wlan_disable {
260		gpio-hog;
261		gpios = <19 GPIO_ACTIVE_LOW>;
262		output-low;
263	};
264
265	lte_disable {
266		gpio-hog;
267		gpios = <21 GPIO_ACTIVE_LOW>;
268		output-low;
269	};
270};
271
272&cp0_ethernet {
273	status = "okay";
274};
275
276/* SFP */
277&cp0_eth0 {
278	status = "okay";
279	phy-mode = "10gbase-r";
280	managed = "in-band-status";
281	phys = <&cp0_comphy2 0>;
282	sfp = <&sfp_cp0_eth0>;
283};
284
285&cp0_sdhci0 {
286	broken-cd;
287	bus-width = <4>;
288	pinctrl-names = "default";
289	pinctrl-0 = <&cp0_sdhci_pins>;
290	status = "okay";
291	vqmmc-supply = <&v_3_3>;
292};
293
294&cp0_usb3_1 {
295	status = "okay";
296};
297
298&cp1_pinctrl {
299	/*
300	 * MPP Bus:
301	 * [0-5] TDM
302	 * [6]   VHV Enable
303	 * [7]   CP1 SPI0 CSn1 (FXS)
304	 * [8]   CP1 SPI0 CSn0 (TPM)
305	 * [9.11]CP1 SPI0 MOSI/MISO/CLK
306	 * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
307	 * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
308	 * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
309	 * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
310	 * [24]  Topaz switch reset
311	 * [26]  Buzzer
312	 * [27]  CP1 SMI MDIO
313	 * [28]  CP1 SMI MDC
314	 * [29]  CP0 10G SFP TX Disable
315	 * [30]  WPS button
316	 * [31]  Front panel button
317	 */
318
319	cp1_spi1_pins: spi1-pins {
320		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
321		marvell,function = "spi1";
322	};
323
324	cp1_switch_reset_pins: switch-reset-pins {
325		marvell,pins = "mpp24";
326		marvell,function = "gpio";
327	};
328
329	cp1_ge_mdio_pins: ge-mdio-pins {
330		marvell,pins = "mpp27", "mpp28";
331		marvell,function = "ge";
332	};
333
334	cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
335		marvell,pins = "mpp29";
336		marvell,function = "gpio";
337	};
338
339	cp1_wps_button_pins: wps-button-pins {
340		marvell,pins = "mpp30";
341		marvell,function = "gpio";
342	};
343};
344
345&cp1_sata0 {
346	pinctrl-0 = <&cp0_pci1_reset_pins>;
347	status = "okay";
348
349	sata-port@1 {
350		phys = <&cp1_comphy0 1>;
351		phy-names = "cp1-sata0-1-phy";
352	};
353};
354
355&cp1_mdio {
356	pinctrl-names = "default";
357	pinctrl-0 = <&cp1_ge_mdio_pins>;
358	status = "okay";
359
360	ge_phy: ethernet-phy@0 {
361		/* LED0 - GB link
362		 * LED1 - on: link, blink: activity
363		 */
364		marvell,reg-init = <3 16 0 0x1017>;
365		reg = <0>;
366		pinctrl-names = "default";
367		pinctrl-0 = <&cp0_copper_eth_phy_reset>;
368		reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
369		reset-assert-us = <10000>;
370		reset-deassert-us = <10000>;
371	};
372
373	switch0: switch0@4 {
374		compatible = "marvell,mv88e6085";
375		reg = <4>;
376		pinctrl-names = "default";
377		pinctrl-0 = <&cp1_switch_reset_pins>;
378		reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
379
380		ports {
381			#address-cells = <1>;
382			#size-cells = <0>;
383
384			port@1 {
385				reg = <1>;
386				label = "lan2";
387				phy-handle = <&switch0phy0>;
388			};
389
390			port@2 {
391				reg = <2>;
392				label = "lan1";
393				phy-handle = <&switch0phy1>;
394			};
395
396			port@3 {
397				reg = <3>;
398				label = "lan4";
399				phy-handle = <&switch0phy2>;
400			};
401
402			port@4 {
403				reg = <4>;
404				label = "lan3";
405				phy-handle = <&switch0phy3>;
406			};
407
408			port@5 {
409				reg = <5>;
410				label = "cpu";
411				ethernet = <&cp1_eth2>;
412				phy-mode = "2500base-x";
413				managed = "in-band-status";
414			};
415		};
416
417		mdio {
418			#address-cells = <1>;
419			#size-cells = <0>;
420
421			switch0phy0: switch0phy0@11 {
422				reg = <0x11>;
423			};
424
425			switch0phy1: switch0phy1@12 {
426				reg = <0x12>;
427			};
428
429			switch0phy2: switch0phy2@13 {
430				reg = <0x13>;
431			};
432
433			switch0phy3: switch0phy3@14 {
434				reg = <0x14>;
435			};
436		};
437	};
438};
439
440&cp1_ethernet {
441	status = "okay";
442};
443
444/* 1G copper */
445&cp1_eth1 {
446	status = "okay";
447	phy-mode = "sgmii";
448	phy = <&ge_phy>;
449	phys = <&cp1_comphy3 1>;
450};
451
452/* Switch uplink */
453&cp1_eth2 {
454	status = "okay";
455	phy-mode = "2500base-x";
456	phys = <&cp1_comphy5 2>;
457	managed = "in-band-status";
458};
459
460&cp1_spi1 {
461	pinctrl-names = "default";
462	pinctrl-0 = <&cp1_spi1_pins>;
463	status = "okay";
464
465	spi-flash@0 {
466		compatible = "st,w25q32";
467		spi-max-frequency = <50000000>;
468		reg = <0>;
469	};
470};
471
472&cp1_comphy2 {
473	cp1_usbh0_con: connector {
474		compatible = "usb-a-connector";
475		phy-supply = <&v_5v0_usb3_hst_vbus>;
476	};
477};
478
479&cp1_usb3_0 {
480	phys = <&cp1_comphy2 0>;
481	phy-names = "cp1-usb3h0-comphy";
482	status = "okay";
483};
484