1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2018 MediaTek Inc. 4 5 #include <linux/bitops.h> 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/errno.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/mailbox_controller.h> 17 #include <linux/mailbox/mtk-cmdq-mailbox.h> 18 #include <linux/of_device.h> 19 20 #define CMDQ_OP_CODE_MASK (0xff << CMDQ_OP_CODE_SHIFT) 21 #define CMDQ_NUM_CMD(t) (t->cmd_buf_size / CMDQ_INST_SIZE) 22 23 #define CMDQ_CURR_IRQ_STATUS 0x10 24 #define CMDQ_SYNC_TOKEN_UPDATE 0x68 25 #define CMDQ_THR_SLOT_CYCLES 0x30 26 #define CMDQ_THR_BASE 0x100 27 #define CMDQ_THR_SIZE 0x80 28 #define CMDQ_THR_WARM_RESET 0x00 29 #define CMDQ_THR_ENABLE_TASK 0x04 30 #define CMDQ_THR_SUSPEND_TASK 0x08 31 #define CMDQ_THR_CURR_STATUS 0x0c 32 #define CMDQ_THR_IRQ_STATUS 0x10 33 #define CMDQ_THR_IRQ_ENABLE 0x14 34 #define CMDQ_THR_CURR_ADDR 0x20 35 #define CMDQ_THR_END_ADDR 0x24 36 #define CMDQ_THR_WAIT_TOKEN 0x30 37 #define CMDQ_THR_PRIORITY 0x40 38 39 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 40 #define CMDQ_THR_ENABLED 0x1 41 #define CMDQ_THR_DISABLED 0x0 42 #define CMDQ_THR_SUSPEND 0x1 43 #define CMDQ_THR_RESUME 0x0 44 #define CMDQ_THR_STATUS_SUSPENDED BIT(1) 45 #define CMDQ_THR_DO_WARM_RESET BIT(0) 46 #define CMDQ_THR_IRQ_DONE 0x1 47 #define CMDQ_THR_IRQ_ERROR 0x12 48 #define CMDQ_THR_IRQ_EN (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE) 49 #define CMDQ_THR_IS_WAITING BIT(31) 50 51 #define CMDQ_JUMP_BY_OFFSET 0x10000000 52 #define CMDQ_JUMP_BY_PA 0x10000001 53 54 struct cmdq_thread { 55 struct mbox_chan *chan; 56 void __iomem *base; 57 struct list_head task_busy_list; 58 u32 priority; 59 }; 60 61 struct cmdq_task { 62 struct cmdq *cmdq; 63 struct list_head list_entry; 64 dma_addr_t pa_base; 65 struct cmdq_thread *thread; 66 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */ 67 }; 68 69 struct cmdq { 70 struct mbox_controller mbox; 71 void __iomem *base; 72 u32 irq; 73 u32 thread_nr; 74 u32 irq_mask; 75 struct cmdq_thread *thread; 76 struct clk *clock; 77 bool suspended; 78 }; 79 80 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) 81 { 82 u32 status; 83 84 writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK); 85 86 /* If already disabled, treat as suspended successful. */ 87 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 88 return 0; 89 90 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS, 91 status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) { 92 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n", 93 (u32)(thread->base - cmdq->base)); 94 return -EFAULT; 95 } 96 97 return 0; 98 } 99 100 static void cmdq_thread_resume(struct cmdq_thread *thread) 101 { 102 writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK); 103 } 104 105 static void cmdq_init(struct cmdq *cmdq) 106 { 107 int i; 108 109 WARN_ON(clk_enable(cmdq->clock) < 0); 110 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); 111 for (i = 0; i <= CMDQ_MAX_EVENT; i++) 112 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); 113 clk_disable(cmdq->clock); 114 } 115 116 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) 117 { 118 u32 warm_reset; 119 120 writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET); 121 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET, 122 warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET), 123 0, 10)) { 124 dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n", 125 (u32)(thread->base - cmdq->base)); 126 return -EFAULT; 127 } 128 129 return 0; 130 } 131 132 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread) 133 { 134 cmdq_thread_reset(cmdq, thread); 135 writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK); 136 } 137 138 /* notify GCE to re-fetch commands by setting GCE thread PC */ 139 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread) 140 { 141 writel(readl(thread->base + CMDQ_THR_CURR_ADDR), 142 thread->base + CMDQ_THR_CURR_ADDR); 143 } 144 145 static void cmdq_task_insert_into_thread(struct cmdq_task *task) 146 { 147 struct device *dev = task->cmdq->mbox.dev; 148 struct cmdq_thread *thread = task->thread; 149 struct cmdq_task *prev_task = list_last_entry( 150 &thread->task_busy_list, typeof(*task), list_entry); 151 u64 *prev_task_base = prev_task->pkt->va_base; 152 153 /* let previous task jump to this task */ 154 dma_sync_single_for_cpu(dev, prev_task->pa_base, 155 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 156 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = 157 (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base; 158 dma_sync_single_for_device(dev, prev_task->pa_base, 159 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 160 161 cmdq_thread_invalidate_fetched_data(thread); 162 } 163 164 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread) 165 { 166 return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING; 167 } 168 169 static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status sta) 170 { 171 struct cmdq_task_cb *cb = &task->pkt->async_cb; 172 struct cmdq_cb_data data; 173 174 WARN_ON(cb->cb == (cmdq_async_flush_cb)NULL); 175 data.sta = sta; 176 data.data = cb->data; 177 cb->cb(data); 178 179 list_del(&task->list_entry); 180 } 181 182 static void cmdq_task_handle_error(struct cmdq_task *task) 183 { 184 struct cmdq_thread *thread = task->thread; 185 struct cmdq_task *next_task; 186 187 dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task); 188 WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0); 189 next_task = list_first_entry_or_null(&thread->task_busy_list, 190 struct cmdq_task, list_entry); 191 if (next_task) 192 writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); 193 cmdq_thread_resume(thread); 194 } 195 196 static void cmdq_thread_irq_handler(struct cmdq *cmdq, 197 struct cmdq_thread *thread) 198 { 199 struct cmdq_task *task, *tmp, *curr_task = NULL; 200 u32 curr_pa, irq_flag, task_end_pa; 201 bool err; 202 203 irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS); 204 writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS); 205 206 /* 207 * When ISR call this function, another CPU core could run 208 * "release task" right before we acquire the spin lock, and thus 209 * reset / disable this GCE thread, so we need to check the enable 210 * bit of this GCE thread. 211 */ 212 if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED)) 213 return; 214 215 if (irq_flag & CMDQ_THR_IRQ_ERROR) 216 err = true; 217 else if (irq_flag & CMDQ_THR_IRQ_DONE) 218 err = false; 219 else 220 return; 221 222 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); 223 224 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 225 list_entry) { 226 task_end_pa = task->pa_base + task->pkt->cmd_buf_size; 227 if (curr_pa >= task->pa_base && curr_pa < task_end_pa) 228 curr_task = task; 229 230 if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) { 231 cmdq_task_exec_done(task, CMDQ_CB_NORMAL); 232 kfree(task); 233 } else if (err) { 234 cmdq_task_exec_done(task, CMDQ_CB_ERROR); 235 cmdq_task_handle_error(curr_task); 236 kfree(task); 237 } 238 239 if (curr_task) 240 break; 241 } 242 243 if (list_empty(&thread->task_busy_list)) { 244 cmdq_thread_disable(cmdq, thread); 245 clk_disable(cmdq->clock); 246 } 247 } 248 249 static irqreturn_t cmdq_irq_handler(int irq, void *dev) 250 { 251 struct cmdq *cmdq = dev; 252 unsigned long irq_status, flags = 0L; 253 int bit; 254 255 irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask; 256 if (!(irq_status ^ cmdq->irq_mask)) 257 return IRQ_NONE; 258 259 for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) { 260 struct cmdq_thread *thread = &cmdq->thread[bit]; 261 262 spin_lock_irqsave(&thread->chan->lock, flags); 263 cmdq_thread_irq_handler(cmdq, thread); 264 spin_unlock_irqrestore(&thread->chan->lock, flags); 265 } 266 267 return IRQ_HANDLED; 268 } 269 270 static int cmdq_suspend(struct device *dev) 271 { 272 struct cmdq *cmdq = dev_get_drvdata(dev); 273 struct cmdq_thread *thread; 274 int i; 275 bool task_running = false; 276 277 cmdq->suspended = true; 278 279 for (i = 0; i < cmdq->thread_nr; i++) { 280 thread = &cmdq->thread[i]; 281 if (!list_empty(&thread->task_busy_list)) { 282 task_running = true; 283 break; 284 } 285 } 286 287 if (task_running) 288 dev_warn(dev, "exist running task(s) in suspend\n"); 289 290 clk_unprepare(cmdq->clock); 291 292 return 0; 293 } 294 295 static int cmdq_resume(struct device *dev) 296 { 297 struct cmdq *cmdq = dev_get_drvdata(dev); 298 299 WARN_ON(clk_prepare(cmdq->clock) < 0); 300 cmdq->suspended = false; 301 return 0; 302 } 303 304 static int cmdq_remove(struct platform_device *pdev) 305 { 306 struct cmdq *cmdq = platform_get_drvdata(pdev); 307 308 clk_unprepare(cmdq->clock); 309 310 return 0; 311 } 312 313 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) 314 { 315 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; 316 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 317 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 318 struct cmdq_task *task; 319 unsigned long curr_pa, end_pa; 320 321 /* Client should not flush new tasks if suspended. */ 322 WARN_ON(cmdq->suspended); 323 324 task = kzalloc(sizeof(*task), GFP_ATOMIC); 325 if (!task) 326 return -ENOMEM; 327 328 task->cmdq = cmdq; 329 INIT_LIST_HEAD(&task->list_entry); 330 task->pa_base = pkt->pa_base; 331 task->thread = thread; 332 task->pkt = pkt; 333 334 if (list_empty(&thread->task_busy_list)) { 335 WARN_ON(clk_enable(cmdq->clock) < 0); 336 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0); 337 338 writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR); 339 writel(task->pa_base + pkt->cmd_buf_size, 340 thread->base + CMDQ_THR_END_ADDR); 341 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); 342 writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE); 343 writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK); 344 } else { 345 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 346 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR); 347 end_pa = readl(thread->base + CMDQ_THR_END_ADDR); 348 /* check boundary */ 349 if (curr_pa == end_pa - CMDQ_INST_SIZE || 350 curr_pa == end_pa) { 351 /* set to this task directly */ 352 writel(task->pa_base, 353 thread->base + CMDQ_THR_CURR_ADDR); 354 } else { 355 cmdq_task_insert_into_thread(task); 356 smp_mb(); /* modify jump before enable thread */ 357 } 358 writel(task->pa_base + pkt->cmd_buf_size, 359 thread->base + CMDQ_THR_END_ADDR); 360 cmdq_thread_resume(thread); 361 } 362 list_move_tail(&task->list_entry, &thread->task_busy_list); 363 364 return 0; 365 } 366 367 static int cmdq_mbox_startup(struct mbox_chan *chan) 368 { 369 return 0; 370 } 371 372 static void cmdq_mbox_shutdown(struct mbox_chan *chan) 373 { 374 } 375 376 static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout) 377 { 378 struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv; 379 struct cmdq_task_cb *cb; 380 struct cmdq_cb_data data; 381 struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev); 382 struct cmdq_task *task, *tmp; 383 unsigned long flags; 384 u32 enable; 385 386 spin_lock_irqsave(&thread->chan->lock, flags); 387 if (list_empty(&thread->task_busy_list)) 388 goto out; 389 390 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 391 if (!cmdq_thread_is_in_wfe(thread)) 392 goto wait; 393 394 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 395 list_entry) { 396 cb = &task->pkt->async_cb; 397 if (cb->cb) { 398 data.sta = CMDQ_CB_ERROR; 399 data.data = cb->data; 400 cb->cb(data); 401 } 402 list_del(&task->list_entry); 403 kfree(task); 404 } 405 406 cmdq_thread_resume(thread); 407 cmdq_thread_disable(cmdq, thread); 408 clk_disable(cmdq->clock); 409 410 out: 411 spin_unlock_irqrestore(&thread->chan->lock, flags); 412 return 0; 413 414 wait: 415 cmdq_thread_resume(thread); 416 spin_unlock_irqrestore(&thread->chan->lock, flags); 417 if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK, 418 enable, enable == 0, 1, timeout)) { 419 dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n", 420 (u32)(thread->base - cmdq->base)); 421 422 return -EFAULT; 423 } 424 return 0; 425 } 426 427 static const struct mbox_chan_ops cmdq_mbox_chan_ops = { 428 .send_data = cmdq_mbox_send_data, 429 .startup = cmdq_mbox_startup, 430 .shutdown = cmdq_mbox_shutdown, 431 .flush = cmdq_mbox_flush, 432 }; 433 434 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox, 435 const struct of_phandle_args *sp) 436 { 437 int ind = sp->args[0]; 438 struct cmdq_thread *thread; 439 440 if (ind >= mbox->num_chans) 441 return ERR_PTR(-EINVAL); 442 443 thread = (struct cmdq_thread *)mbox->chans[ind].con_priv; 444 thread->priority = sp->args[1]; 445 thread->chan = &mbox->chans[ind]; 446 447 return &mbox->chans[ind]; 448 } 449 450 static int cmdq_probe(struct platform_device *pdev) 451 { 452 struct device *dev = &pdev->dev; 453 struct resource *res; 454 struct cmdq *cmdq; 455 int err, i; 456 457 cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); 458 if (!cmdq) 459 return -ENOMEM; 460 461 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 462 cmdq->base = devm_ioremap_resource(dev, res); 463 if (IS_ERR(cmdq->base)) { 464 dev_err(dev, "failed to ioremap gce\n"); 465 return PTR_ERR(cmdq->base); 466 } 467 468 cmdq->irq = platform_get_irq(pdev, 0); 469 if (!cmdq->irq) { 470 dev_err(dev, "failed to get irq\n"); 471 return -EINVAL; 472 } 473 474 cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev); 475 cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); 476 err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, 477 "mtk_cmdq", cmdq); 478 if (err < 0) { 479 dev_err(dev, "failed to register ISR (%d)\n", err); 480 return err; 481 } 482 483 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n", 484 dev, cmdq->base, cmdq->irq); 485 486 cmdq->clock = devm_clk_get(dev, "gce"); 487 if (IS_ERR(cmdq->clock)) { 488 dev_err(dev, "failed to get gce clk\n"); 489 return PTR_ERR(cmdq->clock); 490 } 491 492 cmdq->mbox.dev = dev; 493 cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, 494 sizeof(*cmdq->mbox.chans), GFP_KERNEL); 495 if (!cmdq->mbox.chans) 496 return -ENOMEM; 497 498 cmdq->mbox.num_chans = cmdq->thread_nr; 499 cmdq->mbox.ops = &cmdq_mbox_chan_ops; 500 cmdq->mbox.of_xlate = cmdq_xlate; 501 502 /* make use of TXDONE_BY_ACK */ 503 cmdq->mbox.txdone_irq = false; 504 cmdq->mbox.txdone_poll = false; 505 506 cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr, 507 sizeof(*cmdq->thread), GFP_KERNEL); 508 if (!cmdq->thread) 509 return -ENOMEM; 510 511 for (i = 0; i < cmdq->thread_nr; i++) { 512 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE + 513 CMDQ_THR_SIZE * i; 514 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list); 515 cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i]; 516 } 517 518 err = devm_mbox_controller_register(dev, &cmdq->mbox); 519 if (err < 0) { 520 dev_err(dev, "failed to register mailbox: %d\n", err); 521 return err; 522 } 523 524 platform_set_drvdata(pdev, cmdq); 525 WARN_ON(clk_prepare(cmdq->clock) < 0); 526 527 cmdq_init(cmdq); 528 529 return 0; 530 } 531 532 static const struct dev_pm_ops cmdq_pm_ops = { 533 .suspend = cmdq_suspend, 534 .resume = cmdq_resume, 535 }; 536 537 static const struct of_device_id cmdq_of_ids[] = { 538 {.compatible = "mediatek,mt8173-gce", .data = (void *)16}, 539 {.compatible = "mediatek,mt8183-gce", .data = (void *)24}, 540 {} 541 }; 542 543 static struct platform_driver cmdq_drv = { 544 .probe = cmdq_probe, 545 .remove = cmdq_remove, 546 .driver = { 547 .name = "mtk_cmdq", 548 .pm = &cmdq_pm_ops, 549 .of_match_table = cmdq_of_ids, 550 } 551 }; 552 553 static int __init cmdq_drv_init(void) 554 { 555 return platform_driver_register(&cmdq_drv); 556 } 557 558 static void __exit cmdq_drv_exit(void) 559 { 560 platform_driver_unregister(&cmdq_drv); 561 } 562 563 subsys_initcall(cmdq_drv_init); 564 module_exit(cmdq_drv_exit); 565 566 MODULE_LICENSE("GPL v2"); 567