1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 67 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 68 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 69 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 70 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 71 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 72 * 73 * Features supported by this driver: 74 * Software PEC no 75 * Hardware PEC yes 76 * Block buffer yes 77 * Block process call transaction yes 78 * I2C block read transaction yes (doesn't use the block buffer) 79 * Slave mode no 80 * SMBus Host Notify yes 81 * Interrupt processing yes 82 * 83 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 84 */ 85 86 #include <linux/interrupt.h> 87 #include <linux/module.h> 88 #include <linux/pci.h> 89 #include <linux/kernel.h> 90 #include <linux/stddef.h> 91 #include <linux/delay.h> 92 #include <linux/ioport.h> 93 #include <linux/init.h> 94 #include <linux/i2c.h> 95 #include <linux/i2c-smbus.h> 96 #include <linux/acpi.h> 97 #include <linux/io.h> 98 #include <linux/dmi.h> 99 #include <linux/slab.h> 100 #include <linux/string.h> 101 #include <linux/wait.h> 102 #include <linux/err.h> 103 #include <linux/platform_device.h> 104 #include <linux/platform_data/itco_wdt.h> 105 #include <linux/pm_runtime.h> 106 107 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 108 #include <linux/gpio/machine.h> 109 #include <linux/platform_data/i2c-mux-gpio.h> 110 #endif 111 112 /* I801 SMBus address offsets */ 113 #define SMBHSTSTS(p) (0 + (p)->smba) 114 #define SMBHSTCNT(p) (2 + (p)->smba) 115 #define SMBHSTCMD(p) (3 + (p)->smba) 116 #define SMBHSTADD(p) (4 + (p)->smba) 117 #define SMBHSTDAT0(p) (5 + (p)->smba) 118 #define SMBHSTDAT1(p) (6 + (p)->smba) 119 #define SMBBLKDAT(p) (7 + (p)->smba) 120 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 121 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 122 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 123 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 124 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 125 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 126 127 /* PCI Address Constants */ 128 #define SMBBAR 4 129 #define SMBPCICTL 0x004 130 #define SMBPCISTS 0x006 131 #define SMBHSTCFG 0x040 132 #define TCOBASE 0x050 133 #define TCOCTL 0x054 134 135 #define SBREG_BAR 0x10 136 #define SBREG_SMBCTRL 0xc6000c 137 #define SBREG_SMBCTRL_DNV 0xcf000c 138 139 /* Host status bits for SMBPCISTS */ 140 #define SMBPCISTS_INTS BIT(3) 141 142 /* Control bits for SMBPCICTL */ 143 #define SMBPCICTL_INTDIS BIT(10) 144 145 /* Host configuration bits for SMBHSTCFG */ 146 #define SMBHSTCFG_HST_EN BIT(0) 147 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 148 #define SMBHSTCFG_I2C_EN BIT(2) 149 #define SMBHSTCFG_SPD_WD BIT(4) 150 151 /* TCO configuration bits for TCOCTL */ 152 #define TCOCTL_EN BIT(8) 153 154 /* Auxiliary status register bits, ICH4+ only */ 155 #define SMBAUXSTS_CRCE BIT(0) 156 #define SMBAUXSTS_STCO BIT(1) 157 158 /* Auxiliary control register bits, ICH4+ only */ 159 #define SMBAUXCTL_CRC BIT(0) 160 #define SMBAUXCTL_E32B BIT(1) 161 162 /* Other settings */ 163 #define MAX_RETRIES 400 164 165 /* I801 command constants */ 166 #define I801_QUICK 0x00 167 #define I801_BYTE 0x04 168 #define I801_BYTE_DATA 0x08 169 #define I801_WORD_DATA 0x0C 170 #define I801_PROC_CALL 0x10 /* unimplemented */ 171 #define I801_BLOCK_DATA 0x14 172 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 173 #define I801_BLOCK_PROC_CALL 0x1C 174 175 /* I801 Host Control register bits */ 176 #define SMBHSTCNT_INTREN BIT(0) 177 #define SMBHSTCNT_KILL BIT(1) 178 #define SMBHSTCNT_LAST_BYTE BIT(5) 179 #define SMBHSTCNT_START BIT(6) 180 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 181 182 /* I801 Hosts Status register bits */ 183 #define SMBHSTSTS_BYTE_DONE BIT(7) 184 #define SMBHSTSTS_INUSE_STS BIT(6) 185 #define SMBHSTSTS_SMBALERT_STS BIT(5) 186 #define SMBHSTSTS_FAILED BIT(4) 187 #define SMBHSTSTS_BUS_ERR BIT(3) 188 #define SMBHSTSTS_DEV_ERR BIT(2) 189 #define SMBHSTSTS_INTR BIT(1) 190 #define SMBHSTSTS_HOST_BUSY BIT(0) 191 192 /* Host Notify Status register bits */ 193 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 194 195 /* Host Notify Command register bits */ 196 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 197 198 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 199 SMBHSTSTS_DEV_ERR) 200 201 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 202 STATUS_ERROR_FLAGS) 203 204 /* Older devices have their ID defined in <linux/pci_ids.h> */ 205 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 207 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 208 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 209 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 210 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 212 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 216 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 217 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 218 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 219 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 220 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 221 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 222 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 223 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 224 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 225 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 226 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 227 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 228 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 229 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 230 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 233 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 234 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 235 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 236 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 237 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 238 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 239 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 241 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 242 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 243 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 244 245 struct i801_mux_config { 246 char *gpio_chip; 247 unsigned values[3]; 248 int n_values; 249 unsigned classes[3]; 250 unsigned gpios[2]; /* Relative to gpio_chip->base */ 251 int n_gpios; 252 }; 253 254 struct i801_priv { 255 struct i2c_adapter adapter; 256 unsigned long smba; 257 unsigned char original_hstcfg; 258 unsigned char original_slvcmd; 259 struct pci_dev *pci_dev; 260 unsigned int features; 261 262 /* isr processing */ 263 wait_queue_head_t waitq; 264 u8 status; 265 266 /* Command state used by isr for byte-by-byte block transactions */ 267 u8 cmd; 268 bool is_read; 269 int count; 270 int len; 271 u8 *data; 272 273 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 274 const struct i801_mux_config *mux_drvdata; 275 struct platform_device *mux_pdev; 276 struct gpiod_lookup_table *lookup; 277 #endif 278 struct platform_device *tco_pdev; 279 280 /* 281 * If set to true the host controller registers are reserved for 282 * ACPI AML use. Protected by acpi_lock. 283 */ 284 bool acpi_reserved; 285 struct mutex acpi_lock; 286 }; 287 288 #define FEATURE_SMBUS_PEC BIT(0) 289 #define FEATURE_BLOCK_BUFFER BIT(1) 290 #define FEATURE_BLOCK_PROC BIT(2) 291 #define FEATURE_I2C_BLOCK_READ BIT(3) 292 #define FEATURE_IRQ BIT(4) 293 #define FEATURE_HOST_NOTIFY BIT(5) 294 /* Not really a feature, but it's convenient to handle it as such */ 295 #define FEATURE_IDF BIT(15) 296 #define FEATURE_TCO_SPT BIT(16) 297 #define FEATURE_TCO_CNL BIT(17) 298 299 static const char *i801_feature_names[] = { 300 "SMBus PEC", 301 "Block buffer", 302 "Block process call", 303 "I2C block read", 304 "Interrupt", 305 "SMBus Host Notify", 306 }; 307 308 static unsigned int disable_features; 309 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 310 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 311 "\t\t 0x01 disable SMBus PEC\n" 312 "\t\t 0x02 disable the block buffer\n" 313 "\t\t 0x08 disable the I2C block read functionality\n" 314 "\t\t 0x10 don't use interrupts\n" 315 "\t\t 0x20 disable SMBus Host Notify "); 316 317 /* Make sure the SMBus host is ready to start transmitting. 318 Return 0 if it is, -EBUSY if it is not. */ 319 static int i801_check_pre(struct i801_priv *priv) 320 { 321 int status; 322 323 status = inb_p(SMBHSTSTS(priv)); 324 if (status & SMBHSTSTS_HOST_BUSY) { 325 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 326 return -EBUSY; 327 } 328 329 status &= STATUS_FLAGS; 330 if (status) { 331 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 332 status); 333 outb_p(status, SMBHSTSTS(priv)); 334 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 335 if (status) { 336 dev_err(&priv->pci_dev->dev, 337 "Failed clearing status flags (%02x)\n", 338 status); 339 return -EBUSY; 340 } 341 } 342 343 /* 344 * Clear CRC status if needed. 345 * During normal operation, i801_check_post() takes care 346 * of it after every operation. We do it here only in case 347 * the hardware was already in this state when the driver 348 * started. 349 */ 350 if (priv->features & FEATURE_SMBUS_PEC) { 351 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 352 if (status) { 353 dev_dbg(&priv->pci_dev->dev, 354 "Clearing aux status flags (%02x)\n", status); 355 outb_p(status, SMBAUXSTS(priv)); 356 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 357 if (status) { 358 dev_err(&priv->pci_dev->dev, 359 "Failed clearing aux status flags (%02x)\n", 360 status); 361 return -EBUSY; 362 } 363 } 364 } 365 366 return 0; 367 } 368 369 /* 370 * Convert the status register to an error code, and clear it. 371 * Note that status only contains the bits we want to clear, not the 372 * actual register value. 373 */ 374 static int i801_check_post(struct i801_priv *priv, int status) 375 { 376 int result = 0; 377 378 /* 379 * If the SMBus is still busy, we give up 380 * Note: This timeout condition only happens when using polling 381 * transactions. For interrupt operation, NAK/timeout is indicated by 382 * DEV_ERR. 383 */ 384 if (unlikely(status < 0)) { 385 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 386 /* try to stop the current command */ 387 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 388 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 389 SMBHSTCNT(priv)); 390 usleep_range(1000, 2000); 391 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 392 SMBHSTCNT(priv)); 393 394 /* Check if it worked */ 395 status = inb_p(SMBHSTSTS(priv)); 396 if ((status & SMBHSTSTS_HOST_BUSY) || 397 !(status & SMBHSTSTS_FAILED)) 398 dev_err(&priv->pci_dev->dev, 399 "Failed terminating the transaction\n"); 400 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 401 return -ETIMEDOUT; 402 } 403 404 if (status & SMBHSTSTS_FAILED) { 405 result = -EIO; 406 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 407 } 408 if (status & SMBHSTSTS_DEV_ERR) { 409 /* 410 * This may be a PEC error, check and clear it. 411 * 412 * AUXSTS is handled differently from HSTSTS. 413 * For HSTSTS, i801_isr() or i801_wait_intr() 414 * has already cleared the error bits in hardware, 415 * and we are passed a copy of the original value 416 * in "status". 417 * For AUXSTS, the hardware register is left 418 * for us to handle here. 419 * This is asymmetric, slightly iffy, but safe, 420 * since all this code is serialized and the CRCE 421 * bit is harmless as long as it's cleared before 422 * the next operation. 423 */ 424 if ((priv->features & FEATURE_SMBUS_PEC) && 425 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 426 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 427 result = -EBADMSG; 428 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 429 } else { 430 result = -ENXIO; 431 dev_dbg(&priv->pci_dev->dev, "No response\n"); 432 } 433 } 434 if (status & SMBHSTSTS_BUS_ERR) { 435 result = -EAGAIN; 436 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 437 } 438 439 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 440 outb_p(status, SMBHSTSTS(priv)); 441 442 return result; 443 } 444 445 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 446 static int i801_wait_intr(struct i801_priv *priv) 447 { 448 int timeout = 0; 449 int status; 450 451 /* We will always wait for a fraction of a second! */ 452 do { 453 usleep_range(250, 500); 454 status = inb_p(SMBHSTSTS(priv)); 455 } while (((status & SMBHSTSTS_HOST_BUSY) || 456 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 457 (timeout++ < MAX_RETRIES)); 458 459 if (timeout > MAX_RETRIES) { 460 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 461 return -ETIMEDOUT; 462 } 463 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 464 } 465 466 /* Wait for either BYTE_DONE or an error flag being set */ 467 static int i801_wait_byte_done(struct i801_priv *priv) 468 { 469 int timeout = 0; 470 int status; 471 472 /* We will always wait for a fraction of a second! */ 473 do { 474 usleep_range(250, 500); 475 status = inb_p(SMBHSTSTS(priv)); 476 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 477 (timeout++ < MAX_RETRIES)); 478 479 if (timeout > MAX_RETRIES) { 480 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 481 return -ETIMEDOUT; 482 } 483 return status & STATUS_ERROR_FLAGS; 484 } 485 486 static int i801_transaction(struct i801_priv *priv, int xact) 487 { 488 int status; 489 int result; 490 const struct i2c_adapter *adap = &priv->adapter; 491 492 result = i801_check_pre(priv); 493 if (result < 0) 494 return result; 495 496 if (priv->features & FEATURE_IRQ) { 497 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 498 SMBHSTCNT(priv)); 499 result = wait_event_timeout(priv->waitq, 500 (status = priv->status), 501 adap->timeout); 502 if (!result) { 503 status = -ETIMEDOUT; 504 dev_warn(&priv->pci_dev->dev, 505 "Timeout waiting for interrupt!\n"); 506 } 507 priv->status = 0; 508 return i801_check_post(priv, status); 509 } 510 511 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 512 * SMBSCMD are passed in xact */ 513 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 514 515 status = i801_wait_intr(priv); 516 return i801_check_post(priv, status); 517 } 518 519 static int i801_block_transaction_by_block(struct i801_priv *priv, 520 union i2c_smbus_data *data, 521 char read_write, int command, 522 int hwpec) 523 { 524 int i, len; 525 int status; 526 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; 527 528 switch (command) { 529 case I2C_SMBUS_BLOCK_PROC_CALL: 530 xact |= I801_BLOCK_PROC_CALL; 531 break; 532 case I2C_SMBUS_BLOCK_DATA: 533 xact |= I801_BLOCK_DATA; 534 break; 535 default: 536 return -EOPNOTSUPP; 537 } 538 539 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 540 541 /* Use 32-byte buffer to process this transaction */ 542 if (read_write == I2C_SMBUS_WRITE) { 543 len = data->block[0]; 544 outb_p(len, SMBHSTDAT0(priv)); 545 for (i = 0; i < len; i++) 546 outb_p(data->block[i+1], SMBBLKDAT(priv)); 547 } 548 549 status = i801_transaction(priv, xact); 550 if (status) 551 return status; 552 553 if (read_write == I2C_SMBUS_READ || 554 command == I2C_SMBUS_BLOCK_PROC_CALL) { 555 len = inb_p(SMBHSTDAT0(priv)); 556 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 557 return -EPROTO; 558 559 data->block[0] = len; 560 for (i = 0; i < len; i++) 561 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 562 } 563 return 0; 564 } 565 566 static void i801_isr_byte_done(struct i801_priv *priv) 567 { 568 if (priv->is_read) { 569 /* For SMBus block reads, length is received with first byte */ 570 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 571 (priv->count == 0)) { 572 priv->len = inb_p(SMBHSTDAT0(priv)); 573 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 574 dev_err(&priv->pci_dev->dev, 575 "Illegal SMBus block read size %d\n", 576 priv->len); 577 /* FIXME: Recover */ 578 priv->len = I2C_SMBUS_BLOCK_MAX; 579 } else { 580 dev_dbg(&priv->pci_dev->dev, 581 "SMBus block read size is %d\n", 582 priv->len); 583 } 584 priv->data[-1] = priv->len; 585 } 586 587 /* Read next byte */ 588 if (priv->count < priv->len) 589 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 590 else 591 dev_dbg(&priv->pci_dev->dev, 592 "Discarding extra byte on block read\n"); 593 594 /* Set LAST_BYTE for last byte of read transaction */ 595 if (priv->count == priv->len - 1) 596 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 597 SMBHSTCNT(priv)); 598 } else if (priv->count < priv->len - 1) { 599 /* Write next byte, except for IRQ after last byte */ 600 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 601 } 602 603 /* Clear BYTE_DONE to continue with next byte */ 604 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 605 } 606 607 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 608 { 609 unsigned short addr; 610 611 addr = inb_p(SMBNTFDADD(priv)) >> 1; 612 613 /* 614 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 615 * always returns 0. Our current implementation doesn't provide 616 * data, so we just ignore it. 617 */ 618 i2c_handle_smbus_host_notify(&priv->adapter, addr); 619 620 /* clear Host Notify bit and return */ 621 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 622 return IRQ_HANDLED; 623 } 624 625 /* 626 * There are three kinds of interrupts: 627 * 628 * 1) i801 signals transaction completion with one of these interrupts: 629 * INTR - Success 630 * DEV_ERR - Invalid command, NAK or communication timeout 631 * BUS_ERR - SMI# transaction collision 632 * FAILED - transaction was canceled due to a KILL request 633 * When any of these occur, update ->status and wake up the waitq. 634 * ->status must be cleared before kicking off the next transaction. 635 * 636 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 637 * occurs for each byte of a byte-by-byte to prepare the next byte. 638 * 639 * 3) Host Notify interrupts 640 */ 641 static irqreturn_t i801_isr(int irq, void *dev_id) 642 { 643 struct i801_priv *priv = dev_id; 644 u16 pcists; 645 u8 status; 646 647 /* Confirm this is our interrupt */ 648 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 649 if (!(pcists & SMBPCISTS_INTS)) 650 return IRQ_NONE; 651 652 if (priv->features & FEATURE_HOST_NOTIFY) { 653 status = inb_p(SMBSLVSTS(priv)); 654 if (status & SMBSLVSTS_HST_NTFY_STS) 655 return i801_host_notify_isr(priv); 656 } 657 658 status = inb_p(SMBHSTSTS(priv)); 659 if (status & SMBHSTSTS_BYTE_DONE) 660 i801_isr_byte_done(priv); 661 662 /* 663 * Clear irq sources and report transaction result. 664 * ->status must be cleared before the next transaction is started. 665 */ 666 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 667 if (status) { 668 outb_p(status, SMBHSTSTS(priv)); 669 priv->status = status; 670 wake_up(&priv->waitq); 671 } 672 673 return IRQ_HANDLED; 674 } 675 676 /* 677 * For "byte-by-byte" block transactions: 678 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 679 * I2C read uses cmd=I801_I2C_BLOCK_DATA 680 */ 681 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 682 union i2c_smbus_data *data, 683 char read_write, int command, 684 int hwpec) 685 { 686 int i, len; 687 int smbcmd; 688 int status; 689 int result; 690 const struct i2c_adapter *adap = &priv->adapter; 691 692 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 693 return -EOPNOTSUPP; 694 695 result = i801_check_pre(priv); 696 if (result < 0) 697 return result; 698 699 len = data->block[0]; 700 701 if (read_write == I2C_SMBUS_WRITE) { 702 outb_p(len, SMBHSTDAT0(priv)); 703 outb_p(data->block[1], SMBBLKDAT(priv)); 704 } 705 706 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 707 read_write == I2C_SMBUS_READ) 708 smbcmd = I801_I2C_BLOCK_DATA; 709 else 710 smbcmd = I801_BLOCK_DATA; 711 712 if (priv->features & FEATURE_IRQ) { 713 priv->is_read = (read_write == I2C_SMBUS_READ); 714 if (len == 1 && priv->is_read) 715 smbcmd |= SMBHSTCNT_LAST_BYTE; 716 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 717 priv->len = len; 718 priv->count = 0; 719 priv->data = &data->block[1]; 720 721 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 722 result = wait_event_timeout(priv->waitq, 723 (status = priv->status), 724 adap->timeout); 725 if (!result) { 726 status = -ETIMEDOUT; 727 dev_warn(&priv->pci_dev->dev, 728 "Timeout waiting for interrupt!\n"); 729 } 730 priv->status = 0; 731 return i801_check_post(priv, status); 732 } 733 734 for (i = 1; i <= len; i++) { 735 if (i == len && read_write == I2C_SMBUS_READ) 736 smbcmd |= SMBHSTCNT_LAST_BYTE; 737 outb_p(smbcmd, SMBHSTCNT(priv)); 738 739 if (i == 1) 740 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 741 SMBHSTCNT(priv)); 742 743 status = i801_wait_byte_done(priv); 744 if (status) 745 goto exit; 746 747 if (i == 1 && read_write == I2C_SMBUS_READ 748 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 749 len = inb_p(SMBHSTDAT0(priv)); 750 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 751 dev_err(&priv->pci_dev->dev, 752 "Illegal SMBus block read size %d\n", 753 len); 754 /* Recover */ 755 while (inb_p(SMBHSTSTS(priv)) & 756 SMBHSTSTS_HOST_BUSY) 757 outb_p(SMBHSTSTS_BYTE_DONE, 758 SMBHSTSTS(priv)); 759 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 760 return -EPROTO; 761 } 762 data->block[0] = len; 763 } 764 765 /* Retrieve/store value in SMBBLKDAT */ 766 if (read_write == I2C_SMBUS_READ) 767 data->block[i] = inb_p(SMBBLKDAT(priv)); 768 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 769 outb_p(data->block[i+1], SMBBLKDAT(priv)); 770 771 /* signals SMBBLKDAT ready */ 772 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 773 } 774 775 status = i801_wait_intr(priv); 776 exit: 777 return i801_check_post(priv, status); 778 } 779 780 static int i801_set_block_buffer_mode(struct i801_priv *priv) 781 { 782 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 783 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 784 return -EIO; 785 return 0; 786 } 787 788 /* Block transaction function */ 789 static int i801_block_transaction(struct i801_priv *priv, 790 union i2c_smbus_data *data, char read_write, 791 int command, int hwpec) 792 { 793 int result = 0; 794 unsigned char hostc; 795 796 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 797 if (read_write == I2C_SMBUS_WRITE) { 798 /* set I2C_EN bit in configuration register */ 799 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 800 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 801 hostc | SMBHSTCFG_I2C_EN); 802 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 803 dev_err(&priv->pci_dev->dev, 804 "I2C block read is unsupported!\n"); 805 return -EOPNOTSUPP; 806 } 807 } 808 809 if (read_write == I2C_SMBUS_WRITE 810 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 811 if (data->block[0] < 1) 812 data->block[0] = 1; 813 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 814 data->block[0] = I2C_SMBUS_BLOCK_MAX; 815 } else { 816 data->block[0] = 32; /* max for SMBus block reads */ 817 } 818 819 /* Experience has shown that the block buffer can only be used for 820 SMBus (not I2C) block transactions, even though the datasheet 821 doesn't mention this limitation. */ 822 if ((priv->features & FEATURE_BLOCK_BUFFER) 823 && command != I2C_SMBUS_I2C_BLOCK_DATA 824 && i801_set_block_buffer_mode(priv) == 0) 825 result = i801_block_transaction_by_block(priv, data, 826 read_write, 827 command, hwpec); 828 else 829 result = i801_block_transaction_byte_by_byte(priv, data, 830 read_write, 831 command, hwpec); 832 833 if (command == I2C_SMBUS_I2C_BLOCK_DATA 834 && read_write == I2C_SMBUS_WRITE) { 835 /* restore saved configuration register value */ 836 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 837 } 838 return result; 839 } 840 841 /* Return negative errno on error. */ 842 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 843 unsigned short flags, char read_write, u8 command, 844 int size, union i2c_smbus_data *data) 845 { 846 int hwpec; 847 int block = 0; 848 int ret = 0, xact = 0; 849 struct i801_priv *priv = i2c_get_adapdata(adap); 850 851 mutex_lock(&priv->acpi_lock); 852 if (priv->acpi_reserved) { 853 mutex_unlock(&priv->acpi_lock); 854 return -EBUSY; 855 } 856 857 pm_runtime_get_sync(&priv->pci_dev->dev); 858 859 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 860 && size != I2C_SMBUS_QUICK 861 && size != I2C_SMBUS_I2C_BLOCK_DATA; 862 863 switch (size) { 864 case I2C_SMBUS_QUICK: 865 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 866 SMBHSTADD(priv)); 867 xact = I801_QUICK; 868 break; 869 case I2C_SMBUS_BYTE: 870 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 871 SMBHSTADD(priv)); 872 if (read_write == I2C_SMBUS_WRITE) 873 outb_p(command, SMBHSTCMD(priv)); 874 xact = I801_BYTE; 875 break; 876 case I2C_SMBUS_BYTE_DATA: 877 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 878 SMBHSTADD(priv)); 879 outb_p(command, SMBHSTCMD(priv)); 880 if (read_write == I2C_SMBUS_WRITE) 881 outb_p(data->byte, SMBHSTDAT0(priv)); 882 xact = I801_BYTE_DATA; 883 break; 884 case I2C_SMBUS_WORD_DATA: 885 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 886 SMBHSTADD(priv)); 887 outb_p(command, SMBHSTCMD(priv)); 888 if (read_write == I2C_SMBUS_WRITE) { 889 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 890 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 891 } 892 xact = I801_WORD_DATA; 893 break; 894 case I2C_SMBUS_BLOCK_DATA: 895 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 896 SMBHSTADD(priv)); 897 outb_p(command, SMBHSTCMD(priv)); 898 block = 1; 899 break; 900 case I2C_SMBUS_I2C_BLOCK_DATA: 901 /* 902 * NB: page 240 of ICH5 datasheet shows that the R/#W 903 * bit should be cleared here, even when reading. 904 * However if SPD Write Disable is set (Lynx Point and later), 905 * the read will fail if we don't set the R/#W bit. 906 */ 907 outb_p(((addr & 0x7f) << 1) | 908 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 909 (read_write & 0x01) : 0), 910 SMBHSTADD(priv)); 911 if (read_write == I2C_SMBUS_READ) { 912 /* NB: page 240 of ICH5 datasheet also shows 913 * that DATA1 is the cmd field when reading */ 914 outb_p(command, SMBHSTDAT1(priv)); 915 } else 916 outb_p(command, SMBHSTCMD(priv)); 917 block = 1; 918 break; 919 case I2C_SMBUS_BLOCK_PROC_CALL: 920 /* 921 * Bit 0 of the slave address register always indicate a write 922 * command. 923 */ 924 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 925 outb_p(command, SMBHSTCMD(priv)); 926 block = 1; 927 break; 928 default: 929 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 930 size); 931 ret = -EOPNOTSUPP; 932 goto out; 933 } 934 935 if (hwpec) /* enable/disable hardware PEC */ 936 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 937 else 938 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 939 SMBAUXCTL(priv)); 940 941 if (block) 942 ret = i801_block_transaction(priv, data, read_write, size, 943 hwpec); 944 else 945 ret = i801_transaction(priv, xact); 946 947 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 948 time, so we forcibly disable it after every transaction. Turn off 949 E32B for the same reason. */ 950 if (hwpec || block) 951 outb_p(inb_p(SMBAUXCTL(priv)) & 952 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 953 954 if (block) 955 goto out; 956 if (ret) 957 goto out; 958 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 959 goto out; 960 961 switch (xact & 0x7f) { 962 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 963 case I801_BYTE_DATA: 964 data->byte = inb_p(SMBHSTDAT0(priv)); 965 break; 966 case I801_WORD_DATA: 967 data->word = inb_p(SMBHSTDAT0(priv)) + 968 (inb_p(SMBHSTDAT1(priv)) << 8); 969 break; 970 } 971 972 out: 973 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 974 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 975 mutex_unlock(&priv->acpi_lock); 976 return ret; 977 } 978 979 980 static u32 i801_func(struct i2c_adapter *adapter) 981 { 982 struct i801_priv *priv = i2c_get_adapdata(adapter); 983 984 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 985 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 986 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 987 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 988 ((priv->features & FEATURE_BLOCK_PROC) ? 989 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 990 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 991 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 992 ((priv->features & FEATURE_HOST_NOTIFY) ? 993 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 994 } 995 996 static void i801_enable_host_notify(struct i2c_adapter *adapter) 997 { 998 struct i801_priv *priv = i2c_get_adapdata(adapter); 999 1000 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1001 return; 1002 1003 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 1004 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 1005 SMBSLVCMD(priv)); 1006 1007 /* clear Host Notify bit to allow a new notification */ 1008 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 1009 } 1010 1011 static void i801_disable_host_notify(struct i801_priv *priv) 1012 { 1013 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1014 return; 1015 1016 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 1017 } 1018 1019 static const struct i2c_algorithm smbus_algorithm = { 1020 .smbus_xfer = i801_access, 1021 .functionality = i801_func, 1022 }; 1023 1024 static const struct pci_device_id i801_ids[] = { 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, 1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, 1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1078 { 0, } 1079 }; 1080 1081 MODULE_DEVICE_TABLE(pci, i801_ids); 1082 1083 #if defined CONFIG_X86 && defined CONFIG_DMI 1084 static unsigned char apanel_addr; 1085 1086 /* Scan the system ROM for the signature "FJKEYINF" */ 1087 static __init const void __iomem *bios_signature(const void __iomem *bios) 1088 { 1089 ssize_t offset; 1090 const unsigned char signature[] = "FJKEYINF"; 1091 1092 for (offset = 0; offset < 0x10000; offset += 0x10) { 1093 if (check_signature(bios + offset, signature, 1094 sizeof(signature)-1)) 1095 return bios + offset; 1096 } 1097 return NULL; 1098 } 1099 1100 static void __init input_apanel_init(void) 1101 { 1102 void __iomem *bios; 1103 const void __iomem *p; 1104 1105 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1106 p = bios_signature(bios); 1107 if (p) { 1108 /* just use the first address */ 1109 apanel_addr = readb(p + 8 + 3) >> 1; 1110 } 1111 iounmap(bios); 1112 } 1113 1114 struct dmi_onboard_device_info { 1115 const char *name; 1116 u8 type; 1117 unsigned short i2c_addr; 1118 const char *i2c_type; 1119 }; 1120 1121 static const struct dmi_onboard_device_info dmi_devices[] = { 1122 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1123 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1124 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1125 }; 1126 1127 static void dmi_check_onboard_device(u8 type, const char *name, 1128 struct i2c_adapter *adap) 1129 { 1130 int i; 1131 struct i2c_board_info info; 1132 1133 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1134 /* & ~0x80, ignore enabled/disabled bit */ 1135 if ((type & ~0x80) != dmi_devices[i].type) 1136 continue; 1137 if (strcasecmp(name, dmi_devices[i].name)) 1138 continue; 1139 1140 memset(&info, 0, sizeof(struct i2c_board_info)); 1141 info.addr = dmi_devices[i].i2c_addr; 1142 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1143 i2c_new_client_device(adap, &info); 1144 break; 1145 } 1146 } 1147 1148 /* We use our own function to check for onboard devices instead of 1149 dmi_find_device() as some buggy BIOS's have the devices we are interested 1150 in marked as disabled */ 1151 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1152 { 1153 int i, count; 1154 1155 if (dm->type != 10) 1156 return; 1157 1158 count = (dm->length - sizeof(struct dmi_header)) / 2; 1159 for (i = 0; i < count; i++) { 1160 const u8 *d = (char *)(dm + 1) + (i * 2); 1161 const char *name = ((char *) dm) + dm->length; 1162 u8 type = d[0]; 1163 u8 s = d[1]; 1164 1165 if (!s) 1166 continue; 1167 s--; 1168 while (s > 0 && name[0]) { 1169 name += strlen(name) + 1; 1170 s--; 1171 } 1172 if (name[0] == 0) /* Bogus string reference */ 1173 continue; 1174 1175 dmi_check_onboard_device(type, name, adap); 1176 } 1177 } 1178 1179 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1180 static const char *const acpi_smo8800_ids[] = { 1181 "SMO8800", 1182 "SMO8801", 1183 "SMO8810", 1184 "SMO8811", 1185 "SMO8820", 1186 "SMO8821", 1187 "SMO8830", 1188 "SMO8831", 1189 }; 1190 1191 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1192 u32 nesting_level, 1193 void *context, 1194 void **return_value) 1195 { 1196 struct acpi_device_info *info; 1197 acpi_status status; 1198 char *hid; 1199 int i; 1200 1201 status = acpi_get_object_info(obj_handle, &info); 1202 if (ACPI_FAILURE(status)) 1203 return AE_OK; 1204 1205 if (!(info->valid & ACPI_VALID_HID)) 1206 goto smo88xx_not_found; 1207 1208 hid = info->hardware_id.string; 1209 if (!hid) 1210 goto smo88xx_not_found; 1211 1212 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1213 if (i < 0) 1214 goto smo88xx_not_found; 1215 1216 kfree(info); 1217 1218 *((bool *)return_value) = true; 1219 return AE_CTRL_TERMINATE; 1220 1221 smo88xx_not_found: 1222 kfree(info); 1223 return AE_OK; 1224 } 1225 1226 static bool is_dell_system_with_lis3lv02d(void) 1227 { 1228 bool found; 1229 const char *vendor; 1230 1231 vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1232 if (!vendor || strcmp(vendor, "Dell Inc.")) 1233 return false; 1234 1235 /* 1236 * Check that ACPI device SMO88xx is present and is functioning. 1237 * Function acpi_get_devices() already filters all ACPI devices 1238 * which are not present or are not functioning. 1239 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1240 * accelerometer but unfortunately ACPI does not provide any other 1241 * information (like I2C address). 1242 */ 1243 found = false; 1244 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, 1245 (void **)&found); 1246 1247 return found; 1248 } 1249 1250 /* 1251 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1252 * so it is needed to define mapping table based on DMI product names. 1253 */ 1254 static const struct { 1255 const char *dmi_product_name; 1256 unsigned short i2c_addr; 1257 } dell_lis3lv02d_devices[] = { 1258 /* 1259 * Dell platform team told us that these Latitude devices have 1260 * ST microelectronics accelerometer at I2C address 0x29. 1261 */ 1262 { "Latitude E5250", 0x29 }, 1263 { "Latitude E5450", 0x29 }, 1264 { "Latitude E5550", 0x29 }, 1265 { "Latitude E6440", 0x29 }, 1266 { "Latitude E6440 ATG", 0x29 }, 1267 { "Latitude E6540", 0x29 }, 1268 /* 1269 * Additional individual entries were added after verification. 1270 */ 1271 { "Vostro V131", 0x1d }, 1272 }; 1273 1274 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1275 { 1276 struct i2c_board_info info; 1277 const char *dmi_product_name; 1278 int i; 1279 1280 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1281 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1282 if (strcmp(dmi_product_name, 1283 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1284 break; 1285 } 1286 1287 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1288 dev_warn(&priv->pci_dev->dev, 1289 "Accelerometer lis3lv02d is present on SMBus but its" 1290 " address is unknown, skipping registration\n"); 1291 return; 1292 } 1293 1294 memset(&info, 0, sizeof(struct i2c_board_info)); 1295 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1296 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1297 i2c_new_client_device(&priv->adapter, &info); 1298 } 1299 1300 /* Register optional slaves */ 1301 static void i801_probe_optional_slaves(struct i801_priv *priv) 1302 { 1303 /* Only register slaves on main SMBus channel */ 1304 if (priv->features & FEATURE_IDF) 1305 return; 1306 1307 if (apanel_addr) { 1308 struct i2c_board_info info; 1309 1310 memset(&info, 0, sizeof(struct i2c_board_info)); 1311 info.addr = apanel_addr; 1312 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1313 i2c_new_client_device(&priv->adapter, &info); 1314 } 1315 1316 if (dmi_name_in_vendors("FUJITSU")) 1317 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1318 1319 if (is_dell_system_with_lis3lv02d()) 1320 register_dell_lis3lv02d_i2c_device(priv); 1321 } 1322 #else 1323 static void __init input_apanel_init(void) {} 1324 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1325 #endif /* CONFIG_X86 && CONFIG_DMI */ 1326 1327 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1328 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1329 .gpio_chip = "gpio_ich", 1330 .values = { 0x02, 0x03 }, 1331 .n_values = 2, 1332 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1333 .gpios = { 52, 53 }, 1334 .n_gpios = 2, 1335 }; 1336 1337 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1338 .gpio_chip = "gpio_ich", 1339 .values = { 0x02, 0x03, 0x01 }, 1340 .n_values = 3, 1341 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1342 .gpios = { 52, 53 }, 1343 .n_gpios = 2, 1344 }; 1345 1346 static const struct dmi_system_id mux_dmi_table[] = { 1347 { 1348 .matches = { 1349 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1350 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1351 }, 1352 .driver_data = &i801_mux_config_asus_z8_d12, 1353 }, 1354 { 1355 .matches = { 1356 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1357 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1358 }, 1359 .driver_data = &i801_mux_config_asus_z8_d12, 1360 }, 1361 { 1362 .matches = { 1363 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1364 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1365 }, 1366 .driver_data = &i801_mux_config_asus_z8_d12, 1367 }, 1368 { 1369 .matches = { 1370 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1371 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1372 }, 1373 .driver_data = &i801_mux_config_asus_z8_d12, 1374 }, 1375 { 1376 .matches = { 1377 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1378 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1379 }, 1380 .driver_data = &i801_mux_config_asus_z8_d12, 1381 }, 1382 { 1383 .matches = { 1384 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1385 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1386 }, 1387 .driver_data = &i801_mux_config_asus_z8_d12, 1388 }, 1389 { 1390 .matches = { 1391 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1392 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1393 }, 1394 .driver_data = &i801_mux_config_asus_z8_d18, 1395 }, 1396 { 1397 .matches = { 1398 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1399 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1400 }, 1401 .driver_data = &i801_mux_config_asus_z8_d18, 1402 }, 1403 { 1404 .matches = { 1405 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1406 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1407 }, 1408 .driver_data = &i801_mux_config_asus_z8_d12, 1409 }, 1410 { } 1411 }; 1412 1413 /* Setup multiplexing if needed */ 1414 static int i801_add_mux(struct i801_priv *priv) 1415 { 1416 struct device *dev = &priv->adapter.dev; 1417 const struct i801_mux_config *mux_config; 1418 struct i2c_mux_gpio_platform_data gpio_data; 1419 struct gpiod_lookup_table *lookup; 1420 int err, i; 1421 1422 if (!priv->mux_drvdata) 1423 return 0; 1424 mux_config = priv->mux_drvdata; 1425 1426 /* Prepare the platform data */ 1427 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1428 gpio_data.parent = priv->adapter.nr; 1429 gpio_data.values = mux_config->values; 1430 gpio_data.n_values = mux_config->n_values; 1431 gpio_data.classes = mux_config->classes; 1432 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1433 1434 /* Register GPIO descriptor lookup table */ 1435 lookup = devm_kzalloc(dev, 1436 struct_size(lookup, table, mux_config->n_gpios), 1437 GFP_KERNEL); 1438 if (!lookup) 1439 return -ENOMEM; 1440 lookup->dev_id = "i2c-mux-gpio"; 1441 for (i = 0; i < mux_config->n_gpios; i++) { 1442 lookup->table[i].chip_label = mux_config->gpio_chip; 1443 lookup->table[i].chip_hwnum = mux_config->gpios[i]; 1444 lookup->table[i].con_id = "mux"; 1445 } 1446 gpiod_add_lookup_table(lookup); 1447 priv->lookup = lookup; 1448 1449 /* 1450 * Register the mux device, we use PLATFORM_DEVID_NONE here 1451 * because since we are referring to the GPIO chip by name we are 1452 * anyways in deep trouble if there is more than one of these 1453 * devices, and there should likely only be one platform controller 1454 * hub. 1455 */ 1456 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1457 PLATFORM_DEVID_NONE, &gpio_data, 1458 sizeof(struct i2c_mux_gpio_platform_data)); 1459 if (IS_ERR(priv->mux_pdev)) { 1460 err = PTR_ERR(priv->mux_pdev); 1461 gpiod_remove_lookup_table(lookup); 1462 priv->mux_pdev = NULL; 1463 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1464 return err; 1465 } 1466 1467 return 0; 1468 } 1469 1470 static void i801_del_mux(struct i801_priv *priv) 1471 { 1472 if (priv->mux_pdev) 1473 platform_device_unregister(priv->mux_pdev); 1474 if (priv->lookup) 1475 gpiod_remove_lookup_table(priv->lookup); 1476 } 1477 1478 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1479 { 1480 const struct dmi_system_id *id; 1481 const struct i801_mux_config *mux_config; 1482 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1483 int i; 1484 1485 id = dmi_first_match(mux_dmi_table); 1486 if (id) { 1487 /* Remove branch classes from trunk */ 1488 mux_config = id->driver_data; 1489 for (i = 0; i < mux_config->n_values; i++) 1490 class &= ~mux_config->classes[i]; 1491 1492 /* Remember for later */ 1493 priv->mux_drvdata = mux_config; 1494 } 1495 1496 return class; 1497 } 1498 #else 1499 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1500 static inline void i801_del_mux(struct i801_priv *priv) { } 1501 1502 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1503 { 1504 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1505 } 1506 #endif 1507 1508 static const struct itco_wdt_platform_data spt_tco_platform_data = { 1509 .name = "Intel PCH", 1510 .version = 4, 1511 }; 1512 1513 static DEFINE_SPINLOCK(p2sb_spinlock); 1514 1515 static struct platform_device * 1516 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1517 struct resource *tco_res) 1518 { 1519 struct resource *res; 1520 unsigned int devfn; 1521 u64 base64_addr; 1522 u32 base_addr; 1523 u8 hidden; 1524 1525 /* 1526 * We must access the NO_REBOOT bit over the Primary to Sideband 1527 * bridge (P2SB). The BIOS prevents the P2SB device from being 1528 * enumerated by the PCI subsystem, so we need to unhide/hide it 1529 * to lookup the P2SB BAR. 1530 */ 1531 spin_lock(&p2sb_spinlock); 1532 1533 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1534 1535 /* Unhide the P2SB device, if it is hidden */ 1536 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1537 if (hidden) 1538 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1539 1540 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1541 base64_addr = base_addr & 0xfffffff0; 1542 1543 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1544 base64_addr |= (u64)base_addr << 32; 1545 1546 /* Hide the P2SB device, if it was hidden before */ 1547 if (hidden) 1548 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1549 spin_unlock(&p2sb_spinlock); 1550 1551 res = &tco_res[1]; 1552 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1553 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1554 else 1555 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1556 1557 res->end = res->start + 3; 1558 res->flags = IORESOURCE_MEM; 1559 1560 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1561 tco_res, 2, &spt_tco_platform_data, 1562 sizeof(spt_tco_platform_data)); 1563 } 1564 1565 static const struct itco_wdt_platform_data cnl_tco_platform_data = { 1566 .name = "Intel PCH", 1567 .version = 6, 1568 }; 1569 1570 static struct platform_device * 1571 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1572 struct resource *tco_res) 1573 { 1574 return platform_device_register_resndata(&pci_dev->dev, 1575 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data, 1576 sizeof(cnl_tco_platform_data)); 1577 } 1578 1579 static void i801_add_tco(struct i801_priv *priv) 1580 { 1581 struct pci_dev *pci_dev = priv->pci_dev; 1582 struct resource tco_res[2], *res; 1583 u32 tco_base, tco_ctl; 1584 1585 /* If we have ACPI based watchdog use that instead */ 1586 if (acpi_has_watchdog()) 1587 return; 1588 1589 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1590 return; 1591 1592 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1593 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1594 if (!(tco_ctl & TCOCTL_EN)) 1595 return; 1596 1597 memset(tco_res, 0, sizeof(tco_res)); 1598 /* 1599 * Always populate the main iTCO IO resource here. The second entry 1600 * for NO_REBOOT MMIO is filled by the SPT specific function. 1601 */ 1602 res = &tco_res[0]; 1603 res->start = tco_base & ~1; 1604 res->end = res->start + 32 - 1; 1605 res->flags = IORESOURCE_IO; 1606 1607 if (priv->features & FEATURE_TCO_CNL) 1608 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1609 else 1610 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1611 1612 if (IS_ERR(priv->tco_pdev)) 1613 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1614 } 1615 1616 #ifdef CONFIG_ACPI 1617 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1618 acpi_physical_address address) 1619 { 1620 return address >= priv->smba && 1621 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1622 } 1623 1624 static acpi_status 1625 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1626 u64 *value, void *handler_context, void *region_context) 1627 { 1628 struct i801_priv *priv = handler_context; 1629 struct pci_dev *pdev = priv->pci_dev; 1630 acpi_status status; 1631 1632 /* 1633 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1634 * further access from the driver itself. This device is now owned 1635 * by the system firmware. 1636 */ 1637 mutex_lock(&priv->acpi_lock); 1638 1639 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1640 priv->acpi_reserved = true; 1641 1642 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1643 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1644 1645 /* 1646 * BIOS is accessing the host controller so prevent it from 1647 * suspending automatically from now on. 1648 */ 1649 pm_runtime_get_sync(&pdev->dev); 1650 } 1651 1652 if ((function & ACPI_IO_MASK) == ACPI_READ) 1653 status = acpi_os_read_port(address, (u32 *)value, bits); 1654 else 1655 status = acpi_os_write_port(address, (u32)*value, bits); 1656 1657 mutex_unlock(&priv->acpi_lock); 1658 1659 return status; 1660 } 1661 1662 static int i801_acpi_probe(struct i801_priv *priv) 1663 { 1664 struct acpi_device *adev; 1665 acpi_status status; 1666 1667 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1668 if (adev) { 1669 status = acpi_install_address_space_handler(adev->handle, 1670 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1671 NULL, priv); 1672 if (ACPI_SUCCESS(status)) 1673 return 0; 1674 } 1675 1676 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1677 } 1678 1679 static void i801_acpi_remove(struct i801_priv *priv) 1680 { 1681 struct acpi_device *adev; 1682 1683 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1684 if (!adev) 1685 return; 1686 1687 acpi_remove_address_space_handler(adev->handle, 1688 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1689 1690 mutex_lock(&priv->acpi_lock); 1691 if (priv->acpi_reserved) 1692 pm_runtime_put(&priv->pci_dev->dev); 1693 mutex_unlock(&priv->acpi_lock); 1694 } 1695 #else 1696 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1697 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1698 #endif 1699 1700 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1701 { 1702 unsigned char temp; 1703 int err, i; 1704 struct i801_priv *priv; 1705 1706 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1707 if (!priv) 1708 return -ENOMEM; 1709 1710 i2c_set_adapdata(&priv->adapter, priv); 1711 priv->adapter.owner = THIS_MODULE; 1712 priv->adapter.class = i801_get_adapter_class(priv); 1713 priv->adapter.algo = &smbus_algorithm; 1714 priv->adapter.dev.parent = &dev->dev; 1715 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1716 priv->adapter.retries = 3; 1717 mutex_init(&priv->acpi_lock); 1718 1719 priv->pci_dev = dev; 1720 switch (dev->device) { 1721 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1722 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1723 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1724 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1725 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1726 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1727 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: 1728 priv->features |= FEATURE_BLOCK_PROC; 1729 priv->features |= FEATURE_I2C_BLOCK_READ; 1730 priv->features |= FEATURE_IRQ; 1731 priv->features |= FEATURE_SMBUS_PEC; 1732 priv->features |= FEATURE_BLOCK_BUFFER; 1733 priv->features |= FEATURE_TCO_SPT; 1734 priv->features |= FEATURE_HOST_NOTIFY; 1735 break; 1736 1737 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1738 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1739 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1740 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1741 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1742 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: 1743 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1744 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1745 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: 1746 priv->features |= FEATURE_BLOCK_PROC; 1747 priv->features |= FEATURE_I2C_BLOCK_READ; 1748 priv->features |= FEATURE_IRQ; 1749 priv->features |= FEATURE_SMBUS_PEC; 1750 priv->features |= FEATURE_BLOCK_BUFFER; 1751 priv->features |= FEATURE_TCO_CNL; 1752 priv->features |= FEATURE_HOST_NOTIFY; 1753 break; 1754 1755 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1756 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1757 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1758 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1759 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1760 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1761 priv->features |= FEATURE_IDF; 1762 /* fall through */ 1763 default: 1764 priv->features |= FEATURE_BLOCK_PROC; 1765 priv->features |= FEATURE_I2C_BLOCK_READ; 1766 priv->features |= FEATURE_IRQ; 1767 /* fall through */ 1768 case PCI_DEVICE_ID_INTEL_82801DB_3: 1769 priv->features |= FEATURE_SMBUS_PEC; 1770 priv->features |= FEATURE_BLOCK_BUFFER; 1771 /* fall through */ 1772 case PCI_DEVICE_ID_INTEL_82801CA_3: 1773 priv->features |= FEATURE_HOST_NOTIFY; 1774 /* fall through */ 1775 case PCI_DEVICE_ID_INTEL_82801BA_2: 1776 case PCI_DEVICE_ID_INTEL_82801AB_3: 1777 case PCI_DEVICE_ID_INTEL_82801AA_3: 1778 break; 1779 } 1780 1781 /* Disable features on user request */ 1782 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1783 if (priv->features & disable_features & (1 << i)) 1784 dev_notice(&dev->dev, "%s disabled by user\n", 1785 i801_feature_names[i]); 1786 } 1787 priv->features &= ~disable_features; 1788 1789 err = pcim_enable_device(dev); 1790 if (err) { 1791 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1792 err); 1793 return err; 1794 } 1795 pcim_pin_device(dev); 1796 1797 /* Determine the address of the SMBus area */ 1798 priv->smba = pci_resource_start(dev, SMBBAR); 1799 if (!priv->smba) { 1800 dev_err(&dev->dev, 1801 "SMBus base address uninitialized, upgrade BIOS\n"); 1802 return -ENODEV; 1803 } 1804 1805 if (i801_acpi_probe(priv)) 1806 return -ENODEV; 1807 1808 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1809 dev_driver_string(&dev->dev)); 1810 if (err) { 1811 dev_err(&dev->dev, 1812 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1813 priv->smba, 1814 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1815 i801_acpi_remove(priv); 1816 return err; 1817 } 1818 1819 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1820 priv->original_hstcfg = temp; 1821 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1822 if (!(temp & SMBHSTCFG_HST_EN)) { 1823 dev_info(&dev->dev, "Enabling SMBus device\n"); 1824 temp |= SMBHSTCFG_HST_EN; 1825 } 1826 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1827 1828 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1829 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1830 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1831 priv->features &= ~FEATURE_IRQ; 1832 } 1833 if (temp & SMBHSTCFG_SPD_WD) 1834 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1835 1836 /* Clear special mode bits */ 1837 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1838 outb_p(inb_p(SMBAUXCTL(priv)) & 1839 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1840 1841 /* Remember original Host Notify setting */ 1842 if (priv->features & FEATURE_HOST_NOTIFY) 1843 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1844 1845 /* Default timeout in interrupt mode: 200 ms */ 1846 priv->adapter.timeout = HZ / 5; 1847 1848 if (dev->irq == IRQ_NOTCONNECTED) 1849 priv->features &= ~FEATURE_IRQ; 1850 1851 if (priv->features & FEATURE_IRQ) { 1852 u16 pcictl, pcists; 1853 1854 /* Complain if an interrupt is already pending */ 1855 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1856 if (pcists & SMBPCISTS_INTS) 1857 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1858 1859 /* Check if interrupts have been disabled */ 1860 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1861 if (pcictl & SMBPCICTL_INTDIS) { 1862 dev_info(&dev->dev, "Interrupts are disabled\n"); 1863 priv->features &= ~FEATURE_IRQ; 1864 } 1865 } 1866 1867 if (priv->features & FEATURE_IRQ) { 1868 init_waitqueue_head(&priv->waitq); 1869 1870 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1871 IRQF_SHARED, 1872 dev_driver_string(&dev->dev), priv); 1873 if (err) { 1874 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1875 dev->irq, err); 1876 priv->features &= ~FEATURE_IRQ; 1877 } 1878 } 1879 dev_info(&dev->dev, "SMBus using %s\n", 1880 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1881 1882 i801_add_tco(priv); 1883 1884 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1885 "SMBus I801 adapter at %04lx", priv->smba); 1886 err = i2c_add_adapter(&priv->adapter); 1887 if (err) { 1888 i801_acpi_remove(priv); 1889 return err; 1890 } 1891 1892 i801_enable_host_notify(&priv->adapter); 1893 1894 i801_probe_optional_slaves(priv); 1895 /* We ignore errors - multiplexing is optional */ 1896 i801_add_mux(priv); 1897 1898 pci_set_drvdata(dev, priv); 1899 1900 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1901 pm_runtime_use_autosuspend(&dev->dev); 1902 pm_runtime_put_autosuspend(&dev->dev); 1903 pm_runtime_allow(&dev->dev); 1904 1905 return 0; 1906 } 1907 1908 static void i801_remove(struct pci_dev *dev) 1909 { 1910 struct i801_priv *priv = pci_get_drvdata(dev); 1911 1912 pm_runtime_forbid(&dev->dev); 1913 pm_runtime_get_noresume(&dev->dev); 1914 1915 i801_disable_host_notify(priv); 1916 i801_del_mux(priv); 1917 i2c_del_adapter(&priv->adapter); 1918 i801_acpi_remove(priv); 1919 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1920 1921 platform_device_unregister(priv->tco_pdev); 1922 1923 /* 1924 * do not call pci_disable_device(dev) since it can cause hard hangs on 1925 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1926 */ 1927 } 1928 1929 static void i801_shutdown(struct pci_dev *dev) 1930 { 1931 struct i801_priv *priv = pci_get_drvdata(dev); 1932 1933 /* Restore config registers to avoid hard hang on some systems */ 1934 i801_disable_host_notify(priv); 1935 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1936 } 1937 1938 #ifdef CONFIG_PM_SLEEP 1939 static int i801_suspend(struct device *dev) 1940 { 1941 struct pci_dev *pci_dev = to_pci_dev(dev); 1942 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1943 1944 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1945 return 0; 1946 } 1947 1948 static int i801_resume(struct device *dev) 1949 { 1950 struct i801_priv *priv = dev_get_drvdata(dev); 1951 1952 i801_enable_host_notify(&priv->adapter); 1953 1954 return 0; 1955 } 1956 #endif 1957 1958 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1959 1960 static struct pci_driver i801_driver = { 1961 .name = "i801_smbus", 1962 .id_table = i801_ids, 1963 .probe = i801_probe, 1964 .remove = i801_remove, 1965 .shutdown = i801_shutdown, 1966 .driver = { 1967 .pm = &i801_pm_ops, 1968 }, 1969 }; 1970 1971 static int __init i2c_i801_init(void) 1972 { 1973 if (dmi_name_in_vendors("FUJITSU")) 1974 input_apanel_init(); 1975 return pci_register_driver(&i801_driver); 1976 } 1977 1978 static void __exit i2c_i801_exit(void) 1979 { 1980 pci_unregister_driver(&i801_driver); 1981 } 1982 1983 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 1984 MODULE_DESCRIPTION("I801 SMBus driver"); 1985 MODULE_LICENSE("GPL"); 1986 1987 module_init(i2c_i801_init); 1988 module_exit(i2c_i801_exit); 1989