1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/pci.h> 10 #include <linux/device.h> 11 #include <linux/errno.h> 12 #include <linux/slab.h> 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/jiffies.h> 16 #include <linux/log2.h> 17 #include <linux/err.h> 18 #include <linux/netdevice.h> 19 20 #include "hinic_sriov.h" 21 #include "hinic_hw_if.h" 22 #include "hinic_hw_eqs.h" 23 #include "hinic_hw_mgmt.h" 24 #include "hinic_hw_qp_ctxt.h" 25 #include "hinic_hw_qp.h" 26 #include "hinic_hw_io.h" 27 #include "hinic_hw_dev.h" 28 29 #define IO_STATUS_TIMEOUT 100 30 #define OUTBOUND_STATE_TIMEOUT 100 31 #define DB_STATE_TIMEOUT 100 32 33 #define MAX_IRQS(max_qps, num_aeqs, num_ceqs) \ 34 (2 * (max_qps) + (num_aeqs) + (num_ceqs)) 35 36 #define ADDR_IN_4BYTES(addr) ((addr) >> 2) 37 38 enum intr_type { 39 INTR_MSIX_TYPE, 40 }; 41 42 enum io_status { 43 IO_STOPPED = 0, 44 IO_RUNNING = 1, 45 }; 46 47 /** 48 * get_capability - convert device capabilities to NIC capabilities 49 * @hwdev: the HW device to set and convert device capabilities for 50 * @dev_cap: device capabilities from FW 51 * 52 * Return 0 - Success, negative - Failure 53 **/ 54 static int parse_capability(struct hinic_hwdev *hwdev, 55 struct hinic_dev_cap *dev_cap) 56 { 57 struct hinic_cap *nic_cap = &hwdev->nic_cap; 58 int num_aeqs, num_ceqs, num_irqs; 59 60 if (!HINIC_IS_VF(hwdev->hwif) && dev_cap->intr_type != INTR_MSIX_TYPE) 61 return -EFAULT; 62 63 num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif); 64 num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif); 65 num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif); 66 67 /* Each QP has its own (SQ + RQ) interrupts */ 68 nic_cap->num_qps = (num_irqs - (num_aeqs + num_ceqs)) / 2; 69 70 if (nic_cap->num_qps > HINIC_Q_CTXT_MAX) 71 nic_cap->num_qps = HINIC_Q_CTXT_MAX; 72 73 if (!HINIC_IS_VF(hwdev->hwif)) 74 nic_cap->max_qps = dev_cap->max_sqs + 1; 75 else 76 nic_cap->max_qps = dev_cap->max_sqs; 77 78 if (nic_cap->num_qps > nic_cap->max_qps) 79 nic_cap->num_qps = nic_cap->max_qps; 80 81 if (!HINIC_IS_VF(hwdev->hwif)) { 82 nic_cap->max_vf = dev_cap->max_vf; 83 nic_cap->max_vf_qps = dev_cap->max_vf_sqs + 1; 84 } 85 86 return 0; 87 } 88 89 /** 90 * get_cap_from_fw - get device capabilities from FW 91 * @pfhwdev: the PF HW device to get capabilities for 92 * 93 * Return 0 - Success, negative - Failure 94 **/ 95 static int get_capability(struct hinic_pfhwdev *pfhwdev) 96 { 97 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 98 struct hinic_hwif *hwif = hwdev->hwif; 99 struct pci_dev *pdev = hwif->pdev; 100 struct hinic_dev_cap dev_cap; 101 u16 out_len; 102 int err; 103 104 out_len = sizeof(dev_cap); 105 106 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_CFGM, 107 HINIC_CFG_NIC_CAP, &dev_cap, sizeof(dev_cap), 108 &dev_cap, &out_len, HINIC_MGMT_MSG_SYNC); 109 if (err) { 110 dev_err(&pdev->dev, "Failed to get capability from FW\n"); 111 return err; 112 } 113 114 return parse_capability(hwdev, &dev_cap); 115 } 116 117 /** 118 * get_dev_cap - get device capabilities 119 * @hwdev: the NIC HW device to get capabilities for 120 * 121 * Return 0 - Success, negative - Failure 122 **/ 123 static int get_dev_cap(struct hinic_hwdev *hwdev) 124 { 125 struct hinic_hwif *hwif = hwdev->hwif; 126 struct pci_dev *pdev = hwif->pdev; 127 struct hinic_pfhwdev *pfhwdev; 128 int err; 129 130 switch (HINIC_FUNC_TYPE(hwif)) { 131 case HINIC_PPF: 132 case HINIC_PF: 133 case HINIC_VF: 134 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 135 err = get_capability(pfhwdev); 136 if (err) { 137 dev_err(&pdev->dev, "Failed to get capability\n"); 138 return err; 139 } 140 break; 141 default: 142 dev_err(&pdev->dev, "Unsupported PCI Function type\n"); 143 return -EINVAL; 144 } 145 146 return 0; 147 } 148 149 /** 150 * init_msix - enable the msix and save the entries 151 * @hwdev: the NIC HW device 152 * 153 * Return 0 - Success, negative - Failure 154 **/ 155 static int init_msix(struct hinic_hwdev *hwdev) 156 { 157 struct hinic_hwif *hwif = hwdev->hwif; 158 struct pci_dev *pdev = hwif->pdev; 159 int nr_irqs, num_aeqs, num_ceqs; 160 size_t msix_entries_size; 161 int i, err; 162 163 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 164 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 165 nr_irqs = MAX_IRQS(HINIC_MAX_QPS, num_aeqs, num_ceqs); 166 if (nr_irqs > HINIC_HWIF_NUM_IRQS(hwif)) 167 nr_irqs = HINIC_HWIF_NUM_IRQS(hwif); 168 169 msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries); 170 hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size, 171 GFP_KERNEL); 172 if (!hwdev->msix_entries) 173 return -ENOMEM; 174 175 for (i = 0; i < nr_irqs; i++) 176 hwdev->msix_entries[i].entry = i; 177 178 err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs); 179 if (err) { 180 dev_err(&pdev->dev, "Failed to enable pci msix\n"); 181 return err; 182 } 183 184 return 0; 185 } 186 187 /** 188 * disable_msix - disable the msix 189 * @hwdev: the NIC HW device 190 **/ 191 static void disable_msix(struct hinic_hwdev *hwdev) 192 { 193 struct hinic_hwif *hwif = hwdev->hwif; 194 struct pci_dev *pdev = hwif->pdev; 195 196 pci_disable_msix(pdev); 197 } 198 199 /** 200 * hinic_port_msg_cmd - send port msg to mgmt 201 * @hwdev: the NIC HW device 202 * @cmd: the port command 203 * @buf_in: input buffer 204 * @in_size: input size 205 * @buf_out: output buffer 206 * @out_size: returned output size 207 * 208 * Return 0 - Success, negative - Failure 209 **/ 210 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 211 void *buf_in, u16 in_size, void *buf_out, u16 *out_size) 212 { 213 struct hinic_pfhwdev *pfhwdev; 214 215 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 216 217 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_L2NIC, cmd, 218 buf_in, in_size, buf_out, out_size, 219 HINIC_MGMT_MSG_SYNC); 220 } 221 222 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, 223 void *buf_in, u16 in_size, void *buf_out, 224 u16 *out_size) 225 { 226 struct hinic_pfhwdev *pfhwdev; 227 228 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 229 230 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_HILINK, cmd, 231 buf_in, in_size, buf_out, out_size, 232 HINIC_MGMT_MSG_SYNC); 233 } 234 235 /** 236 * init_fw_ctxt- Init Firmware tables before network mgmt and io operations 237 * @hwdev: the NIC HW device 238 * 239 * Return 0 - Success, negative - Failure 240 **/ 241 static int init_fw_ctxt(struct hinic_hwdev *hwdev) 242 { 243 struct hinic_hwif *hwif = hwdev->hwif; 244 struct pci_dev *pdev = hwif->pdev; 245 struct hinic_cmd_fw_ctxt fw_ctxt; 246 u16 out_size = sizeof(fw_ctxt); 247 int err; 248 249 fw_ctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 250 fw_ctxt.rx_buf_sz = HINIC_RX_BUF_SZ; 251 252 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT, 253 &fw_ctxt, sizeof(fw_ctxt), 254 &fw_ctxt, &out_size); 255 if (err || (out_size != sizeof(fw_ctxt)) || fw_ctxt.status) { 256 dev_err(&pdev->dev, "Failed to init FW ctxt, ret = %d\n", 257 fw_ctxt.status); 258 return -EFAULT; 259 } 260 261 return 0; 262 } 263 264 /** 265 * set_hw_ioctxt - set the shape of the IO queues in FW 266 * @hwdev: the NIC HW device 267 * @rq_depth: rq depth 268 * @sq_depth: sq depth 269 * 270 * Return 0 - Success, negative - Failure 271 **/ 272 static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int sq_depth, 273 unsigned int rq_depth) 274 { 275 struct hinic_hwif *hwif = hwdev->hwif; 276 struct hinic_cmd_hw_ioctxt hw_ioctxt; 277 struct hinic_pfhwdev *pfhwdev; 278 279 hw_ioctxt.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 280 hw_ioctxt.ppf_idx = HINIC_HWIF_PPF_IDX(hwif); 281 282 hw_ioctxt.set_cmdq_depth = HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT; 283 hw_ioctxt.cmdq_depth = 0; 284 285 hw_ioctxt.lro_en = 1; 286 287 hw_ioctxt.rq_depth = ilog2(rq_depth); 288 289 hw_ioctxt.rx_buf_sz_idx = HINIC_RX_BUF_SZ_IDX; 290 291 hw_ioctxt.sq_depth = ilog2(sq_depth); 292 293 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 294 295 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 296 HINIC_COMM_CMD_HWCTXT_SET, 297 &hw_ioctxt, sizeof(hw_ioctxt), NULL, 298 NULL, HINIC_MGMT_MSG_SYNC); 299 } 300 301 static int wait_for_outbound_state(struct hinic_hwdev *hwdev) 302 { 303 enum hinic_outbound_state outbound_state; 304 struct hinic_hwif *hwif = hwdev->hwif; 305 struct pci_dev *pdev = hwif->pdev; 306 unsigned long end; 307 308 end = jiffies + msecs_to_jiffies(OUTBOUND_STATE_TIMEOUT); 309 do { 310 outbound_state = hinic_outbound_state_get(hwif); 311 312 if (outbound_state == HINIC_OUTBOUND_ENABLE) 313 return 0; 314 315 msleep(20); 316 } while (time_before(jiffies, end)); 317 318 dev_err(&pdev->dev, "Wait for OUTBOUND - Timeout\n"); 319 return -EFAULT; 320 } 321 322 static int wait_for_db_state(struct hinic_hwdev *hwdev) 323 { 324 struct hinic_hwif *hwif = hwdev->hwif; 325 struct pci_dev *pdev = hwif->pdev; 326 enum hinic_db_state db_state; 327 unsigned long end; 328 329 end = jiffies + msecs_to_jiffies(DB_STATE_TIMEOUT); 330 do { 331 db_state = hinic_db_state_get(hwif); 332 333 if (db_state == HINIC_DB_ENABLE) 334 return 0; 335 336 msleep(20); 337 } while (time_before(jiffies, end)); 338 339 dev_err(&pdev->dev, "Wait for DB - Timeout\n"); 340 return -EFAULT; 341 } 342 343 /** 344 * clear_io_resource - set the IO resources as not active in the NIC 345 * @hwdev: the NIC HW device 346 * 347 * Return 0 - Success, negative - Failure 348 **/ 349 static int clear_io_resources(struct hinic_hwdev *hwdev) 350 { 351 struct hinic_cmd_clear_io_res cmd_clear_io_res; 352 struct hinic_hwif *hwif = hwdev->hwif; 353 struct pci_dev *pdev = hwif->pdev; 354 struct hinic_pfhwdev *pfhwdev; 355 int err; 356 357 /* sleep 100ms to wait for firmware stopping I/O */ 358 msleep(100); 359 360 cmd_clear_io_res.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 361 362 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 363 364 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 365 HINIC_COMM_CMD_IO_RES_CLEAR, &cmd_clear_io_res, 366 sizeof(cmd_clear_io_res), NULL, NULL, 367 HINIC_MGMT_MSG_SYNC); 368 if (err) { 369 dev_err(&pdev->dev, "Failed to clear IO resources\n"); 370 return err; 371 } 372 373 return 0; 374 } 375 376 /** 377 * set_resources_state - set the state of the resources in the NIC 378 * @hwdev: the NIC HW device 379 * @state: the state to set 380 * 381 * Return 0 - Success, negative - Failure 382 **/ 383 static int set_resources_state(struct hinic_hwdev *hwdev, 384 enum hinic_res_state state) 385 { 386 struct hinic_cmd_set_res_state res_state; 387 struct hinic_hwif *hwif = hwdev->hwif; 388 struct hinic_pfhwdev *pfhwdev; 389 390 res_state.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 391 res_state.state = state; 392 393 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 394 395 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 396 HINIC_MOD_COMM, 397 HINIC_COMM_CMD_RES_STATE_SET, 398 &res_state, sizeof(res_state), NULL, 399 NULL, HINIC_MGMT_MSG_SYNC); 400 } 401 402 /** 403 * get_base_qpn - get the first qp number 404 * @hwdev: the NIC HW device 405 * @base_qpn: returned qp number 406 * 407 * Return 0 - Success, negative - Failure 408 **/ 409 static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn) 410 { 411 struct hinic_cmd_base_qpn cmd_base_qpn; 412 struct hinic_hwif *hwif = hwdev->hwif; 413 u16 out_size = sizeof(cmd_base_qpn); 414 struct pci_dev *pdev = hwif->pdev; 415 int err; 416 417 cmd_base_qpn.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 418 419 err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN, 420 &cmd_base_qpn, sizeof(cmd_base_qpn), 421 &cmd_base_qpn, &out_size); 422 if (err || (out_size != sizeof(cmd_base_qpn)) || cmd_base_qpn.status) { 423 dev_err(&pdev->dev, "Failed to get base qpn, status = %d\n", 424 cmd_base_qpn.status); 425 return -EFAULT; 426 } 427 428 *base_qpn = cmd_base_qpn.qpn; 429 return 0; 430 } 431 432 /** 433 * hinic_hwdev_ifup - Preparing the HW for passing IO 434 * @hwdev: the NIC HW device 435 * 436 * Return 0 - Success, negative - Failure 437 **/ 438 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth) 439 { 440 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 441 struct hinic_cap *nic_cap = &hwdev->nic_cap; 442 struct hinic_hwif *hwif = hwdev->hwif; 443 int err, num_aeqs, num_ceqs, num_qps; 444 struct msix_entry *ceq_msix_entries; 445 struct msix_entry *sq_msix_entries; 446 struct msix_entry *rq_msix_entries; 447 struct pci_dev *pdev = hwif->pdev; 448 u16 base_qpn; 449 450 err = get_base_qpn(hwdev, &base_qpn); 451 if (err) { 452 dev_err(&pdev->dev, "Failed to get global base qp number\n"); 453 return err; 454 } 455 456 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 457 num_ceqs = HINIC_HWIF_NUM_CEQS(hwif); 458 459 ceq_msix_entries = &hwdev->msix_entries[num_aeqs]; 460 func_to_io->hwdev = hwdev; 461 func_to_io->sq_depth = sq_depth; 462 func_to_io->rq_depth = rq_depth; 463 464 err = hinic_io_init(func_to_io, hwif, nic_cap->max_qps, num_ceqs, 465 ceq_msix_entries); 466 if (err) { 467 dev_err(&pdev->dev, "Failed to init IO channel\n"); 468 return err; 469 } 470 471 num_qps = nic_cap->num_qps; 472 sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs]; 473 rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps]; 474 475 err = hinic_io_create_qps(func_to_io, base_qpn, num_qps, 476 sq_msix_entries, rq_msix_entries); 477 if (err) { 478 dev_err(&pdev->dev, "Failed to create QPs\n"); 479 goto err_create_qps; 480 } 481 482 err = wait_for_db_state(hwdev); 483 if (err) { 484 dev_warn(&pdev->dev, "db - disabled, try again\n"); 485 hinic_db_state_set(hwif, HINIC_DB_ENABLE); 486 } 487 488 err = set_hw_ioctxt(hwdev, sq_depth, rq_depth); 489 if (err) { 490 dev_err(&pdev->dev, "Failed to set HW IO ctxt\n"); 491 goto err_hw_ioctxt; 492 } 493 494 return 0; 495 496 err_hw_ioctxt: 497 hinic_io_destroy_qps(func_to_io, num_qps); 498 499 err_create_qps: 500 hinic_io_free(func_to_io); 501 return err; 502 } 503 504 /** 505 * hinic_hwdev_ifdown - Closing the HW for passing IO 506 * @hwdev: the NIC HW device 507 * 508 **/ 509 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev) 510 { 511 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 512 struct hinic_cap *nic_cap = &hwdev->nic_cap; 513 514 clear_io_resources(hwdev); 515 516 hinic_io_destroy_qps(func_to_io, nic_cap->num_qps); 517 hinic_io_free(func_to_io); 518 } 519 520 /** 521 * hinic_hwdev_cb_register - register callback handler for MGMT events 522 * @hwdev: the NIC HW device 523 * @cmd: the mgmt event 524 * @handle: private data for the handler 525 * @handler: event handler 526 **/ 527 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 528 enum hinic_mgmt_msg_cmd cmd, void *handle, 529 void (*handler)(void *handle, void *buf_in, 530 u16 in_size, void *buf_out, 531 u16 *out_size)) 532 { 533 struct hinic_pfhwdev *pfhwdev; 534 struct hinic_nic_cb *nic_cb; 535 u8 cmd_cb; 536 537 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 538 539 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 540 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 541 542 nic_cb->handler = handler; 543 nic_cb->handle = handle; 544 nic_cb->cb_state = HINIC_CB_ENABLED; 545 } 546 547 /** 548 * hinic_hwdev_cb_unregister - unregister callback handler for MGMT events 549 * @hwdev: the NIC HW device 550 * @cmd: the mgmt event 551 **/ 552 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 553 enum hinic_mgmt_msg_cmd cmd) 554 { 555 struct hinic_hwif *hwif = hwdev->hwif; 556 struct hinic_pfhwdev *pfhwdev; 557 struct hinic_nic_cb *nic_cb; 558 u8 cmd_cb; 559 560 if (!HINIC_IS_PF(hwif) && !HINIC_IS_PPF(hwif)) 561 return; 562 563 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 564 565 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 566 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 567 568 nic_cb->cb_state &= ~HINIC_CB_ENABLED; 569 570 while (nic_cb->cb_state & HINIC_CB_RUNNING) 571 schedule(); 572 573 nic_cb->handler = NULL; 574 } 575 576 /** 577 * nic_mgmt_msg_handler - nic mgmt event handler 578 * @handle: private data for the handler 579 * @buf_in: input buffer 580 * @in_size: input size 581 * @buf_out: output buffer 582 * @out_size: returned output size 583 **/ 584 static void nic_mgmt_msg_handler(void *handle, u8 cmd, void *buf_in, 585 u16 in_size, void *buf_out, u16 *out_size) 586 { 587 struct hinic_pfhwdev *pfhwdev = handle; 588 enum hinic_cb_state cb_state; 589 struct hinic_nic_cb *nic_cb; 590 struct hinic_hwdev *hwdev; 591 struct hinic_hwif *hwif; 592 struct pci_dev *pdev; 593 u8 cmd_cb; 594 595 hwdev = &pfhwdev->hwdev; 596 hwif = hwdev->hwif; 597 pdev = hwif->pdev; 598 599 if ((cmd < HINIC_MGMT_MSG_CMD_BASE) || 600 (cmd >= HINIC_MGMT_MSG_CMD_MAX)) { 601 dev_err(&pdev->dev, "unknown L2NIC event, cmd = %d\n", cmd); 602 return; 603 } 604 605 cmd_cb = cmd - HINIC_MGMT_MSG_CMD_BASE; 606 607 nic_cb = &pfhwdev->nic_cb[cmd_cb]; 608 609 cb_state = cmpxchg(&nic_cb->cb_state, 610 HINIC_CB_ENABLED, 611 HINIC_CB_ENABLED | HINIC_CB_RUNNING); 612 613 if ((cb_state == HINIC_CB_ENABLED) && (nic_cb->handler)) 614 nic_cb->handler(nic_cb->handle, buf_in, 615 in_size, buf_out, out_size); 616 else 617 dev_err(&pdev->dev, "Unhandled NIC Event %d\n", cmd); 618 619 nic_cb->cb_state &= ~HINIC_CB_RUNNING; 620 } 621 622 /** 623 * init_pfhwdev - Initialize the extended components of PF 624 * @pfhwdev: the HW device for PF 625 * 626 * Return 0 - success, negative - failure 627 **/ 628 static int init_pfhwdev(struct hinic_pfhwdev *pfhwdev) 629 { 630 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 631 struct hinic_hwif *hwif = hwdev->hwif; 632 struct pci_dev *pdev = hwif->pdev; 633 int err; 634 635 err = hinic_pf_to_mgmt_init(&pfhwdev->pf_to_mgmt, hwif); 636 if (err) { 637 dev_err(&pdev->dev, "Failed to initialize PF to MGMT channel\n"); 638 return err; 639 } 640 641 err = hinic_func_to_func_init(hwdev); 642 if (err) { 643 dev_err(&hwif->pdev->dev, "Failed to init mailbox\n"); 644 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt); 645 return err; 646 } 647 648 if (!HINIC_IS_VF(hwif)) 649 hinic_register_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, 650 HINIC_MOD_L2NIC, pfhwdev, 651 nic_mgmt_msg_handler); 652 else 653 hinic_register_vf_mbox_cb(hwdev, HINIC_MOD_L2NIC, 654 nic_mgmt_msg_handler); 655 656 hinic_set_pf_action(hwif, HINIC_PF_MGMT_ACTIVE); 657 658 return 0; 659 } 660 661 /** 662 * free_pfhwdev - Free the extended components of PF 663 * @pfhwdev: the HW device for PF 664 **/ 665 static void free_pfhwdev(struct hinic_pfhwdev *pfhwdev) 666 { 667 struct hinic_hwdev *hwdev = &pfhwdev->hwdev; 668 669 hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT); 670 671 if (!HINIC_IS_VF(hwdev->hwif)) 672 hinic_unregister_mgmt_msg_cb(&pfhwdev->pf_to_mgmt, 673 HINIC_MOD_L2NIC); 674 else 675 hinic_unregister_vf_mbox_cb(hwdev, HINIC_MOD_L2NIC); 676 677 hinic_func_to_func_free(hwdev); 678 679 hinic_pf_to_mgmt_free(&pfhwdev->pf_to_mgmt); 680 } 681 682 static int hinic_l2nic_reset(struct hinic_hwdev *hwdev) 683 { 684 struct hinic_cmd_l2nic_reset l2nic_reset = {0}; 685 u16 out_size = sizeof(l2nic_reset); 686 struct hinic_pfhwdev *pfhwdev; 687 int err; 688 689 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 690 691 l2nic_reset.func_id = HINIC_HWIF_FUNC_IDX(hwdev->hwif); 692 /* 0 represents standard l2nic reset flow */ 693 l2nic_reset.reset_flag = 0; 694 695 err = hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, HINIC_MOD_COMM, 696 HINIC_COMM_CMD_L2NIC_RESET, &l2nic_reset, 697 sizeof(l2nic_reset), &l2nic_reset, 698 &out_size, HINIC_MGMT_MSG_SYNC); 699 if (err || !out_size || l2nic_reset.status) { 700 dev_err(&hwdev->hwif->pdev->dev, "Failed to reset L2NIC resources, err: %d, status: 0x%x, out_size: 0x%x\n", 701 err, l2nic_reset.status, out_size); 702 return -EIO; 703 } 704 705 return 0; 706 } 707 708 /** 709 * hinic_init_hwdev - Initialize the NIC HW 710 * @pdev: the NIC pci device 711 * 712 * Return initialized NIC HW device 713 * 714 * Initialize the NIC HW device and return a pointer to it 715 **/ 716 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev) 717 { 718 struct hinic_pfhwdev *pfhwdev; 719 struct hinic_hwdev *hwdev; 720 struct hinic_hwif *hwif; 721 int err, num_aeqs; 722 723 hwif = devm_kzalloc(&pdev->dev, sizeof(*hwif), GFP_KERNEL); 724 if (!hwif) 725 return ERR_PTR(-ENOMEM); 726 727 err = hinic_init_hwif(hwif, pdev); 728 if (err) { 729 dev_err(&pdev->dev, "Failed to init HW interface\n"); 730 return ERR_PTR(err); 731 } 732 733 pfhwdev = devm_kzalloc(&pdev->dev, sizeof(*pfhwdev), GFP_KERNEL); 734 if (!pfhwdev) { 735 err = -ENOMEM; 736 goto err_pfhwdev_alloc; 737 } 738 739 hwdev = &pfhwdev->hwdev; 740 hwdev->hwif = hwif; 741 742 err = init_msix(hwdev); 743 if (err) { 744 dev_err(&pdev->dev, "Failed to init msix\n"); 745 goto err_init_msix; 746 } 747 748 err = wait_for_outbound_state(hwdev); 749 if (err) { 750 dev_warn(&pdev->dev, "outbound - disabled, try again\n"); 751 hinic_outbound_state_set(hwif, HINIC_OUTBOUND_ENABLE); 752 } 753 754 num_aeqs = HINIC_HWIF_NUM_AEQS(hwif); 755 756 err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs, 757 HINIC_DEFAULT_AEQ_LEN, HINIC_EQ_PAGE_SIZE, 758 hwdev->msix_entries); 759 if (err) { 760 dev_err(&pdev->dev, "Failed to init async event queues\n"); 761 goto err_aeqs_init; 762 } 763 764 err = init_pfhwdev(pfhwdev); 765 if (err) { 766 dev_err(&pdev->dev, "Failed to init PF HW device\n"); 767 goto err_init_pfhwdev; 768 } 769 770 err = hinic_l2nic_reset(hwdev); 771 if (err) 772 goto err_l2nic_reset; 773 774 err = get_dev_cap(hwdev); 775 if (err) { 776 dev_err(&pdev->dev, "Failed to get device capabilities\n"); 777 goto err_dev_cap; 778 } 779 780 err = hinic_vf_func_init(hwdev); 781 if (err) { 782 dev_err(&pdev->dev, "Failed to init nic mbox\n"); 783 goto err_vf_func_init; 784 } 785 786 err = init_fw_ctxt(hwdev); 787 if (err) { 788 dev_err(&pdev->dev, "Failed to init function table\n"); 789 goto err_init_fw_ctxt; 790 } 791 792 err = set_resources_state(hwdev, HINIC_RES_ACTIVE); 793 if (err) { 794 dev_err(&pdev->dev, "Failed to set resources state\n"); 795 goto err_resources_state; 796 } 797 798 return hwdev; 799 800 err_resources_state: 801 err_init_fw_ctxt: 802 hinic_vf_func_free(hwdev); 803 err_vf_func_init: 804 err_l2nic_reset: 805 err_dev_cap: 806 free_pfhwdev(pfhwdev); 807 808 err_init_pfhwdev: 809 hinic_aeqs_free(&hwdev->aeqs); 810 811 err_aeqs_init: 812 disable_msix(hwdev); 813 814 err_init_msix: 815 err_pfhwdev_alloc: 816 hinic_free_hwif(hwif); 817 return ERR_PTR(err); 818 } 819 820 /** 821 * hinic_free_hwdev - Free the NIC HW device 822 * @hwdev: the NIC HW device 823 **/ 824 void hinic_free_hwdev(struct hinic_hwdev *hwdev) 825 { 826 struct hinic_pfhwdev *pfhwdev = container_of(hwdev, 827 struct hinic_pfhwdev, 828 hwdev); 829 830 set_resources_state(hwdev, HINIC_RES_CLEAN); 831 832 free_pfhwdev(pfhwdev); 833 834 hinic_aeqs_free(&hwdev->aeqs); 835 836 disable_msix(hwdev); 837 838 hinic_free_hwif(hwdev->hwif); 839 } 840 841 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev) 842 { 843 struct hinic_cap *nic_cap = &hwdev->nic_cap; 844 845 return nic_cap->max_qps; 846 } 847 848 /** 849 * hinic_hwdev_num_qps - return the number QPs available for use 850 * @hwdev: the NIC HW device 851 * 852 * Return number QPs available for use 853 **/ 854 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev) 855 { 856 struct hinic_cap *nic_cap = &hwdev->nic_cap; 857 858 return nic_cap->num_qps; 859 } 860 861 /** 862 * hinic_hwdev_get_sq - get SQ 863 * @hwdev: the NIC HW device 864 * @i: the position of the SQ 865 * 866 * Return: the SQ in the i position 867 **/ 868 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i) 869 { 870 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 871 struct hinic_qp *qp = &func_to_io->qps[i]; 872 873 if (i >= hinic_hwdev_num_qps(hwdev)) 874 return NULL; 875 876 return &qp->sq; 877 } 878 879 /** 880 * hinic_hwdev_get_sq - get RQ 881 * @hwdev: the NIC HW device 882 * @i: the position of the RQ 883 * 884 * Return: the RQ in the i position 885 **/ 886 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i) 887 { 888 struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; 889 struct hinic_qp *qp = &func_to_io->qps[i]; 890 891 if (i >= hinic_hwdev_num_qps(hwdev)) 892 return NULL; 893 894 return &qp->rq; 895 } 896 897 /** 898 * hinic_hwdev_msix_cnt_set - clear message attribute counters for msix entry 899 * @hwdev: the NIC HW device 900 * @msix_index: msix_index 901 * 902 * Return 0 - Success, negative - Failure 903 **/ 904 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index) 905 { 906 return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index); 907 } 908 909 /** 910 * hinic_hwdev_msix_set - set message attribute for msix entry 911 * @hwdev: the NIC HW device 912 * @msix_index: msix_index 913 * @pending_limit: the maximum pending interrupt events (unit 8) 914 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 915 * @lli_timer: replenishing period for low latency credit (unit 8 us) 916 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 917 * @resend_timer: maximum wait for resending msix (unit coalesc period) 918 * 919 * Return 0 - Success, negative - Failure 920 **/ 921 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 922 u8 pending_limit, u8 coalesc_timer, 923 u8 lli_timer_cfg, u8 lli_credit_limit, 924 u8 resend_timer) 925 { 926 return hinic_msix_attr_set(hwdev->hwif, msix_index, 927 pending_limit, coalesc_timer, 928 lli_timer_cfg, lli_credit_limit, 929 resend_timer); 930 } 931 932 /** 933 * hinic_hwdev_hw_ci_addr_set - set cons idx addr and attributes in HW for sq 934 * @hwdev: the NIC HW device 935 * @sq: send queue 936 * @pending_limit: the maximum pending update ci events (unit 8) 937 * @coalesc_timer: coalesc period for update ci (unit 8 us) 938 * 939 * Return 0 - Success, negative - Failure 940 **/ 941 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 942 u8 pending_limit, u8 coalesc_timer) 943 { 944 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq); 945 struct hinic_hwif *hwif = hwdev->hwif; 946 struct hinic_pfhwdev *pfhwdev; 947 struct hinic_cmd_hw_ci hw_ci; 948 949 hw_ci.dma_attr_off = 0; 950 hw_ci.pending_limit = pending_limit; 951 hw_ci.coalesc_timer = coalesc_timer; 952 953 hw_ci.msix_en = 1; 954 hw_ci.msix_entry_idx = sq->msix_entry; 955 956 hw_ci.func_idx = HINIC_HWIF_FUNC_IDX(hwif); 957 958 hw_ci.sq_id = qp->q_id; 959 960 hw_ci.ci_addr = ADDR_IN_4BYTES(sq->hw_ci_dma_addr); 961 962 pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); 963 return hinic_msg_to_mgmt(&pfhwdev->pf_to_mgmt, 964 HINIC_MOD_COMM, 965 HINIC_COMM_CMD_SQ_HI_CI_SET, 966 &hw_ci, sizeof(hw_ci), NULL, 967 NULL, HINIC_MGMT_MSG_SYNC); 968 } 969 970 /** 971 * hinic_hwdev_set_msix_state- set msix state 972 * @hwdev: the NIC HW device 973 * @msix_index: IRQ corresponding index number 974 * @flag: msix state 975 * 976 **/ 977 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 978 enum hinic_msix_state flag) 979 { 980 hinic_set_msix_state(hwdev->hwif, msix_index, flag); 981 } 982