1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NAND Chip and NAND Controller Generic Binding
8
9maintainers:
10  - Miquel Raynal <miquel.raynal@bootlin.com>
11  - Richard Weinberger <richard@nod.at>
12
13description: |
14  The NAND controller should be represented with its own DT node, and
15  all NAND chips attached to this controller should be defined as
16  children nodes of the NAND controller. This representation should be
17  enforced even for simple controllers supporting only one chip.
18
19  The ECC strength and ECC step size properties define the user
20  desires in terms of correction capability of a controller. Together,
21  they request the ECC engine to correct {strength} bit errors per
22  {size} bytes.
23
24  The interpretation of these parameters is implementation-defined, so
25  not all implementations must support all possible
26  combinations. However, implementations are encouraged to further
27  specify the value(s) they support.
28
29properties:
30  $nodename:
31    pattern: "^nand-controller(@.*)?"
32
33  "#address-cells":
34    const: 1
35
36  "#size-cells":
37    const: 0
38
39  ranges: true
40
41patternProperties:
42  "^nand@[a-f0-9]$":
43    type: object
44    properties:
45      reg:
46        description:
47          Contains the native Ready/Busy IDs.
48
49      nand-ecc-mode:
50        description:
51          Desired ECC engine, either hardware (most of the time
52          embedded in the NAND controller) or software correction
53          (Linux will handle the calculations). soft_bch is deprecated
54          and should be replaced by soft and nand-ecc-algo.
55        $ref: /schemas/types.yaml#/definitions/string
56        enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
57
58      nand-ecc-algo:
59        description:
60          Desired ECC algorithm.
61        $ref: /schemas/types.yaml#/definitions/string
62        enum: [hamming, bch, rs]
63
64      nand-bus-width:
65        description:
66          Bus width to the NAND chip
67        $ref: /schemas/types.yaml#/definitions/uint32
68        enum: [8, 16]
69        default: 8
70
71      nand-on-flash-bbt:
72        $ref: /schemas/types.yaml#/definitions/flag
73        description:
74          With this property, the OS will search the device for a Bad
75          Block Table (BBT). If not found, it will create one, reserve
76          a few blocks at the end of the device to store it and update
77          it as the device ages. Otherwise, the out-of-band area of a
78          few pages of all the blocks will be scanned at boot time to
79          find Bad Block Markers (BBM). These markers will help to
80          build a volatile BBT in RAM.
81
82      nand-ecc-strength:
83        description:
84          Maximum number of bits that can be corrected per ECC step.
85        $ref: /schemas/types.yaml#/definitions/uint32
86        minimum: 1
87
88      nand-ecc-step-size:
89        description:
90          Number of data bytes covered by a single ECC step.
91        $ref: /schemas/types.yaml#/definitions/uint32
92        minimum: 1
93
94      nand-ecc-maximize:
95        $ref: /schemas/types.yaml#/definitions/flag
96        description:
97          Whether or not the ECC strength should be maximized. The
98          maximum ECC strength is both controller and chip
99          dependent. The ECC engine has to select the ECC config
100          providing the best strength and taking the OOB area size
101          constraint into account. This is particularly useful when
102          only the in-band area is used by the upper layers, and you
103          want to make your NAND as reliable as possible.
104
105      nand-is-boot-medium:
106        $ref: /schemas/types.yaml#/definitions/flag
107        description:
108          Whether or not the NAND chip is a boot medium. Drivers might
109          use this information to select ECC algorithms supported by
110          the boot ROM or similar restrictions.
111
112      nand-rb:
113        $ref: /schemas/types.yaml#/definitions/uint32-array
114        description:
115          Contains the native Ready/Busy IDs.
116
117      rb-gpios:
118        description:
119          Contains one or more GPIO descriptor (the numper of descriptor
120          depends on the number of R/B pins exposed by the flash) for the
121          Ready/Busy pins. Active state refers to the NAND ready state and
122          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
123
124    required:
125      - reg
126
127required:
128  - "#address-cells"
129  - "#size-cells"
130
131examples:
132  - |
133    nand-controller {
134      #address-cells = <1>;
135      #size-cells = <0>;
136
137      /* controller specific properties */
138
139      nand@0 {
140        reg = <0>;
141        nand-ecc-mode = "soft";
142        nand-ecc-algo = "bch";
143
144        /* controller specific properties */
145      };
146    };
147