1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/ip.h> 12 #include <linux/ipv6.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/aer.h> 16 #include <linux/skbuff.h> 17 #include <linux/sctp.h> 18 #include <linux/vermagic.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 25 #include "hnae3.h" 26 #include "hns3_enet.h" 27 /* All hns3 tracepoints are defined by the include below, which 28 * must be included exactly once across the whole kernel with 29 * CREATE_TRACE_POINTS defined 30 */ 31 #define CREATE_TRACE_POINTS 32 #include "hns3_trace.h" 33 34 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 35 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 36 37 #define hns3_rl_err(fmt, ...) \ 38 do { \ 39 if (net_ratelimit()) \ 40 netdev_err(fmt, ##__VA_ARGS__); \ 41 } while (0) 42 43 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 44 static void hns3_remove_hw_addr(struct net_device *netdev); 45 46 static const char hns3_driver_name[] = "hns3"; 47 const char hns3_driver_version[] = VERMAGIC_STRING; 48 static const char hns3_driver_string[] = 49 "Hisilicon Ethernet Network Driver for Hip08 Family"; 50 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 51 static struct hnae3_client client; 52 53 static int debug = -1; 54 module_param(debug, int, 0); 55 MODULE_PARM_DESC(debug, " Network interface message level setting"); 56 57 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 58 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 59 60 #define HNS3_INNER_VLAN_TAG 1 61 #define HNS3_OUTER_VLAN_TAG 2 62 63 #define HNS3_MIN_TX_LEN 33U 64 65 /* hns3_pci_tbl - PCI Device ID Table 66 * 67 * Last entry must be all 0s 68 * 69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 70 * Class, Class Mask, private data (not used) } 71 */ 72 static const struct pci_device_id hns3_pci_tbl[] = { 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 78 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 79 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 80 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 82 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 84 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 87 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 88 /* required last entry */ 89 {0, } 90 }; 91 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 92 93 static irqreturn_t hns3_irq_handle(int irq, void *vector) 94 { 95 struct hns3_enet_tqp_vector *tqp_vector = vector; 96 97 napi_schedule_irqoff(&tqp_vector->napi); 98 99 return IRQ_HANDLED; 100 } 101 102 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 103 { 104 struct hns3_enet_tqp_vector *tqp_vectors; 105 unsigned int i; 106 107 for (i = 0; i < priv->vector_num; i++) { 108 tqp_vectors = &priv->tqp_vector[i]; 109 110 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 111 continue; 112 113 /* clear the affinity mask */ 114 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 115 116 /* release the irq resource */ 117 free_irq(tqp_vectors->vector_irq, tqp_vectors); 118 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 119 } 120 } 121 122 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 123 { 124 struct hns3_enet_tqp_vector *tqp_vectors; 125 int txrx_int_idx = 0; 126 int rx_int_idx = 0; 127 int tx_int_idx = 0; 128 unsigned int i; 129 int ret; 130 131 for (i = 0; i < priv->vector_num; i++) { 132 tqp_vectors = &priv->tqp_vector[i]; 133 134 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 135 continue; 136 137 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 138 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 139 "%s-%s-%s-%d", hns3_driver_name, 140 pci_name(priv->ae_handle->pdev), 141 "TxRx", txrx_int_idx++); 142 txrx_int_idx++; 143 } else if (tqp_vectors->rx_group.ring) { 144 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 145 "%s-%s-%s-%d", hns3_driver_name, 146 pci_name(priv->ae_handle->pdev), 147 "Rx", rx_int_idx++); 148 } else if (tqp_vectors->tx_group.ring) { 149 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 150 "%s-%s-%s-%d", hns3_driver_name, 151 pci_name(priv->ae_handle->pdev), 152 "Tx", tx_int_idx++); 153 } else { 154 /* Skip this unused q_vector */ 155 continue; 156 } 157 158 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 159 160 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 161 tqp_vectors->name, tqp_vectors); 162 if (ret) { 163 netdev_err(priv->netdev, "request irq(%d) fail\n", 164 tqp_vectors->vector_irq); 165 hns3_nic_uninit_irq(priv); 166 return ret; 167 } 168 169 disable_irq(tqp_vectors->vector_irq); 170 171 irq_set_affinity_hint(tqp_vectors->vector_irq, 172 &tqp_vectors->affinity_mask); 173 174 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 175 } 176 177 return 0; 178 } 179 180 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 181 u32 mask_en) 182 { 183 writel(mask_en, tqp_vector->mask_addr); 184 } 185 186 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 187 { 188 napi_enable(&tqp_vector->napi); 189 enable_irq(tqp_vector->vector_irq); 190 191 /* enable vector */ 192 hns3_mask_vector_irq(tqp_vector, 1); 193 } 194 195 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 196 { 197 /* disable vector */ 198 hns3_mask_vector_irq(tqp_vector, 0); 199 200 disable_irq(tqp_vector->vector_irq); 201 napi_disable(&tqp_vector->napi); 202 } 203 204 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 205 u32 rl_value) 206 { 207 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 208 209 /* this defines the configuration for RL (Interrupt Rate Limiter). 210 * Rl defines rate of interrupts i.e. number of interrupts-per-second 211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 212 */ 213 214 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 215 !tqp_vector->rx_group.coal.gl_adapt_enable) 216 /* According to the hardware, the range of rl_reg is 217 * 0-59 and the unit is 4. 218 */ 219 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 220 221 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 222 } 223 224 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 225 u32 gl_value) 226 { 227 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 228 229 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 230 } 231 232 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 233 u32 gl_value) 234 { 235 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 236 237 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 238 } 239 240 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 241 struct hns3_nic_priv *priv) 242 { 243 /* initialize the configuration for interrupt coalescing. 244 * 1. GL (Interrupt Gap Limiter) 245 * 2. RL (Interrupt Rate Limiter) 246 * 247 * Default: enable interrupt coalescing self-adaptive and GL 248 */ 249 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 250 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 251 252 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 253 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 254 255 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 256 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 257 } 258 259 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 260 struct hns3_nic_priv *priv) 261 { 262 struct hnae3_handle *h = priv->ae_handle; 263 264 hns3_set_vector_coalesce_tx_gl(tqp_vector, 265 tqp_vector->tx_group.coal.int_gl); 266 hns3_set_vector_coalesce_rx_gl(tqp_vector, 267 tqp_vector->rx_group.coal.int_gl); 268 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 269 } 270 271 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 272 { 273 struct hnae3_handle *h = hns3_get_handle(netdev); 274 struct hnae3_knic_private_info *kinfo = &h->kinfo; 275 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 276 int i, ret; 277 278 if (kinfo->num_tc <= 1) { 279 netdev_reset_tc(netdev); 280 } else { 281 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 282 if (ret) { 283 netdev_err(netdev, 284 "netdev_set_num_tc fail, ret=%d!\n", ret); 285 return ret; 286 } 287 288 for (i = 0; i < HNAE3_MAX_TC; i++) { 289 if (!kinfo->tc_info[i].enable) 290 continue; 291 292 netdev_set_tc_queue(netdev, 293 kinfo->tc_info[i].tc, 294 kinfo->tc_info[i].tqp_count, 295 kinfo->tc_info[i].tqp_offset); 296 } 297 } 298 299 ret = netif_set_real_num_tx_queues(netdev, queue_size); 300 if (ret) { 301 netdev_err(netdev, 302 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 303 return ret; 304 } 305 306 ret = netif_set_real_num_rx_queues(netdev, queue_size); 307 if (ret) { 308 netdev_err(netdev, 309 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 310 return ret; 311 } 312 313 return 0; 314 } 315 316 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 317 { 318 u16 alloc_tqps, max_rss_size, rss_size; 319 320 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 321 rss_size = alloc_tqps / h->kinfo.num_tc; 322 323 return min_t(u16, rss_size, max_rss_size); 324 } 325 326 static void hns3_tqp_enable(struct hnae3_queue *tqp) 327 { 328 u32 rcb_reg; 329 330 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 331 rcb_reg |= BIT(HNS3_RING_EN_B); 332 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 333 } 334 335 static void hns3_tqp_disable(struct hnae3_queue *tqp) 336 { 337 u32 rcb_reg; 338 339 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 340 rcb_reg &= ~BIT(HNS3_RING_EN_B); 341 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 342 } 343 344 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 345 { 346 #ifdef CONFIG_RFS_ACCEL 347 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 348 netdev->rx_cpu_rmap = NULL; 349 #endif 350 } 351 352 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 353 { 354 #ifdef CONFIG_RFS_ACCEL 355 struct hns3_nic_priv *priv = netdev_priv(netdev); 356 struct hns3_enet_tqp_vector *tqp_vector; 357 int i, ret; 358 359 if (!netdev->rx_cpu_rmap) { 360 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 361 if (!netdev->rx_cpu_rmap) 362 return -ENOMEM; 363 } 364 365 for (i = 0; i < priv->vector_num; i++) { 366 tqp_vector = &priv->tqp_vector[i]; 367 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 368 tqp_vector->vector_irq); 369 if (ret) { 370 hns3_free_rx_cpu_rmap(netdev); 371 return ret; 372 } 373 } 374 #endif 375 return 0; 376 } 377 378 static int hns3_nic_net_up(struct net_device *netdev) 379 { 380 struct hns3_nic_priv *priv = netdev_priv(netdev); 381 struct hnae3_handle *h = priv->ae_handle; 382 int i, j; 383 int ret; 384 385 ret = hns3_nic_reset_all_ring(h); 386 if (ret) 387 return ret; 388 389 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 390 391 /* enable the vectors */ 392 for (i = 0; i < priv->vector_num; i++) 393 hns3_vector_enable(&priv->tqp_vector[i]); 394 395 /* enable rcb */ 396 for (j = 0; j < h->kinfo.num_tqps; j++) 397 hns3_tqp_enable(h->kinfo.tqp[j]); 398 399 /* start the ae_dev */ 400 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 401 if (ret) { 402 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 403 while (j--) 404 hns3_tqp_disable(h->kinfo.tqp[j]); 405 406 for (j = i - 1; j >= 0; j--) 407 hns3_vector_disable(&priv->tqp_vector[j]); 408 } 409 410 return ret; 411 } 412 413 static void hns3_config_xps(struct hns3_nic_priv *priv) 414 { 415 int i; 416 417 for (i = 0; i < priv->vector_num; i++) { 418 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 419 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 420 421 while (ring) { 422 int ret; 423 424 ret = netif_set_xps_queue(priv->netdev, 425 &tqp_vector->affinity_mask, 426 ring->tqp->tqp_index); 427 if (ret) 428 netdev_warn(priv->netdev, 429 "set xps queue failed: %d", ret); 430 431 ring = ring->next; 432 } 433 } 434 } 435 436 static int hns3_nic_net_open(struct net_device *netdev) 437 { 438 struct hns3_nic_priv *priv = netdev_priv(netdev); 439 struct hnae3_handle *h = hns3_get_handle(netdev); 440 struct hnae3_knic_private_info *kinfo; 441 int i, ret; 442 443 if (hns3_nic_resetting(netdev)) 444 return -EBUSY; 445 446 netif_carrier_off(netdev); 447 448 ret = hns3_nic_set_real_num_queue(netdev); 449 if (ret) 450 return ret; 451 452 ret = hns3_nic_net_up(netdev); 453 if (ret) { 454 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 455 return ret; 456 } 457 458 kinfo = &h->kinfo; 459 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 460 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 461 462 if (h->ae_algo->ops->set_timer_task) 463 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 464 465 hns3_config_xps(priv); 466 467 netif_dbg(h, drv, netdev, "net open\n"); 468 469 return 0; 470 } 471 472 static void hns3_reset_tx_queue(struct hnae3_handle *h) 473 { 474 struct net_device *ndev = h->kinfo.netdev; 475 struct hns3_nic_priv *priv = netdev_priv(ndev); 476 struct netdev_queue *dev_queue; 477 u32 i; 478 479 for (i = 0; i < h->kinfo.num_tqps; i++) { 480 dev_queue = netdev_get_tx_queue(ndev, 481 priv->ring[i].queue_index); 482 netdev_tx_reset_queue(dev_queue); 483 } 484 } 485 486 static void hns3_nic_net_down(struct net_device *netdev) 487 { 488 struct hns3_nic_priv *priv = netdev_priv(netdev); 489 struct hnae3_handle *h = hns3_get_handle(netdev); 490 const struct hnae3_ae_ops *ops; 491 int i; 492 493 /* disable vectors */ 494 for (i = 0; i < priv->vector_num; i++) 495 hns3_vector_disable(&priv->tqp_vector[i]); 496 497 /* disable rcb */ 498 for (i = 0; i < h->kinfo.num_tqps; i++) 499 hns3_tqp_disable(h->kinfo.tqp[i]); 500 501 /* stop ae_dev */ 502 ops = priv->ae_handle->ae_algo->ops; 503 if (ops->stop) 504 ops->stop(priv->ae_handle); 505 506 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 507 * during reset process, because driver may not be able 508 * to disable the ring through firmware when downing the netdev. 509 */ 510 if (!hns3_nic_resetting(netdev)) 511 hns3_clear_all_ring(priv->ae_handle, false); 512 513 hns3_reset_tx_queue(priv->ae_handle); 514 } 515 516 static int hns3_nic_net_stop(struct net_device *netdev) 517 { 518 struct hns3_nic_priv *priv = netdev_priv(netdev); 519 struct hnae3_handle *h = hns3_get_handle(netdev); 520 521 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 522 return 0; 523 524 netif_dbg(h, drv, netdev, "net stop\n"); 525 526 if (h->ae_algo->ops->set_timer_task) 527 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 528 529 netif_tx_stop_all_queues(netdev); 530 netif_carrier_off(netdev); 531 532 hns3_nic_net_down(netdev); 533 534 return 0; 535 } 536 537 static int hns3_nic_uc_sync(struct net_device *netdev, 538 const unsigned char *addr) 539 { 540 struct hnae3_handle *h = hns3_get_handle(netdev); 541 542 if (h->ae_algo->ops->add_uc_addr) 543 return h->ae_algo->ops->add_uc_addr(h, addr); 544 545 return 0; 546 } 547 548 static int hns3_nic_uc_unsync(struct net_device *netdev, 549 const unsigned char *addr) 550 { 551 struct hnae3_handle *h = hns3_get_handle(netdev); 552 553 if (h->ae_algo->ops->rm_uc_addr) 554 return h->ae_algo->ops->rm_uc_addr(h, addr); 555 556 return 0; 557 } 558 559 static int hns3_nic_mc_sync(struct net_device *netdev, 560 const unsigned char *addr) 561 { 562 struct hnae3_handle *h = hns3_get_handle(netdev); 563 564 if (h->ae_algo->ops->add_mc_addr) 565 return h->ae_algo->ops->add_mc_addr(h, addr); 566 567 return 0; 568 } 569 570 static int hns3_nic_mc_unsync(struct net_device *netdev, 571 const unsigned char *addr) 572 { 573 struct hnae3_handle *h = hns3_get_handle(netdev); 574 575 if (h->ae_algo->ops->rm_mc_addr) 576 return h->ae_algo->ops->rm_mc_addr(h, addr); 577 578 return 0; 579 } 580 581 static u8 hns3_get_netdev_flags(struct net_device *netdev) 582 { 583 u8 flags = 0; 584 585 if (netdev->flags & IFF_PROMISC) { 586 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 587 } else { 588 flags |= HNAE3_VLAN_FLTR; 589 if (netdev->flags & IFF_ALLMULTI) 590 flags |= HNAE3_USER_MPE; 591 } 592 593 return flags; 594 } 595 596 static void hns3_nic_set_rx_mode(struct net_device *netdev) 597 { 598 struct hnae3_handle *h = hns3_get_handle(netdev); 599 u8 new_flags; 600 int ret; 601 602 new_flags = hns3_get_netdev_flags(netdev); 603 604 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 605 if (ret) { 606 netdev_err(netdev, "sync uc address fail\n"); 607 if (ret == -ENOSPC) 608 new_flags |= HNAE3_OVERFLOW_UPE; 609 } 610 611 if (netdev->flags & IFF_MULTICAST) { 612 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 613 hns3_nic_mc_unsync); 614 if (ret) { 615 netdev_err(netdev, "sync mc address fail\n"); 616 if (ret == -ENOSPC) 617 new_flags |= HNAE3_OVERFLOW_MPE; 618 } 619 } 620 621 /* User mode Promisc mode enable and vlan filtering is disabled to 622 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 623 * vlan fitering is enabled 624 */ 625 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 626 h->netdev_flags = new_flags; 627 hns3_update_promisc_mode(netdev, new_flags); 628 } 629 630 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 631 { 632 struct hns3_nic_priv *priv = netdev_priv(netdev); 633 struct hnae3_handle *h = priv->ae_handle; 634 635 if (h->ae_algo->ops->set_promisc_mode) { 636 return h->ae_algo->ops->set_promisc_mode(h, 637 promisc_flags & HNAE3_UPE, 638 promisc_flags & HNAE3_MPE); 639 } 640 641 return 0; 642 } 643 644 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 645 { 646 struct hns3_nic_priv *priv = netdev_priv(netdev); 647 struct hnae3_handle *h = priv->ae_handle; 648 bool last_state; 649 650 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 651 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 652 if (enable != last_state) { 653 netdev_info(netdev, 654 "%s vlan filter\n", 655 enable ? "enable" : "disable"); 656 h->ae_algo->ops->enable_vlan_filter(h, enable); 657 } 658 } 659 } 660 661 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 662 u16 *mss, u32 *type_cs_vlan_tso) 663 { 664 u32 l4_offset, hdr_len; 665 union l3_hdr_info l3; 666 union l4_hdr_info l4; 667 u32 l4_paylen; 668 int ret; 669 670 if (!skb_is_gso(skb)) 671 return 0; 672 673 ret = skb_cow_head(skb, 0); 674 if (unlikely(ret < 0)) 675 return ret; 676 677 l3.hdr = skb_network_header(skb); 678 l4.hdr = skb_transport_header(skb); 679 680 /* Software should clear the IPv4's checksum field when tso is 681 * needed. 682 */ 683 if (l3.v4->version == 4) 684 l3.v4->check = 0; 685 686 /* tunnel packet */ 687 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 688 SKB_GSO_GRE_CSUM | 689 SKB_GSO_UDP_TUNNEL | 690 SKB_GSO_UDP_TUNNEL_CSUM)) { 691 if ((!(skb_shinfo(skb)->gso_type & 692 SKB_GSO_PARTIAL)) && 693 (skb_shinfo(skb)->gso_type & 694 SKB_GSO_UDP_TUNNEL_CSUM)) { 695 /* Software should clear the udp's checksum 696 * field when tso is needed. 697 */ 698 l4.udp->check = 0; 699 } 700 /* reset l3&l4 pointers from outer to inner headers */ 701 l3.hdr = skb_inner_network_header(skb); 702 l4.hdr = skb_inner_transport_header(skb); 703 704 /* Software should clear the IPv4's checksum field when 705 * tso is needed. 706 */ 707 if (l3.v4->version == 4) 708 l3.v4->check = 0; 709 } 710 711 /* normal or tunnel packet */ 712 l4_offset = l4.hdr - skb->data; 713 hdr_len = (l4.tcp->doff << 2) + l4_offset; 714 715 /* remove payload length from inner pseudo checksum when tso */ 716 l4_paylen = skb->len - l4_offset; 717 csum_replace_by_diff(&l4.tcp->check, 718 (__force __wsum)htonl(l4_paylen)); 719 720 /* find the txbd field values */ 721 *paylen = skb->len - hdr_len; 722 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 723 724 /* get MSS for TSO */ 725 *mss = skb_shinfo(skb)->gso_size; 726 727 trace_hns3_tso(skb); 728 729 return 0; 730 } 731 732 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 733 u8 *il4_proto) 734 { 735 union l3_hdr_info l3; 736 unsigned char *l4_hdr; 737 unsigned char *exthdr; 738 u8 l4_proto_tmp; 739 __be16 frag_off; 740 741 /* find outer header point */ 742 l3.hdr = skb_network_header(skb); 743 l4_hdr = skb_transport_header(skb); 744 745 if (skb->protocol == htons(ETH_P_IPV6)) { 746 exthdr = l3.hdr + sizeof(*l3.v6); 747 l4_proto_tmp = l3.v6->nexthdr; 748 if (l4_hdr != exthdr) 749 ipv6_skip_exthdr(skb, exthdr - skb->data, 750 &l4_proto_tmp, &frag_off); 751 } else if (skb->protocol == htons(ETH_P_IP)) { 752 l4_proto_tmp = l3.v4->protocol; 753 } else { 754 return -EINVAL; 755 } 756 757 *ol4_proto = l4_proto_tmp; 758 759 /* tunnel packet */ 760 if (!skb->encapsulation) { 761 *il4_proto = 0; 762 return 0; 763 } 764 765 /* find inner header point */ 766 l3.hdr = skb_inner_network_header(skb); 767 l4_hdr = skb_inner_transport_header(skb); 768 769 if (l3.v6->version == 6) { 770 exthdr = l3.hdr + sizeof(*l3.v6); 771 l4_proto_tmp = l3.v6->nexthdr; 772 if (l4_hdr != exthdr) 773 ipv6_skip_exthdr(skb, exthdr - skb->data, 774 &l4_proto_tmp, &frag_off); 775 } else if (l3.v4->version == 4) { 776 l4_proto_tmp = l3.v4->protocol; 777 } 778 779 *il4_proto = l4_proto_tmp; 780 781 return 0; 782 } 783 784 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 785 * and it is udp packet, which has a dest port as the IANA assigned. 786 * the hardware is expected to do the checksum offload, but the 787 * hardware will not do the checksum offload when udp dest port is 788 * 4789. 789 */ 790 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 791 { 792 union l4_hdr_info l4; 793 794 l4.hdr = skb_transport_header(skb); 795 796 if (!(!skb->encapsulation && 797 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT))) 798 return false; 799 800 skb_checksum_help(skb); 801 802 return true; 803 } 804 805 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 806 u32 *ol_type_vlan_len_msec) 807 { 808 u32 l2_len, l3_len, l4_len; 809 unsigned char *il2_hdr; 810 union l3_hdr_info l3; 811 union l4_hdr_info l4; 812 813 l3.hdr = skb_network_header(skb); 814 l4.hdr = skb_transport_header(skb); 815 816 /* compute OL2 header size, defined in 2 Bytes */ 817 l2_len = l3.hdr - skb->data; 818 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 819 820 /* compute OL3 header size, defined in 4 Bytes */ 821 l3_len = l4.hdr - l3.hdr; 822 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 823 824 il2_hdr = skb_inner_mac_header(skb); 825 /* compute OL4 header size, defined in 4 Bytes */ 826 l4_len = il2_hdr - l4.hdr; 827 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 828 829 /* define outer network header type */ 830 if (skb->protocol == htons(ETH_P_IP)) { 831 if (skb_is_gso(skb)) 832 hns3_set_field(*ol_type_vlan_len_msec, 833 HNS3_TXD_OL3T_S, 834 HNS3_OL3T_IPV4_CSUM); 835 else 836 hns3_set_field(*ol_type_vlan_len_msec, 837 HNS3_TXD_OL3T_S, 838 HNS3_OL3T_IPV4_NO_CSUM); 839 840 } else if (skb->protocol == htons(ETH_P_IPV6)) { 841 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 842 HNS3_OL3T_IPV6); 843 } 844 845 if (ol4_proto == IPPROTO_UDP) 846 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 847 HNS3_TUN_MAC_IN_UDP); 848 else if (ol4_proto == IPPROTO_GRE) 849 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 850 HNS3_TUN_NVGRE); 851 } 852 853 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 854 u8 il4_proto, u32 *type_cs_vlan_tso, 855 u32 *ol_type_vlan_len_msec) 856 { 857 unsigned char *l2_hdr = skb->data; 858 u32 l4_proto = ol4_proto; 859 union l4_hdr_info l4; 860 union l3_hdr_info l3; 861 u32 l2_len, l3_len; 862 863 l4.hdr = skb_transport_header(skb); 864 l3.hdr = skb_network_header(skb); 865 866 /* handle encapsulation skb */ 867 if (skb->encapsulation) { 868 /* If this is a not UDP/GRE encapsulation skb */ 869 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 870 /* drop the skb tunnel packet if hardware don't support, 871 * because hardware can't calculate csum when TSO. 872 */ 873 if (skb_is_gso(skb)) 874 return -EDOM; 875 876 /* the stack computes the IP header already, 877 * driver calculate l4 checksum when not TSO. 878 */ 879 skb_checksum_help(skb); 880 return 0; 881 } 882 883 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 884 885 /* switch to inner header */ 886 l2_hdr = skb_inner_mac_header(skb); 887 l3.hdr = skb_inner_network_header(skb); 888 l4.hdr = skb_inner_transport_header(skb); 889 l4_proto = il4_proto; 890 } 891 892 if (l3.v4->version == 4) { 893 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 894 HNS3_L3T_IPV4); 895 896 /* the stack computes the IP header already, the only time we 897 * need the hardware to recompute it is in the case of TSO. 898 */ 899 if (skb_is_gso(skb)) 900 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 901 } else if (l3.v6->version == 6) { 902 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 903 HNS3_L3T_IPV6); 904 } 905 906 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 907 l2_len = l3.hdr - l2_hdr; 908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 909 910 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 911 l3_len = l4.hdr - l3.hdr; 912 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 913 914 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 915 switch (l4_proto) { 916 case IPPROTO_TCP: 917 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 918 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 919 HNS3_L4T_TCP); 920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 921 l4.tcp->doff); 922 break; 923 case IPPROTO_UDP: 924 if (hns3_tunnel_csum_bug(skb)) 925 break; 926 927 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 929 HNS3_L4T_UDP); 930 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 931 (sizeof(struct udphdr) >> 2)); 932 break; 933 case IPPROTO_SCTP: 934 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 935 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 936 HNS3_L4T_SCTP); 937 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 938 (sizeof(struct sctphdr) >> 2)); 939 break; 940 default: 941 /* drop the skb tunnel packet if hardware don't support, 942 * because hardware can't calculate csum when TSO. 943 */ 944 if (skb_is_gso(skb)) 945 return -EDOM; 946 947 /* the stack computes the IP header already, 948 * driver calculate l4 checksum when not TSO. 949 */ 950 skb_checksum_help(skb); 951 return 0; 952 } 953 954 return 0; 955 } 956 957 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 958 struct sk_buff *skb) 959 { 960 struct hnae3_handle *handle = tx_ring->tqp->handle; 961 struct vlan_ethhdr *vhdr; 962 int rc; 963 964 if (!(skb->protocol == htons(ETH_P_8021Q) || 965 skb_vlan_tag_present(skb))) 966 return 0; 967 968 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 969 * header is allowed in skb, otherwise it will cause RAS error. 970 */ 971 if (unlikely(skb_vlan_tagged_multi(skb) && 972 handle->port_base_vlan_state == 973 HNAE3_PORT_BASE_VLAN_ENABLE)) 974 return -EINVAL; 975 976 if (skb->protocol == htons(ETH_P_8021Q) && 977 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 978 /* When HW VLAN acceleration is turned off, and the stack 979 * sets the protocol to 802.1q, the driver just need to 980 * set the protocol to the encapsulated ethertype. 981 */ 982 skb->protocol = vlan_get_protocol(skb); 983 return 0; 984 } 985 986 if (skb_vlan_tag_present(skb)) { 987 /* Based on hw strategy, use out_vtag in two layer tag case, 988 * and use inner_vtag in one tag case. 989 */ 990 if (skb->protocol == htons(ETH_P_8021Q) && 991 handle->port_base_vlan_state == 992 HNAE3_PORT_BASE_VLAN_DISABLE) 993 rc = HNS3_OUTER_VLAN_TAG; 994 else 995 rc = HNS3_INNER_VLAN_TAG; 996 997 skb->protocol = vlan_get_protocol(skb); 998 return rc; 999 } 1000 1001 rc = skb_cow_head(skb, 0); 1002 if (unlikely(rc < 0)) 1003 return rc; 1004 1005 vhdr = (struct vlan_ethhdr *)skb->data; 1006 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1007 & VLAN_PRIO_MASK); 1008 1009 skb->protocol = vlan_get_protocol(skb); 1010 return 0; 1011 } 1012 1013 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1014 struct sk_buff *skb, struct hns3_desc *desc) 1015 { 1016 u32 ol_type_vlan_len_msec = 0; 1017 u32 type_cs_vlan_tso = 0; 1018 u32 paylen = skb->len; 1019 u16 inner_vtag = 0; 1020 u16 out_vtag = 0; 1021 u16 mss = 0; 1022 int ret; 1023 1024 ret = hns3_handle_vtags(ring, skb); 1025 if (unlikely(ret < 0)) { 1026 u64_stats_update_begin(&ring->syncp); 1027 ring->stats.tx_vlan_err++; 1028 u64_stats_update_end(&ring->syncp); 1029 return ret; 1030 } else if (ret == HNS3_INNER_VLAN_TAG) { 1031 inner_vtag = skb_vlan_tag_get(skb); 1032 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1033 VLAN_PRIO_MASK; 1034 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1035 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1036 out_vtag = skb_vlan_tag_get(skb); 1037 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1038 VLAN_PRIO_MASK; 1039 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1040 1); 1041 } 1042 1043 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1044 u8 ol4_proto, il4_proto; 1045 1046 skb_reset_mac_len(skb); 1047 1048 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1049 if (unlikely(ret < 0)) { 1050 u64_stats_update_begin(&ring->syncp); 1051 ring->stats.tx_l4_proto_err++; 1052 u64_stats_update_end(&ring->syncp); 1053 return ret; 1054 } 1055 1056 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1057 &type_cs_vlan_tso, 1058 &ol_type_vlan_len_msec); 1059 if (unlikely(ret < 0)) { 1060 u64_stats_update_begin(&ring->syncp); 1061 ring->stats.tx_l2l3l4_err++; 1062 u64_stats_update_end(&ring->syncp); 1063 return ret; 1064 } 1065 1066 ret = hns3_set_tso(skb, &paylen, &mss, 1067 &type_cs_vlan_tso); 1068 if (unlikely(ret < 0)) { 1069 u64_stats_update_begin(&ring->syncp); 1070 ring->stats.tx_tso_err++; 1071 u64_stats_update_end(&ring->syncp); 1072 return ret; 1073 } 1074 } 1075 1076 /* Set txbd */ 1077 desc->tx.ol_type_vlan_len_msec = 1078 cpu_to_le32(ol_type_vlan_len_msec); 1079 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1080 desc->tx.paylen = cpu_to_le32(paylen); 1081 desc->tx.mss = cpu_to_le16(mss); 1082 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1083 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1084 1085 return 0; 1086 } 1087 1088 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1089 unsigned int size, enum hns_desc_type type) 1090 { 1091 #define HNS3_LIKELY_BD_NUM 1 1092 1093 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1094 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1095 struct device *dev = ring_to_dev(ring); 1096 skb_frag_t *frag; 1097 unsigned int frag_buf_num; 1098 int k, sizeoflast; 1099 dma_addr_t dma; 1100 1101 if (type == DESC_TYPE_SKB) { 1102 struct sk_buff *skb = (struct sk_buff *)priv; 1103 int ret; 1104 1105 ret = hns3_fill_skb_desc(ring, skb, desc); 1106 if (unlikely(ret < 0)) 1107 return ret; 1108 1109 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1110 } else if (type == DESC_TYPE_FRAGLIST_SKB) { 1111 struct sk_buff *skb = (struct sk_buff *)priv; 1112 1113 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1114 } else { 1115 frag = (skb_frag_t *)priv; 1116 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1117 } 1118 1119 if (unlikely(dma_mapping_error(dev, dma))) { 1120 u64_stats_update_begin(&ring->syncp); 1121 ring->stats.sw_err_cnt++; 1122 u64_stats_update_end(&ring->syncp); 1123 return -ENOMEM; 1124 } 1125 1126 desc_cb->length = size; 1127 1128 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1129 desc_cb->priv = priv; 1130 desc_cb->dma = dma; 1131 desc_cb->type = type; 1132 desc->addr = cpu_to_le64(dma); 1133 desc->tx.send_size = cpu_to_le16(size); 1134 desc->tx.bdtp_fe_sc_vld_ra_ri = 1135 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1136 1137 trace_hns3_tx_desc(ring, ring->next_to_use); 1138 ring_ptr_move_fw(ring, next_to_use); 1139 return HNS3_LIKELY_BD_NUM; 1140 } 1141 1142 frag_buf_num = hns3_tx_bd_count(size); 1143 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1144 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1145 1146 /* When frag size is bigger than hardware limit, split this frag */ 1147 for (k = 0; k < frag_buf_num; k++) { 1148 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1149 desc_cb->priv = priv; 1150 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1151 desc_cb->type = ((type == DESC_TYPE_FRAGLIST_SKB || 1152 type == DESC_TYPE_SKB) && !k) ? 1153 type : DESC_TYPE_PAGE; 1154 1155 /* now, fill the descriptor */ 1156 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1157 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1158 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1159 desc->tx.bdtp_fe_sc_vld_ra_ri = 1160 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1161 1162 trace_hns3_tx_desc(ring, ring->next_to_use); 1163 /* move ring pointer to next */ 1164 ring_ptr_move_fw(ring, next_to_use); 1165 1166 desc_cb = &ring->desc_cb[ring->next_to_use]; 1167 desc = &ring->desc[ring->next_to_use]; 1168 } 1169 1170 return frag_buf_num; 1171 } 1172 1173 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1174 unsigned int bd_num) 1175 { 1176 unsigned int size; 1177 int i; 1178 1179 size = skb_headlen(skb); 1180 while (size > HNS3_MAX_BD_SIZE) { 1181 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1182 size -= HNS3_MAX_BD_SIZE; 1183 1184 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1185 return bd_num; 1186 } 1187 1188 if (size) { 1189 bd_size[bd_num++] = size; 1190 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1191 return bd_num; 1192 } 1193 1194 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1195 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1196 size = skb_frag_size(frag); 1197 if (!size) 1198 continue; 1199 1200 while (size > HNS3_MAX_BD_SIZE) { 1201 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1202 size -= HNS3_MAX_BD_SIZE; 1203 1204 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1205 return bd_num; 1206 } 1207 1208 bd_size[bd_num++] = size; 1209 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1210 return bd_num; 1211 } 1212 1213 return bd_num; 1214 } 1215 1216 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size) 1217 { 1218 struct sk_buff *frag_skb; 1219 unsigned int bd_num = 0; 1220 1221 /* If the total len is within the max bd limit */ 1222 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) && 1223 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM)) 1224 return skb_shinfo(skb)->nr_frags + 1U; 1225 1226 /* The below case will always be linearized, return 1227 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized. 1228 */ 1229 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE || 1230 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE))) 1231 return HNS3_MAX_TSO_BD_NUM + 1U; 1232 1233 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1234 1235 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1236 return bd_num; 1237 1238 skb_walk_frags(skb, frag_skb) { 1239 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num); 1240 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1241 return bd_num; 1242 } 1243 1244 return bd_num; 1245 } 1246 1247 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1248 { 1249 if (!skb->encapsulation) 1250 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1251 1252 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1253 } 1254 1255 /* HW need every continuous 8 buffer data to be larger than MSS, 1256 * we simplify it by ensuring skb_headlen + the first continuous 1257 * 7 frags to to be larger than gso header len + mss, and the remaining 1258 * continuous 7 frags to be larger than MSS except the last 7 frags. 1259 */ 1260 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1261 unsigned int bd_num) 1262 { 1263 unsigned int tot_len = 0; 1264 int i; 1265 1266 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++) 1267 tot_len += bd_size[i]; 1268 1269 /* ensure the first 8 frags is greater than mss + header */ 1270 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] < 1271 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1272 return true; 1273 1274 /* ensure every continuous 7 buffer is greater than mss 1275 * except the last one. 1276 */ 1277 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) { 1278 tot_len -= bd_size[i]; 1279 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U]; 1280 1281 if (tot_len < skb_shinfo(skb)->gso_size) 1282 return true; 1283 } 1284 1285 return false; 1286 } 1287 1288 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1289 { 1290 int i = 0; 1291 1292 for (i = 0; i < MAX_SKB_FRAGS; i++) 1293 size[i] = skb_frag_size(&shinfo->frags[i]); 1294 } 1295 1296 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1297 struct net_device *netdev, 1298 struct sk_buff *skb) 1299 { 1300 struct hns3_nic_priv *priv = netdev_priv(netdev); 1301 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1302 unsigned int bd_num; 1303 1304 bd_num = hns3_tx_bd_num(skb, bd_size); 1305 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) { 1306 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1307 !hns3_skb_need_linearized(skb, bd_size, bd_num)) { 1308 trace_hns3_over_8bd(skb); 1309 goto out; 1310 } 1311 1312 if (__skb_linearize(skb)) 1313 return -ENOMEM; 1314 1315 bd_num = hns3_tx_bd_count(skb->len); 1316 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) || 1317 (!skb_is_gso(skb) && 1318 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) { 1319 trace_hns3_over_8bd(skb); 1320 return -ENOMEM; 1321 } 1322 1323 u64_stats_update_begin(&ring->syncp); 1324 ring->stats.tx_copy++; 1325 u64_stats_update_end(&ring->syncp); 1326 } 1327 1328 out: 1329 if (likely(ring_space(ring) >= bd_num)) 1330 return bd_num; 1331 1332 netif_stop_subqueue(netdev, ring->queue_index); 1333 smp_mb(); /* Memory barrier before checking ring_space */ 1334 1335 /* Start queue in case hns3_clean_tx_ring has just made room 1336 * available and has not seen the queue stopped state performed 1337 * by netif_stop_subqueue above. 1338 */ 1339 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1340 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1341 netif_start_subqueue(netdev, ring->queue_index); 1342 return bd_num; 1343 } 1344 1345 return -EBUSY; 1346 } 1347 1348 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1349 { 1350 struct device *dev = ring_to_dev(ring); 1351 unsigned int i; 1352 1353 for (i = 0; i < ring->desc_num; i++) { 1354 /* check if this is where we started */ 1355 if (ring->next_to_use == next_to_use_orig) 1356 break; 1357 1358 /* rollback one */ 1359 ring_ptr_move_bw(ring, next_to_use); 1360 1361 /* unmap the descriptor dma address */ 1362 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1363 ring->desc_cb[ring->next_to_use].type == 1364 DESC_TYPE_FRAGLIST_SKB) 1365 dma_unmap_single(dev, 1366 ring->desc_cb[ring->next_to_use].dma, 1367 ring->desc_cb[ring->next_to_use].length, 1368 DMA_TO_DEVICE); 1369 else if (ring->desc_cb[ring->next_to_use].length) 1370 dma_unmap_page(dev, 1371 ring->desc_cb[ring->next_to_use].dma, 1372 ring->desc_cb[ring->next_to_use].length, 1373 DMA_TO_DEVICE); 1374 1375 ring->desc_cb[ring->next_to_use].length = 0; 1376 ring->desc_cb[ring->next_to_use].dma = 0; 1377 } 1378 } 1379 1380 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1381 struct sk_buff *skb, enum hns_desc_type type) 1382 { 1383 unsigned int size = skb_headlen(skb); 1384 int i, ret, bd_num = 0; 1385 1386 if (size) { 1387 ret = hns3_fill_desc(ring, skb, size, type); 1388 if (unlikely(ret < 0)) 1389 return ret; 1390 1391 bd_num += ret; 1392 } 1393 1394 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1395 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1396 1397 size = skb_frag_size(frag); 1398 if (!size) 1399 continue; 1400 1401 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1402 if (unlikely(ret < 0)) 1403 return ret; 1404 1405 bd_num += ret; 1406 } 1407 1408 return bd_num; 1409 } 1410 1411 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1412 { 1413 struct hns3_nic_priv *priv = netdev_priv(netdev); 1414 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1415 struct netdev_queue *dev_queue; 1416 int pre_ntu, next_to_use_head; 1417 struct sk_buff *frag_skb; 1418 int bd_num = 0; 1419 int ret; 1420 1421 /* Hardware can only handle short frames above 32 bytes */ 1422 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) 1423 return NETDEV_TX_OK; 1424 1425 /* Prefetch the data used later */ 1426 prefetch(skb->data); 1427 1428 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1429 if (unlikely(ret <= 0)) { 1430 if (ret == -EBUSY) { 1431 u64_stats_update_begin(&ring->syncp); 1432 ring->stats.tx_busy++; 1433 u64_stats_update_end(&ring->syncp); 1434 return NETDEV_TX_BUSY; 1435 } else if (ret == -ENOMEM) { 1436 u64_stats_update_begin(&ring->syncp); 1437 ring->stats.sw_err_cnt++; 1438 u64_stats_update_end(&ring->syncp); 1439 } 1440 1441 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1442 goto out_err_tx_ok; 1443 } 1444 1445 next_to_use_head = ring->next_to_use; 1446 1447 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1448 if (unlikely(ret < 0)) 1449 goto fill_err; 1450 1451 bd_num += ret; 1452 1453 if (!skb_has_frag_list(skb)) 1454 goto out; 1455 1456 skb_walk_frags(skb, frag_skb) { 1457 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1458 DESC_TYPE_FRAGLIST_SKB); 1459 if (unlikely(ret < 0)) 1460 goto fill_err; 1461 1462 bd_num += ret; 1463 } 1464 out: 1465 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1466 (ring->desc_num - 1); 1467 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1468 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1469 trace_hns3_tx_desc(ring, pre_ntu); 1470 1471 /* Complete translate all packets */ 1472 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1473 netdev_tx_sent_queue(dev_queue, skb->len); 1474 1475 wmb(); /* Commit all data before submit */ 1476 1477 hnae3_queue_xmit(ring->tqp, bd_num); 1478 1479 return NETDEV_TX_OK; 1480 1481 fill_err: 1482 hns3_clear_desc(ring, next_to_use_head); 1483 1484 out_err_tx_ok: 1485 dev_kfree_skb_any(skb); 1486 return NETDEV_TX_OK; 1487 } 1488 1489 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1490 { 1491 struct hnae3_handle *h = hns3_get_handle(netdev); 1492 struct sockaddr *mac_addr = p; 1493 int ret; 1494 1495 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1496 return -EADDRNOTAVAIL; 1497 1498 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1499 netdev_info(netdev, "already using mac address %pM\n", 1500 mac_addr->sa_data); 1501 return 0; 1502 } 1503 1504 /* For VF device, if there is a perm_addr, then the user will not 1505 * be allowed to change the address. 1506 */ 1507 if (!hns3_is_phys_func(h->pdev) && 1508 !is_zero_ether_addr(netdev->perm_addr)) { 1509 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1510 netdev->perm_addr, mac_addr->sa_data); 1511 return -EPERM; 1512 } 1513 1514 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1515 if (ret) { 1516 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1517 return ret; 1518 } 1519 1520 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1521 1522 return 0; 1523 } 1524 1525 static int hns3_nic_do_ioctl(struct net_device *netdev, 1526 struct ifreq *ifr, int cmd) 1527 { 1528 struct hnae3_handle *h = hns3_get_handle(netdev); 1529 1530 if (!netif_running(netdev)) 1531 return -EINVAL; 1532 1533 if (!h->ae_algo->ops->do_ioctl) 1534 return -EOPNOTSUPP; 1535 1536 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1537 } 1538 1539 static int hns3_nic_set_features(struct net_device *netdev, 1540 netdev_features_t features) 1541 { 1542 netdev_features_t changed = netdev->features ^ features; 1543 struct hns3_nic_priv *priv = netdev_priv(netdev); 1544 struct hnae3_handle *h = priv->ae_handle; 1545 bool enable; 1546 int ret; 1547 1548 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1549 enable = !!(features & NETIF_F_GRO_HW); 1550 ret = h->ae_algo->ops->set_gro_en(h, enable); 1551 if (ret) 1552 return ret; 1553 } 1554 1555 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1556 h->ae_algo->ops->enable_vlan_filter) { 1557 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1558 h->ae_algo->ops->enable_vlan_filter(h, enable); 1559 } 1560 1561 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1562 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1563 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1564 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1565 if (ret) 1566 return ret; 1567 } 1568 1569 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1570 enable = !!(features & NETIF_F_NTUPLE); 1571 h->ae_algo->ops->enable_fd(h, enable); 1572 } 1573 1574 netdev->features = features; 1575 return 0; 1576 } 1577 1578 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1579 struct net_device *dev, 1580 netdev_features_t features) 1581 { 1582 #define HNS3_MAX_HDR_LEN 480U 1583 #define HNS3_MAX_L4_HDR_LEN 60U 1584 1585 size_t len; 1586 1587 if (skb->ip_summed != CHECKSUM_PARTIAL) 1588 return features; 1589 1590 if (skb->encapsulation) 1591 len = skb_inner_transport_header(skb) - skb->data; 1592 else 1593 len = skb_transport_header(skb) - skb->data; 1594 1595 /* Assume L4 is 60 byte as TCP is the only protocol with a 1596 * a flexible value, and it's max len is 60 bytes. 1597 */ 1598 len += HNS3_MAX_L4_HDR_LEN; 1599 1600 /* Hardware only supports checksum on the skb with a max header 1601 * len of 480 bytes. 1602 */ 1603 if (len > HNS3_MAX_HDR_LEN) 1604 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 1605 1606 return features; 1607 } 1608 1609 static void hns3_nic_get_stats64(struct net_device *netdev, 1610 struct rtnl_link_stats64 *stats) 1611 { 1612 struct hns3_nic_priv *priv = netdev_priv(netdev); 1613 int queue_num = priv->ae_handle->kinfo.num_tqps; 1614 struct hnae3_handle *handle = priv->ae_handle; 1615 struct hns3_enet_ring *ring; 1616 u64 rx_length_errors = 0; 1617 u64 rx_crc_errors = 0; 1618 u64 rx_multicast = 0; 1619 unsigned int start; 1620 u64 tx_errors = 0; 1621 u64 rx_errors = 0; 1622 unsigned int idx; 1623 u64 tx_bytes = 0; 1624 u64 rx_bytes = 0; 1625 u64 tx_pkts = 0; 1626 u64 rx_pkts = 0; 1627 u64 tx_drop = 0; 1628 u64 rx_drop = 0; 1629 1630 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1631 return; 1632 1633 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1634 1635 for (idx = 0; idx < queue_num; idx++) { 1636 /* fetch the tx stats */ 1637 ring = &priv->ring[idx]; 1638 do { 1639 start = u64_stats_fetch_begin_irq(&ring->syncp); 1640 tx_bytes += ring->stats.tx_bytes; 1641 tx_pkts += ring->stats.tx_pkts; 1642 tx_drop += ring->stats.sw_err_cnt; 1643 tx_drop += ring->stats.tx_vlan_err; 1644 tx_drop += ring->stats.tx_l4_proto_err; 1645 tx_drop += ring->stats.tx_l2l3l4_err; 1646 tx_drop += ring->stats.tx_tso_err; 1647 tx_errors += ring->stats.sw_err_cnt; 1648 tx_errors += ring->stats.tx_vlan_err; 1649 tx_errors += ring->stats.tx_l4_proto_err; 1650 tx_errors += ring->stats.tx_l2l3l4_err; 1651 tx_errors += ring->stats.tx_tso_err; 1652 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1653 1654 /* fetch the rx stats */ 1655 ring = &priv->ring[idx + queue_num]; 1656 do { 1657 start = u64_stats_fetch_begin_irq(&ring->syncp); 1658 rx_bytes += ring->stats.rx_bytes; 1659 rx_pkts += ring->stats.rx_pkts; 1660 rx_drop += ring->stats.l2_err; 1661 rx_errors += ring->stats.l2_err; 1662 rx_errors += ring->stats.l3l4_csum_err; 1663 rx_crc_errors += ring->stats.l2_err; 1664 rx_multicast += ring->stats.rx_multicast; 1665 rx_length_errors += ring->stats.err_pkt_len; 1666 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1667 } 1668 1669 stats->tx_bytes = tx_bytes; 1670 stats->tx_packets = tx_pkts; 1671 stats->rx_bytes = rx_bytes; 1672 stats->rx_packets = rx_pkts; 1673 1674 stats->rx_errors = rx_errors; 1675 stats->multicast = rx_multicast; 1676 stats->rx_length_errors = rx_length_errors; 1677 stats->rx_crc_errors = rx_crc_errors; 1678 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1679 1680 stats->tx_errors = tx_errors; 1681 stats->rx_dropped = rx_drop; 1682 stats->tx_dropped = tx_drop; 1683 stats->collisions = netdev->stats.collisions; 1684 stats->rx_over_errors = netdev->stats.rx_over_errors; 1685 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1686 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1687 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1688 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1689 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1690 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1691 stats->tx_window_errors = netdev->stats.tx_window_errors; 1692 stats->rx_compressed = netdev->stats.rx_compressed; 1693 stats->tx_compressed = netdev->stats.tx_compressed; 1694 } 1695 1696 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1697 { 1698 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1699 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1700 struct hnae3_knic_private_info *kinfo; 1701 u8 tc = mqprio_qopt->qopt.num_tc; 1702 u16 mode = mqprio_qopt->mode; 1703 u8 hw = mqprio_qopt->qopt.hw; 1704 struct hnae3_handle *h; 1705 1706 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1707 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1708 return -EOPNOTSUPP; 1709 1710 if (tc > HNAE3_MAX_TC) 1711 return -EINVAL; 1712 1713 if (!netdev) 1714 return -EINVAL; 1715 1716 h = hns3_get_handle(netdev); 1717 kinfo = &h->kinfo; 1718 1719 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1720 1721 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1722 kinfo->dcb_ops->setup_tc(h, tc ? tc : 1, prio_tc) : -EOPNOTSUPP; 1723 } 1724 1725 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1726 void *type_data) 1727 { 1728 if (type != TC_SETUP_QDISC_MQPRIO) 1729 return -EOPNOTSUPP; 1730 1731 return hns3_setup_tc(dev, type_data); 1732 } 1733 1734 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1735 __be16 proto, u16 vid) 1736 { 1737 struct hnae3_handle *h = hns3_get_handle(netdev); 1738 int ret = -EIO; 1739 1740 if (h->ae_algo->ops->set_vlan_filter) 1741 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1742 1743 return ret; 1744 } 1745 1746 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1747 __be16 proto, u16 vid) 1748 { 1749 struct hnae3_handle *h = hns3_get_handle(netdev); 1750 int ret = -EIO; 1751 1752 if (h->ae_algo->ops->set_vlan_filter) 1753 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1754 1755 return ret; 1756 } 1757 1758 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1759 u8 qos, __be16 vlan_proto) 1760 { 1761 struct hnae3_handle *h = hns3_get_handle(netdev); 1762 int ret = -EIO; 1763 1764 netif_dbg(h, drv, netdev, 1765 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1766 vf, vlan, qos, ntohs(vlan_proto)); 1767 1768 if (h->ae_algo->ops->set_vf_vlan_filter) 1769 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1770 qos, vlan_proto); 1771 1772 return ret; 1773 } 1774 1775 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1776 { 1777 struct hnae3_handle *handle = hns3_get_handle(netdev); 1778 1779 if (hns3_nic_resetting(netdev)) 1780 return -EBUSY; 1781 1782 if (!handle->ae_algo->ops->set_vf_spoofchk) 1783 return -EOPNOTSUPP; 1784 1785 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1786 } 1787 1788 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1789 { 1790 struct hnae3_handle *handle = hns3_get_handle(netdev); 1791 1792 if (!handle->ae_algo->ops->set_vf_trust) 1793 return -EOPNOTSUPP; 1794 1795 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1796 } 1797 1798 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1799 { 1800 struct hnae3_handle *h = hns3_get_handle(netdev); 1801 int ret; 1802 1803 if (hns3_nic_resetting(netdev)) 1804 return -EBUSY; 1805 1806 if (!h->ae_algo->ops->set_mtu) 1807 return -EOPNOTSUPP; 1808 1809 netif_dbg(h, drv, netdev, 1810 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1811 1812 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1813 if (ret) 1814 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1815 ret); 1816 else 1817 netdev->mtu = new_mtu; 1818 1819 return ret; 1820 } 1821 1822 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1823 { 1824 struct hns3_nic_priv *priv = netdev_priv(ndev); 1825 struct hnae3_handle *h = hns3_get_handle(ndev); 1826 struct hns3_enet_ring *tx_ring; 1827 struct napi_struct *napi; 1828 int timeout_queue = 0; 1829 int hw_head, hw_tail; 1830 int fbd_num, fbd_oft; 1831 int ebd_num, ebd_oft; 1832 int bd_num, bd_err; 1833 int ring_en, tc; 1834 int i; 1835 1836 /* Find the stopped queue the same way the stack does */ 1837 for (i = 0; i < ndev->num_tx_queues; i++) { 1838 struct netdev_queue *q; 1839 unsigned long trans_start; 1840 1841 q = netdev_get_tx_queue(ndev, i); 1842 trans_start = q->trans_start; 1843 if (netif_xmit_stopped(q) && 1844 time_after(jiffies, 1845 (trans_start + ndev->watchdog_timeo))) { 1846 timeout_queue = i; 1847 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 1848 q->state, 1849 jiffies_to_msecs(jiffies - trans_start)); 1850 break; 1851 } 1852 } 1853 1854 if (i == ndev->num_tx_queues) { 1855 netdev_info(ndev, 1856 "no netdev TX timeout queue found, timeout count: %llu\n", 1857 priv->tx_timeout_count); 1858 return false; 1859 } 1860 1861 priv->tx_timeout_count++; 1862 1863 tx_ring = &priv->ring[timeout_queue]; 1864 napi = &tx_ring->tqp_vector->napi; 1865 1866 netdev_info(ndev, 1867 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1868 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1869 tx_ring->next_to_clean, napi->state); 1870 1871 netdev_info(ndev, 1872 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n", 1873 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1874 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt); 1875 1876 netdev_info(ndev, 1877 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n", 1878 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt, 1879 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1880 1881 /* When mac received many pause frames continuous, it's unable to send 1882 * packets, which may cause tx timeout 1883 */ 1884 if (h->ae_algo->ops->get_mac_stats) { 1885 struct hns3_mac_stats mac_stats; 1886 1887 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1888 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1889 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1890 } 1891 1892 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1893 HNS3_RING_TX_RING_HEAD_REG); 1894 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1895 HNS3_RING_TX_RING_TAIL_REG); 1896 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1897 HNS3_RING_TX_RING_FBDNUM_REG); 1898 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1899 HNS3_RING_TX_RING_OFFSET_REG); 1900 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1901 HNS3_RING_TX_RING_EBDNUM_REG); 1902 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1903 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1904 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1905 HNS3_RING_TX_RING_BD_NUM_REG); 1906 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1907 HNS3_RING_TX_RING_BD_ERR_REG); 1908 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1909 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1910 1911 netdev_info(ndev, 1912 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1913 bd_num, hw_head, hw_tail, bd_err, 1914 readl(tx_ring->tqp_vector->mask_addr)); 1915 netdev_info(ndev, 1916 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1917 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1918 1919 return true; 1920 } 1921 1922 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 1923 { 1924 struct hns3_nic_priv *priv = netdev_priv(ndev); 1925 struct hnae3_handle *h = priv->ae_handle; 1926 1927 if (!hns3_get_tx_timeo_queue_info(ndev)) 1928 return; 1929 1930 /* request the reset, and let the hclge to determine 1931 * which reset level should be done 1932 */ 1933 if (h->ae_algo->ops->reset_event) 1934 h->ae_algo->ops->reset_event(h->pdev, h); 1935 } 1936 1937 #ifdef CONFIG_RFS_ACCEL 1938 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1939 u16 rxq_index, u32 flow_id) 1940 { 1941 struct hnae3_handle *h = hns3_get_handle(dev); 1942 struct flow_keys fkeys; 1943 1944 if (!h->ae_algo->ops->add_arfs_entry) 1945 return -EOPNOTSUPP; 1946 1947 if (skb->encapsulation) 1948 return -EPROTONOSUPPORT; 1949 1950 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 1951 return -EPROTONOSUPPORT; 1952 1953 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 1954 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 1955 (fkeys.basic.ip_proto != IPPROTO_TCP && 1956 fkeys.basic.ip_proto != IPPROTO_UDP)) 1957 return -EPROTONOSUPPORT; 1958 1959 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 1960 } 1961 #endif 1962 1963 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 1964 struct ifla_vf_info *ivf) 1965 { 1966 struct hnae3_handle *h = hns3_get_handle(ndev); 1967 1968 if (!h->ae_algo->ops->get_vf_config) 1969 return -EOPNOTSUPP; 1970 1971 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 1972 } 1973 1974 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 1975 int link_state) 1976 { 1977 struct hnae3_handle *h = hns3_get_handle(ndev); 1978 1979 if (!h->ae_algo->ops->set_vf_link_state) 1980 return -EOPNOTSUPP; 1981 1982 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 1983 } 1984 1985 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 1986 int min_tx_rate, int max_tx_rate) 1987 { 1988 struct hnae3_handle *h = hns3_get_handle(ndev); 1989 1990 if (!h->ae_algo->ops->set_vf_rate) 1991 return -EOPNOTSUPP; 1992 1993 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 1994 false); 1995 } 1996 1997 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 1998 { 1999 struct hnae3_handle *h = hns3_get_handle(netdev); 2000 2001 if (!h->ae_algo->ops->set_vf_mac) 2002 return -EOPNOTSUPP; 2003 2004 if (is_multicast_ether_addr(mac)) { 2005 netdev_err(netdev, 2006 "Invalid MAC:%pM specified. Could not set MAC\n", 2007 mac); 2008 return -EINVAL; 2009 } 2010 2011 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2012 } 2013 2014 static const struct net_device_ops hns3_nic_netdev_ops = { 2015 .ndo_open = hns3_nic_net_open, 2016 .ndo_stop = hns3_nic_net_stop, 2017 .ndo_start_xmit = hns3_nic_net_xmit, 2018 .ndo_tx_timeout = hns3_nic_net_timeout, 2019 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2020 .ndo_do_ioctl = hns3_nic_do_ioctl, 2021 .ndo_change_mtu = hns3_nic_change_mtu, 2022 .ndo_set_features = hns3_nic_set_features, 2023 .ndo_features_check = hns3_features_check, 2024 .ndo_get_stats64 = hns3_nic_get_stats64, 2025 .ndo_setup_tc = hns3_nic_setup_tc, 2026 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2027 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2028 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2029 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2030 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2031 .ndo_set_vf_trust = hns3_set_vf_trust, 2032 #ifdef CONFIG_RFS_ACCEL 2033 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2034 #endif 2035 .ndo_get_vf_config = hns3_nic_get_vf_config, 2036 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2037 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2038 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2039 }; 2040 2041 bool hns3_is_phys_func(struct pci_dev *pdev) 2042 { 2043 u32 dev_id = pdev->device; 2044 2045 switch (dev_id) { 2046 case HNAE3_DEV_ID_GE: 2047 case HNAE3_DEV_ID_25GE: 2048 case HNAE3_DEV_ID_25GE_RDMA: 2049 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2050 case HNAE3_DEV_ID_50GE_RDMA: 2051 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2052 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2053 return true; 2054 case HNAE3_DEV_ID_100G_VF: 2055 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 2056 return false; 2057 default: 2058 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2059 dev_id); 2060 } 2061 2062 return false; 2063 } 2064 2065 static void hns3_disable_sriov(struct pci_dev *pdev) 2066 { 2067 /* If our VFs are assigned we cannot shut down SR-IOV 2068 * without causing issues, so just leave the hardware 2069 * available but disabled 2070 */ 2071 if (pci_vfs_assigned(pdev)) { 2072 dev_warn(&pdev->dev, 2073 "disabling driver while VFs are assigned\n"); 2074 return; 2075 } 2076 2077 pci_disable_sriov(pdev); 2078 } 2079 2080 static void hns3_get_dev_capability(struct pci_dev *pdev, 2081 struct hnae3_ae_dev *ae_dev) 2082 { 2083 if (pdev->revision >= 0x21) { 2084 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 2085 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 2086 } 2087 } 2088 2089 /* hns3_probe - Device initialization routine 2090 * @pdev: PCI device information struct 2091 * @ent: entry in hns3_pci_tbl 2092 * 2093 * hns3_probe initializes a PF identified by a pci_dev structure. 2094 * The OS initialization, configuring of the PF private structure, 2095 * and a hardware reset occur. 2096 * 2097 * Returns 0 on success, negative on failure 2098 */ 2099 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2100 { 2101 struct hnae3_ae_dev *ae_dev; 2102 int ret; 2103 2104 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2105 if (!ae_dev) 2106 return -ENOMEM; 2107 2108 ae_dev->pdev = pdev; 2109 ae_dev->flag = ent->driver_data; 2110 ae_dev->reset_type = HNAE3_NONE_RESET; 2111 hns3_get_dev_capability(pdev, ae_dev); 2112 pci_set_drvdata(pdev, ae_dev); 2113 2114 ret = hnae3_register_ae_dev(ae_dev); 2115 if (ret) { 2116 devm_kfree(&pdev->dev, ae_dev); 2117 pci_set_drvdata(pdev, NULL); 2118 } 2119 2120 return ret; 2121 } 2122 2123 /* hns3_remove - Device removal routine 2124 * @pdev: PCI device information struct 2125 */ 2126 static void hns3_remove(struct pci_dev *pdev) 2127 { 2128 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2129 2130 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2131 hns3_disable_sriov(pdev); 2132 2133 hnae3_unregister_ae_dev(ae_dev); 2134 pci_set_drvdata(pdev, NULL); 2135 } 2136 2137 /** 2138 * hns3_pci_sriov_configure 2139 * @pdev: pointer to a pci_dev structure 2140 * @num_vfs: number of VFs to allocate 2141 * 2142 * Enable or change the number of VFs. Called when the user updates the number 2143 * of VFs in sysfs. 2144 **/ 2145 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2146 { 2147 int ret; 2148 2149 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2150 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2151 return -EINVAL; 2152 } 2153 2154 if (num_vfs) { 2155 ret = pci_enable_sriov(pdev, num_vfs); 2156 if (ret) 2157 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2158 else 2159 return num_vfs; 2160 } else if (!pci_vfs_assigned(pdev)) { 2161 pci_disable_sriov(pdev); 2162 } else { 2163 dev_warn(&pdev->dev, 2164 "Unable to free VFs because some are assigned to VMs.\n"); 2165 } 2166 2167 return 0; 2168 } 2169 2170 static void hns3_shutdown(struct pci_dev *pdev) 2171 { 2172 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2173 2174 hnae3_unregister_ae_dev(ae_dev); 2175 devm_kfree(&pdev->dev, ae_dev); 2176 pci_set_drvdata(pdev, NULL); 2177 2178 if (system_state == SYSTEM_POWER_OFF) 2179 pci_set_power_state(pdev, PCI_D3hot); 2180 } 2181 2182 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2183 pci_channel_state_t state) 2184 { 2185 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2186 pci_ers_result_t ret; 2187 2188 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 2189 2190 if (state == pci_channel_io_perm_failure) 2191 return PCI_ERS_RESULT_DISCONNECT; 2192 2193 if (!ae_dev || !ae_dev->ops) { 2194 dev_err(&pdev->dev, 2195 "Can't recover - error happened before device initialized\n"); 2196 return PCI_ERS_RESULT_NONE; 2197 } 2198 2199 if (ae_dev->ops->handle_hw_ras_error) 2200 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2201 else 2202 return PCI_ERS_RESULT_NONE; 2203 2204 return ret; 2205 } 2206 2207 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2208 { 2209 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2210 const struct hnae3_ae_ops *ops; 2211 enum hnae3_reset_type reset_type; 2212 struct device *dev = &pdev->dev; 2213 2214 if (!ae_dev || !ae_dev->ops) 2215 return PCI_ERS_RESULT_NONE; 2216 2217 ops = ae_dev->ops; 2218 /* request the reset */ 2219 if (ops->reset_event && ops->get_reset_level && 2220 ops->set_default_reset_request) { 2221 if (ae_dev->hw_err_reset_req) { 2222 reset_type = ops->get_reset_level(ae_dev, 2223 &ae_dev->hw_err_reset_req); 2224 ops->set_default_reset_request(ae_dev, reset_type); 2225 dev_info(dev, "requesting reset due to PCI error\n"); 2226 ops->reset_event(pdev, NULL); 2227 } 2228 2229 return PCI_ERS_RESULT_RECOVERED; 2230 } 2231 2232 return PCI_ERS_RESULT_DISCONNECT; 2233 } 2234 2235 static void hns3_reset_prepare(struct pci_dev *pdev) 2236 { 2237 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2238 2239 dev_info(&pdev->dev, "FLR prepare\n"); 2240 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2241 ae_dev->ops->flr_prepare(ae_dev); 2242 } 2243 2244 static void hns3_reset_done(struct pci_dev *pdev) 2245 { 2246 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2247 2248 dev_info(&pdev->dev, "FLR done\n"); 2249 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2250 ae_dev->ops->flr_done(ae_dev); 2251 } 2252 2253 static const struct pci_error_handlers hns3_err_handler = { 2254 .error_detected = hns3_error_detected, 2255 .slot_reset = hns3_slot_reset, 2256 .reset_prepare = hns3_reset_prepare, 2257 .reset_done = hns3_reset_done, 2258 }; 2259 2260 static struct pci_driver hns3_driver = { 2261 .name = hns3_driver_name, 2262 .id_table = hns3_pci_tbl, 2263 .probe = hns3_probe, 2264 .remove = hns3_remove, 2265 .shutdown = hns3_shutdown, 2266 .sriov_configure = hns3_pci_sriov_configure, 2267 .err_handler = &hns3_err_handler, 2268 }; 2269 2270 /* set default feature to hns3 */ 2271 static void hns3_set_default_feature(struct net_device *netdev) 2272 { 2273 struct hnae3_handle *h = hns3_get_handle(netdev); 2274 struct pci_dev *pdev = h->pdev; 2275 2276 netdev->priv_flags |= IFF_UNICAST_FLT; 2277 2278 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2279 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2280 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2281 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2282 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2283 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2284 2285 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2286 2287 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2288 NETIF_F_HW_VLAN_CTAG_FILTER | 2289 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2290 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2291 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2292 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2293 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2294 NETIF_F_FRAGLIST; 2295 2296 netdev->vlan_features |= 2297 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2298 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2299 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2300 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2301 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2302 NETIF_F_FRAGLIST; 2303 2304 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2305 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2306 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2307 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2308 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2309 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2310 NETIF_F_FRAGLIST; 2311 2312 if (pdev->revision >= 0x21) { 2313 netdev->hw_features |= NETIF_F_GRO_HW; 2314 netdev->features |= NETIF_F_GRO_HW; 2315 2316 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2317 netdev->hw_features |= NETIF_F_NTUPLE; 2318 netdev->features |= NETIF_F_NTUPLE; 2319 } 2320 } 2321 } 2322 2323 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2324 struct hns3_desc_cb *cb) 2325 { 2326 unsigned int order = hns3_page_order(ring); 2327 struct page *p; 2328 2329 p = dev_alloc_pages(order); 2330 if (!p) 2331 return -ENOMEM; 2332 2333 cb->priv = p; 2334 cb->page_offset = 0; 2335 cb->reuse_flag = 0; 2336 cb->buf = page_address(p); 2337 cb->length = hns3_page_size(ring); 2338 cb->type = DESC_TYPE_PAGE; 2339 2340 return 0; 2341 } 2342 2343 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2344 struct hns3_desc_cb *cb) 2345 { 2346 if (cb->type == DESC_TYPE_SKB) 2347 dev_kfree_skb_any((struct sk_buff *)cb->priv); 2348 else if (!HNAE3_IS_TX_RING(ring)) 2349 put_page((struct page *)cb->priv); 2350 memset(cb, 0, sizeof(*cb)); 2351 } 2352 2353 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2354 { 2355 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2356 cb->length, ring_to_dma_dir(ring)); 2357 2358 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2359 return -EIO; 2360 2361 return 0; 2362 } 2363 2364 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2365 struct hns3_desc_cb *cb) 2366 { 2367 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2368 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2369 ring_to_dma_dir(ring)); 2370 else if (cb->length) 2371 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2372 ring_to_dma_dir(ring)); 2373 } 2374 2375 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2376 { 2377 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2378 ring->desc[i].addr = 0; 2379 } 2380 2381 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2382 { 2383 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2384 2385 if (!ring->desc_cb[i].dma) 2386 return; 2387 2388 hns3_buffer_detach(ring, i); 2389 hns3_free_buffer(ring, cb); 2390 } 2391 2392 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2393 { 2394 int i; 2395 2396 for (i = 0; i < ring->desc_num; i++) 2397 hns3_free_buffer_detach(ring, i); 2398 } 2399 2400 /* free desc along with its attached buffer */ 2401 static void hns3_free_desc(struct hns3_enet_ring *ring) 2402 { 2403 int size = ring->desc_num * sizeof(ring->desc[0]); 2404 2405 hns3_free_buffers(ring); 2406 2407 if (ring->desc) { 2408 dma_free_coherent(ring_to_dev(ring), size, 2409 ring->desc, ring->desc_dma_addr); 2410 ring->desc = NULL; 2411 } 2412 } 2413 2414 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2415 { 2416 int size = ring->desc_num * sizeof(ring->desc[0]); 2417 2418 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2419 &ring->desc_dma_addr, GFP_KERNEL); 2420 if (!ring->desc) 2421 return -ENOMEM; 2422 2423 return 0; 2424 } 2425 2426 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2427 struct hns3_desc_cb *cb) 2428 { 2429 int ret; 2430 2431 ret = hns3_alloc_buffer(ring, cb); 2432 if (ret) 2433 goto out; 2434 2435 ret = hns3_map_buffer(ring, cb); 2436 if (ret) 2437 goto out_with_buf; 2438 2439 return 0; 2440 2441 out_with_buf: 2442 hns3_free_buffer(ring, cb); 2443 out: 2444 return ret; 2445 } 2446 2447 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2448 { 2449 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2450 2451 if (ret) 2452 return ret; 2453 2454 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2455 2456 return 0; 2457 } 2458 2459 /* Allocate memory for raw pkg, and map with dma */ 2460 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2461 { 2462 int i, j, ret; 2463 2464 for (i = 0; i < ring->desc_num; i++) { 2465 ret = hns3_alloc_buffer_attach(ring, i); 2466 if (ret) 2467 goto out_buffer_fail; 2468 } 2469 2470 return 0; 2471 2472 out_buffer_fail: 2473 for (j = i - 1; j >= 0; j--) 2474 hns3_free_buffer_detach(ring, j); 2475 return ret; 2476 } 2477 2478 /* detach a in-used buffer and replace with a reserved one */ 2479 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2480 struct hns3_desc_cb *res_cb) 2481 { 2482 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2483 ring->desc_cb[i] = *res_cb; 2484 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2485 ring->desc[i].rx.bd_base_info = 0; 2486 } 2487 2488 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2489 { 2490 ring->desc_cb[i].reuse_flag = 0; 2491 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2492 ring->desc_cb[i].page_offset); 2493 ring->desc[i].rx.bd_base_info = 0; 2494 } 2495 2496 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head, 2497 int *bytes, int *pkts) 2498 { 2499 int ntc = ring->next_to_clean; 2500 struct hns3_desc_cb *desc_cb; 2501 2502 while (head != ntc) { 2503 desc_cb = &ring->desc_cb[ntc]; 2504 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2505 (*bytes) += desc_cb->length; 2506 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2507 hns3_free_buffer_detach(ring, ntc); 2508 2509 if (++ntc == ring->desc_num) 2510 ntc = 0; 2511 2512 /* Issue prefetch for next Tx descriptor */ 2513 prefetch(&ring->desc_cb[ntc]); 2514 } 2515 2516 /* This smp_store_release() pairs with smp_load_acquire() in 2517 * ring_space called by hns3_nic_net_xmit. 2518 */ 2519 smp_store_release(&ring->next_to_clean, ntc); 2520 } 2521 2522 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2523 { 2524 int u = ring->next_to_use; 2525 int c = ring->next_to_clean; 2526 2527 if (unlikely(h > ring->desc_num)) 2528 return 0; 2529 2530 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2531 } 2532 2533 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2534 { 2535 struct net_device *netdev = ring_to_netdev(ring); 2536 struct hns3_nic_priv *priv = netdev_priv(netdev); 2537 struct netdev_queue *dev_queue; 2538 int bytes, pkts; 2539 int head; 2540 2541 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2542 2543 if (is_ring_empty(ring) || head == ring->next_to_clean) 2544 return; /* no data to poll */ 2545 2546 rmb(); /* Make sure head is ready before touch any data */ 2547 2548 if (unlikely(!is_valid_clean_head(ring, head))) { 2549 hns3_rl_err(netdev, "wrong head (%d, %d-%d)\n", head, 2550 ring->next_to_use, ring->next_to_clean); 2551 2552 u64_stats_update_begin(&ring->syncp); 2553 ring->stats.io_err_cnt++; 2554 u64_stats_update_end(&ring->syncp); 2555 return; 2556 } 2557 2558 bytes = 0; 2559 pkts = 0; 2560 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts); 2561 2562 ring->tqp_vector->tx_group.total_bytes += bytes; 2563 ring->tqp_vector->tx_group.total_packets += pkts; 2564 2565 u64_stats_update_begin(&ring->syncp); 2566 ring->stats.tx_bytes += bytes; 2567 ring->stats.tx_pkts += pkts; 2568 u64_stats_update_end(&ring->syncp); 2569 2570 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2571 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2572 2573 if (unlikely(netif_carrier_ok(netdev) && 2574 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2575 /* Make sure that anybody stopping the queue after this 2576 * sees the new next_to_clean. 2577 */ 2578 smp_mb(); 2579 if (netif_tx_queue_stopped(dev_queue) && 2580 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2581 netif_tx_wake_queue(dev_queue); 2582 ring->stats.restart_queue++; 2583 } 2584 } 2585 } 2586 2587 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2588 { 2589 int ntc = ring->next_to_clean; 2590 int ntu = ring->next_to_use; 2591 2592 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2593 } 2594 2595 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2596 int cleand_count) 2597 { 2598 struct hns3_desc_cb *desc_cb; 2599 struct hns3_desc_cb res_cbs; 2600 int i, ret; 2601 2602 for (i = 0; i < cleand_count; i++) { 2603 desc_cb = &ring->desc_cb[ring->next_to_use]; 2604 if (desc_cb->reuse_flag) { 2605 u64_stats_update_begin(&ring->syncp); 2606 ring->stats.reuse_pg_cnt++; 2607 u64_stats_update_end(&ring->syncp); 2608 2609 hns3_reuse_buffer(ring, ring->next_to_use); 2610 } else { 2611 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2612 if (ret) { 2613 u64_stats_update_begin(&ring->syncp); 2614 ring->stats.sw_err_cnt++; 2615 u64_stats_update_end(&ring->syncp); 2616 2617 hns3_rl_err(ring_to_netdev(ring), 2618 "alloc rx buffer failed: %d\n", 2619 ret); 2620 break; 2621 } 2622 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2623 2624 u64_stats_update_begin(&ring->syncp); 2625 ring->stats.non_reuse_pg++; 2626 u64_stats_update_end(&ring->syncp); 2627 } 2628 2629 ring_ptr_move_fw(ring, next_to_use); 2630 } 2631 2632 wmb(); /* Make all data has been write before submit */ 2633 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2634 } 2635 2636 static bool hns3_page_is_reusable(struct page *page) 2637 { 2638 return page_to_nid(page) == numa_mem_id() && 2639 !page_is_pfmemalloc(page); 2640 } 2641 2642 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2643 struct hns3_enet_ring *ring, int pull_len, 2644 struct hns3_desc_cb *desc_cb) 2645 { 2646 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2647 int size = le16_to_cpu(desc->rx.size); 2648 u32 truesize = hns3_buf_size(ring); 2649 2650 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2651 size - pull_len, truesize); 2652 2653 /* Avoid re-using remote pages, or the stack is still using the page 2654 * when page_offset rollback to zero, flag default unreuse 2655 */ 2656 if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) || 2657 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1)) 2658 return; 2659 2660 /* Move offset up to the next cache line */ 2661 desc_cb->page_offset += truesize; 2662 2663 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2664 desc_cb->reuse_flag = 1; 2665 /* Bump ref count on page before it is given */ 2666 get_page(desc_cb->priv); 2667 } else if (page_count(desc_cb->priv) == 1) { 2668 desc_cb->reuse_flag = 1; 2669 desc_cb->page_offset = 0; 2670 get_page(desc_cb->priv); 2671 } 2672 } 2673 2674 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2675 { 2676 __be16 type = skb->protocol; 2677 struct tcphdr *th; 2678 int depth = 0; 2679 2680 while (eth_type_vlan(type)) { 2681 struct vlan_hdr *vh; 2682 2683 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2684 return -EFAULT; 2685 2686 vh = (struct vlan_hdr *)(skb->data + depth); 2687 type = vh->h_vlan_encapsulated_proto; 2688 depth += VLAN_HLEN; 2689 } 2690 2691 skb_set_network_header(skb, depth); 2692 2693 if (type == htons(ETH_P_IP)) { 2694 const struct iphdr *iph = ip_hdr(skb); 2695 2696 depth += sizeof(struct iphdr); 2697 skb_set_transport_header(skb, depth); 2698 th = tcp_hdr(skb); 2699 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2700 iph->daddr, 0); 2701 } else if (type == htons(ETH_P_IPV6)) { 2702 const struct ipv6hdr *iph = ipv6_hdr(skb); 2703 2704 depth += sizeof(struct ipv6hdr); 2705 skb_set_transport_header(skb, depth); 2706 th = tcp_hdr(skb); 2707 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2708 &iph->daddr, 0); 2709 } else { 2710 hns3_rl_err(skb->dev, 2711 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2712 be16_to_cpu(type), depth); 2713 return -EFAULT; 2714 } 2715 2716 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2717 if (th->cwr) 2718 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2719 2720 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2721 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2722 2723 skb->csum_start = (unsigned char *)th - skb->head; 2724 skb->csum_offset = offsetof(struct tcphdr, check); 2725 skb->ip_summed = CHECKSUM_PARTIAL; 2726 2727 trace_hns3_gro(skb); 2728 2729 return 0; 2730 } 2731 2732 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2733 u32 l234info, u32 bd_base_info, u32 ol_info) 2734 { 2735 struct net_device *netdev = ring_to_netdev(ring); 2736 int l3_type, l4_type; 2737 int ol4_type; 2738 2739 skb->ip_summed = CHECKSUM_NONE; 2740 2741 skb_checksum_none_assert(skb); 2742 2743 if (!(netdev->features & NETIF_F_RXCSUM)) 2744 return; 2745 2746 /* check if hardware has done checksum */ 2747 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2748 return; 2749 2750 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2751 BIT(HNS3_RXD_OL3E_B) | 2752 BIT(HNS3_RXD_OL4E_B)))) { 2753 u64_stats_update_begin(&ring->syncp); 2754 ring->stats.l3l4_csum_err++; 2755 u64_stats_update_end(&ring->syncp); 2756 2757 return; 2758 } 2759 2760 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2761 HNS3_RXD_OL4ID_S); 2762 switch (ol4_type) { 2763 case HNS3_OL4_TYPE_MAC_IN_UDP: 2764 case HNS3_OL4_TYPE_NVGRE: 2765 skb->csum_level = 1; 2766 /* fall through */ 2767 case HNS3_OL4_TYPE_NO_TUN: 2768 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2769 HNS3_RXD_L3ID_S); 2770 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2771 HNS3_RXD_L4ID_S); 2772 2773 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2774 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2775 l3_type == HNS3_L3_TYPE_IPV6) && 2776 (l4_type == HNS3_L4_TYPE_UDP || 2777 l4_type == HNS3_L4_TYPE_TCP || 2778 l4_type == HNS3_L4_TYPE_SCTP)) 2779 skb->ip_summed = CHECKSUM_UNNECESSARY; 2780 break; 2781 default: 2782 break; 2783 } 2784 } 2785 2786 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2787 { 2788 if (skb_has_frag_list(skb)) 2789 napi_gro_flush(&ring->tqp_vector->napi, false); 2790 2791 napi_gro_receive(&ring->tqp_vector->napi, skb); 2792 } 2793 2794 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2795 struct hns3_desc *desc, u32 l234info, 2796 u16 *vlan_tag) 2797 { 2798 struct hnae3_handle *handle = ring->tqp->handle; 2799 struct pci_dev *pdev = ring->tqp->handle->pdev; 2800 2801 if (pdev->revision == 0x20) { 2802 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2803 if (!(*vlan_tag & VLAN_VID_MASK)) 2804 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2805 2806 return (*vlan_tag != 0); 2807 } 2808 2809 #define HNS3_STRP_OUTER_VLAN 0x1 2810 #define HNS3_STRP_INNER_VLAN 0x2 2811 #define HNS3_STRP_BOTH 0x3 2812 2813 /* Hardware always insert VLAN tag into RX descriptor when 2814 * remove the tag from packet, driver needs to determine 2815 * reporting which tag to stack. 2816 */ 2817 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2818 HNS3_RXD_STRP_TAGP_S)) { 2819 case HNS3_STRP_OUTER_VLAN: 2820 if (handle->port_base_vlan_state != 2821 HNAE3_PORT_BASE_VLAN_DISABLE) 2822 return false; 2823 2824 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2825 return true; 2826 case HNS3_STRP_INNER_VLAN: 2827 if (handle->port_base_vlan_state != 2828 HNAE3_PORT_BASE_VLAN_DISABLE) 2829 return false; 2830 2831 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2832 return true; 2833 case HNS3_STRP_BOTH: 2834 if (handle->port_base_vlan_state == 2835 HNAE3_PORT_BASE_VLAN_DISABLE) 2836 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2837 else 2838 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2839 2840 return true; 2841 default: 2842 return false; 2843 } 2844 } 2845 2846 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2847 unsigned char *va) 2848 { 2849 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2850 struct net_device *netdev = ring_to_netdev(ring); 2851 struct sk_buff *skb; 2852 2853 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2854 skb = ring->skb; 2855 if (unlikely(!skb)) { 2856 hns3_rl_err(netdev, "alloc rx skb fail\n"); 2857 2858 u64_stats_update_begin(&ring->syncp); 2859 ring->stats.sw_err_cnt++; 2860 u64_stats_update_end(&ring->syncp); 2861 2862 return -ENOMEM; 2863 } 2864 2865 trace_hns3_rx_desc(ring); 2866 prefetchw(skb->data); 2867 2868 ring->pending_buf = 1; 2869 ring->frag_num = 0; 2870 ring->tail_skb = NULL; 2871 if (length <= HNS3_RX_HEAD_SIZE) { 2872 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2873 2874 /* We can reuse buffer as-is, just make sure it is local */ 2875 if (likely(hns3_page_is_reusable(desc_cb->priv))) 2876 desc_cb->reuse_flag = 1; 2877 else /* This page cannot be reused so discard it */ 2878 put_page(desc_cb->priv); 2879 2880 ring_ptr_move_fw(ring, next_to_clean); 2881 return 0; 2882 } 2883 u64_stats_update_begin(&ring->syncp); 2884 ring->stats.seg_pkt_cnt++; 2885 u64_stats_update_end(&ring->syncp); 2886 2887 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2888 __skb_put(skb, ring->pull_len); 2889 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2890 desc_cb); 2891 ring_ptr_move_fw(ring, next_to_clean); 2892 2893 return 0; 2894 } 2895 2896 static int hns3_add_frag(struct hns3_enet_ring *ring) 2897 { 2898 struct sk_buff *skb = ring->skb; 2899 struct sk_buff *head_skb = skb; 2900 struct sk_buff *new_skb; 2901 struct hns3_desc_cb *desc_cb; 2902 struct hns3_desc *desc; 2903 u32 bd_base_info; 2904 2905 do { 2906 desc = &ring->desc[ring->next_to_clean]; 2907 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2908 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2909 /* make sure HW write desc complete */ 2910 dma_rmb(); 2911 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2912 return -ENXIO; 2913 2914 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2915 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 2916 if (unlikely(!new_skb)) { 2917 hns3_rl_err(ring_to_netdev(ring), 2918 "alloc rx fraglist skb fail\n"); 2919 return -ENXIO; 2920 } 2921 ring->frag_num = 0; 2922 2923 if (ring->tail_skb) { 2924 ring->tail_skb->next = new_skb; 2925 ring->tail_skb = new_skb; 2926 } else { 2927 skb_shinfo(skb)->frag_list = new_skb; 2928 ring->tail_skb = new_skb; 2929 } 2930 } 2931 2932 if (ring->tail_skb) { 2933 head_skb->truesize += hns3_buf_size(ring); 2934 head_skb->data_len += le16_to_cpu(desc->rx.size); 2935 head_skb->len += le16_to_cpu(desc->rx.size); 2936 skb = ring->tail_skb; 2937 } 2938 2939 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2940 trace_hns3_rx_desc(ring); 2941 ring_ptr_move_fw(ring, next_to_clean); 2942 ring->pending_buf++; 2943 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 2944 2945 return 0; 2946 } 2947 2948 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2949 struct sk_buff *skb, u32 l234info, 2950 u32 bd_base_info, u32 ol_info) 2951 { 2952 u32 l3_type; 2953 2954 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2955 HNS3_RXD_GRO_SIZE_M, 2956 HNS3_RXD_GRO_SIZE_S); 2957 /* if there is no HW GRO, do not set gro params */ 2958 if (!skb_shinfo(skb)->gso_size) { 2959 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 2960 return 0; 2961 } 2962 2963 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 2964 HNS3_RXD_GRO_COUNT_M, 2965 HNS3_RXD_GRO_COUNT_S); 2966 2967 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 2968 if (l3_type == HNS3_L3_TYPE_IPV4) 2969 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2970 else if (l3_type == HNS3_L3_TYPE_IPV6) 2971 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2972 else 2973 return -EFAULT; 2974 2975 return hns3_gro_complete(skb, l234info); 2976 } 2977 2978 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2979 struct sk_buff *skb, u32 rss_hash) 2980 { 2981 struct hnae3_handle *handle = ring->tqp->handle; 2982 enum pkt_hash_types rss_type; 2983 2984 if (rss_hash) 2985 rss_type = handle->kinfo.rss_type; 2986 else 2987 rss_type = PKT_HASH_TYPE_NONE; 2988 2989 skb_set_hash(skb, rss_hash, rss_type); 2990 } 2991 2992 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 2993 { 2994 struct net_device *netdev = ring_to_netdev(ring); 2995 enum hns3_pkt_l2t_type l2_frame_type; 2996 u32 bd_base_info, l234info, ol_info; 2997 struct hns3_desc *desc; 2998 unsigned int len; 2999 int pre_ntc, ret; 3000 3001 /* bdinfo handled below is only valid on the last BD of the 3002 * current packet, and ring->next_to_clean indicates the first 3003 * descriptor of next packet, so need - 1 below. 3004 */ 3005 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3006 (ring->desc_num - 1); 3007 desc = &ring->desc[pre_ntc]; 3008 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3009 l234info = le32_to_cpu(desc->rx.l234_info); 3010 ol_info = le32_to_cpu(desc->rx.ol_info); 3011 3012 /* Based on hw strategy, the tag offloaded will be stored at 3013 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3014 * in one layer tag case. 3015 */ 3016 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3017 u16 vlan_tag; 3018 3019 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3020 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3021 vlan_tag); 3022 } 3023 3024 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3025 BIT(HNS3_RXD_L2E_B))))) { 3026 u64_stats_update_begin(&ring->syncp); 3027 if (l234info & BIT(HNS3_RXD_L2E_B)) 3028 ring->stats.l2_err++; 3029 else 3030 ring->stats.err_pkt_len++; 3031 u64_stats_update_end(&ring->syncp); 3032 3033 return -EFAULT; 3034 } 3035 3036 len = skb->len; 3037 3038 /* Do update ip stack process */ 3039 skb->protocol = eth_type_trans(skb, netdev); 3040 3041 /* This is needed in order to enable forwarding support */ 3042 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3043 bd_base_info, ol_info); 3044 if (unlikely(ret)) { 3045 u64_stats_update_begin(&ring->syncp); 3046 ring->stats.rx_err_cnt++; 3047 u64_stats_update_end(&ring->syncp); 3048 return ret; 3049 } 3050 3051 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3052 HNS3_RXD_DMAC_S); 3053 3054 u64_stats_update_begin(&ring->syncp); 3055 ring->stats.rx_pkts++; 3056 ring->stats.rx_bytes += len; 3057 3058 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3059 ring->stats.rx_multicast++; 3060 3061 u64_stats_update_end(&ring->syncp); 3062 3063 ring->tqp_vector->rx_group.total_bytes += len; 3064 3065 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3066 return 0; 3067 } 3068 3069 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3070 { 3071 struct sk_buff *skb = ring->skb; 3072 struct hns3_desc_cb *desc_cb; 3073 struct hns3_desc *desc; 3074 unsigned int length; 3075 u32 bd_base_info; 3076 int ret; 3077 3078 desc = &ring->desc[ring->next_to_clean]; 3079 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3080 3081 prefetch(desc); 3082 3083 length = le16_to_cpu(desc->rx.size); 3084 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3085 3086 /* Check valid BD */ 3087 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3088 return -ENXIO; 3089 3090 if (!skb) 3091 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 3092 3093 /* Prefetch first cache line of first page 3094 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 3095 * line size is 64B so need to prefetch twice to make it 128B. But in 3096 * actual we can have greater size of caches with 128B Level 1 cache 3097 * lines. In such a case, single fetch would suffice to cache in the 3098 * relevant part of the header. 3099 */ 3100 prefetch(ring->va); 3101 #if L1_CACHE_BYTES < 128 3102 prefetch(ring->va + L1_CACHE_BYTES); 3103 #endif 3104 3105 if (!skb) { 3106 ret = hns3_alloc_skb(ring, length, ring->va); 3107 skb = ring->skb; 3108 3109 if (ret < 0) /* alloc buffer fail */ 3110 return ret; 3111 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3112 ret = hns3_add_frag(ring); 3113 if (ret) 3114 return ret; 3115 } 3116 } else { 3117 ret = hns3_add_frag(ring); 3118 if (ret) 3119 return ret; 3120 } 3121 3122 /* As the head data may be changed when GRO enable, copy 3123 * the head data in after other data rx completed 3124 */ 3125 if (skb->len > HNS3_RX_HEAD_SIZE) 3126 memcpy(skb->data, ring->va, 3127 ALIGN(ring->pull_len, sizeof(long))); 3128 3129 ret = hns3_handle_bdinfo(ring, skb); 3130 if (unlikely(ret)) { 3131 dev_kfree_skb_any(skb); 3132 return ret; 3133 } 3134 3135 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3136 return 0; 3137 } 3138 3139 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3140 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3141 { 3142 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3143 int unused_count = hns3_desc_unused(ring); 3144 int recv_pkts = 0; 3145 int recv_bds = 0; 3146 int err, num; 3147 3148 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 3149 num -= unused_count; 3150 unused_count -= ring->pending_buf; 3151 3152 if (num <= 0) 3153 goto out; 3154 3155 rmb(); /* Make sure num taken effect before the other data is touched */ 3156 3157 while (recv_pkts < budget && recv_bds < num) { 3158 /* Reuse or realloc buffers */ 3159 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3160 hns3_nic_alloc_rx_buffers(ring, unused_count); 3161 unused_count = hns3_desc_unused(ring) - 3162 ring->pending_buf; 3163 } 3164 3165 /* Poll one pkt */ 3166 err = hns3_handle_rx_bd(ring); 3167 /* Do not get FE for the packet or failed to alloc skb */ 3168 if (unlikely(!ring->skb || err == -ENXIO)) { 3169 goto out; 3170 } else if (likely(!err)) { 3171 rx_fn(ring, ring->skb); 3172 recv_pkts++; 3173 } 3174 3175 recv_bds += ring->pending_buf; 3176 unused_count += ring->pending_buf; 3177 ring->skb = NULL; 3178 ring->pending_buf = 0; 3179 } 3180 3181 out: 3182 /* Make all data has been write before submit */ 3183 if (unused_count > 0) 3184 hns3_nic_alloc_rx_buffers(ring, unused_count); 3185 3186 return recv_pkts; 3187 } 3188 3189 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3190 { 3191 #define HNS3_RX_LOW_BYTE_RATE 10000 3192 #define HNS3_RX_MID_BYTE_RATE 20000 3193 #define HNS3_RX_ULTRA_PACKET_RATE 40 3194 3195 enum hns3_flow_level_range new_flow_level; 3196 struct hns3_enet_tqp_vector *tqp_vector; 3197 int packets_per_msecs, bytes_per_msecs; 3198 u32 time_passed_ms; 3199 3200 tqp_vector = ring_group->ring->tqp_vector; 3201 time_passed_ms = 3202 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3203 if (!time_passed_ms) 3204 return false; 3205 3206 do_div(ring_group->total_packets, time_passed_ms); 3207 packets_per_msecs = ring_group->total_packets; 3208 3209 do_div(ring_group->total_bytes, time_passed_ms); 3210 bytes_per_msecs = ring_group->total_bytes; 3211 3212 new_flow_level = ring_group->coal.flow_level; 3213 3214 /* Simple throttlerate management 3215 * 0-10MB/s lower (50000 ints/s) 3216 * 10-20MB/s middle (20000 ints/s) 3217 * 20-1249MB/s high (18000 ints/s) 3218 * > 40000pps ultra (8000 ints/s) 3219 */ 3220 switch (new_flow_level) { 3221 case HNS3_FLOW_LOW: 3222 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3223 new_flow_level = HNS3_FLOW_MID; 3224 break; 3225 case HNS3_FLOW_MID: 3226 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3227 new_flow_level = HNS3_FLOW_HIGH; 3228 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3229 new_flow_level = HNS3_FLOW_LOW; 3230 break; 3231 case HNS3_FLOW_HIGH: 3232 case HNS3_FLOW_ULTRA: 3233 default: 3234 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3235 new_flow_level = HNS3_FLOW_MID; 3236 break; 3237 } 3238 3239 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3240 &tqp_vector->rx_group == ring_group) 3241 new_flow_level = HNS3_FLOW_ULTRA; 3242 3243 ring_group->total_bytes = 0; 3244 ring_group->total_packets = 0; 3245 ring_group->coal.flow_level = new_flow_level; 3246 3247 return true; 3248 } 3249 3250 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3251 { 3252 struct hns3_enet_tqp_vector *tqp_vector; 3253 u16 new_int_gl; 3254 3255 if (!ring_group->ring) 3256 return false; 3257 3258 tqp_vector = ring_group->ring->tqp_vector; 3259 if (!tqp_vector->last_jiffies) 3260 return false; 3261 3262 if (ring_group->total_packets == 0) { 3263 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3264 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3265 return true; 3266 } 3267 3268 if (!hns3_get_new_flow_lvl(ring_group)) 3269 return false; 3270 3271 new_int_gl = ring_group->coal.int_gl; 3272 switch (ring_group->coal.flow_level) { 3273 case HNS3_FLOW_LOW: 3274 new_int_gl = HNS3_INT_GL_50K; 3275 break; 3276 case HNS3_FLOW_MID: 3277 new_int_gl = HNS3_INT_GL_20K; 3278 break; 3279 case HNS3_FLOW_HIGH: 3280 new_int_gl = HNS3_INT_GL_18K; 3281 break; 3282 case HNS3_FLOW_ULTRA: 3283 new_int_gl = HNS3_INT_GL_8K; 3284 break; 3285 default: 3286 break; 3287 } 3288 3289 if (new_int_gl != ring_group->coal.int_gl) { 3290 ring_group->coal.int_gl = new_int_gl; 3291 return true; 3292 } 3293 return false; 3294 } 3295 3296 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3297 { 3298 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3299 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3300 bool rx_update, tx_update; 3301 3302 /* update param every 1000ms */ 3303 if (time_before(jiffies, 3304 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3305 return; 3306 3307 if (rx_group->coal.gl_adapt_enable) { 3308 rx_update = hns3_get_new_int_gl(rx_group); 3309 if (rx_update) 3310 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3311 rx_group->coal.int_gl); 3312 } 3313 3314 if (tx_group->coal.gl_adapt_enable) { 3315 tx_update = hns3_get_new_int_gl(tx_group); 3316 if (tx_update) 3317 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3318 tx_group->coal.int_gl); 3319 } 3320 3321 tqp_vector->last_jiffies = jiffies; 3322 } 3323 3324 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3325 { 3326 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3327 struct hns3_enet_ring *ring; 3328 int rx_pkt_total = 0; 3329 3330 struct hns3_enet_tqp_vector *tqp_vector = 3331 container_of(napi, struct hns3_enet_tqp_vector, napi); 3332 bool clean_complete = true; 3333 int rx_budget = budget; 3334 3335 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3336 napi_complete(napi); 3337 return 0; 3338 } 3339 3340 /* Since the actual Tx work is minimal, we can give the Tx a larger 3341 * budget and be more aggressive about cleaning up the Tx descriptors. 3342 */ 3343 hns3_for_each_ring(ring, tqp_vector->tx_group) 3344 hns3_clean_tx_ring(ring); 3345 3346 /* make sure rx ring budget not smaller than 1 */ 3347 if (tqp_vector->num_tqps > 1) 3348 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3349 3350 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3351 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3352 hns3_rx_skb); 3353 3354 if (rx_cleaned >= rx_budget) 3355 clean_complete = false; 3356 3357 rx_pkt_total += rx_cleaned; 3358 } 3359 3360 tqp_vector->rx_group.total_packets += rx_pkt_total; 3361 3362 if (!clean_complete) 3363 return budget; 3364 3365 if (napi_complete(napi) && 3366 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3367 hns3_update_new_int_gl(tqp_vector); 3368 hns3_mask_vector_irq(tqp_vector, 1); 3369 } 3370 3371 return rx_pkt_total; 3372 } 3373 3374 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3375 struct hnae3_ring_chain_node *head) 3376 { 3377 struct pci_dev *pdev = tqp_vector->handle->pdev; 3378 struct hnae3_ring_chain_node *cur_chain = head; 3379 struct hnae3_ring_chain_node *chain; 3380 struct hns3_enet_ring *tx_ring; 3381 struct hns3_enet_ring *rx_ring; 3382 3383 tx_ring = tqp_vector->tx_group.ring; 3384 if (tx_ring) { 3385 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3386 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3387 HNAE3_RING_TYPE_TX); 3388 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3389 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3390 3391 cur_chain->next = NULL; 3392 3393 while (tx_ring->next) { 3394 tx_ring = tx_ring->next; 3395 3396 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3397 GFP_KERNEL); 3398 if (!chain) 3399 goto err_free_chain; 3400 3401 cur_chain->next = chain; 3402 chain->tqp_index = tx_ring->tqp->tqp_index; 3403 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3404 HNAE3_RING_TYPE_TX); 3405 hnae3_set_field(chain->int_gl_idx, 3406 HNAE3_RING_GL_IDX_M, 3407 HNAE3_RING_GL_IDX_S, 3408 HNAE3_RING_GL_TX); 3409 3410 cur_chain = chain; 3411 } 3412 } 3413 3414 rx_ring = tqp_vector->rx_group.ring; 3415 if (!tx_ring && rx_ring) { 3416 cur_chain->next = NULL; 3417 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3418 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3419 HNAE3_RING_TYPE_RX); 3420 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3421 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3422 3423 rx_ring = rx_ring->next; 3424 } 3425 3426 while (rx_ring) { 3427 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3428 if (!chain) 3429 goto err_free_chain; 3430 3431 cur_chain->next = chain; 3432 chain->tqp_index = rx_ring->tqp->tqp_index; 3433 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3434 HNAE3_RING_TYPE_RX); 3435 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3436 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3437 3438 cur_chain = chain; 3439 3440 rx_ring = rx_ring->next; 3441 } 3442 3443 return 0; 3444 3445 err_free_chain: 3446 cur_chain = head->next; 3447 while (cur_chain) { 3448 chain = cur_chain->next; 3449 devm_kfree(&pdev->dev, cur_chain); 3450 cur_chain = chain; 3451 } 3452 head->next = NULL; 3453 3454 return -ENOMEM; 3455 } 3456 3457 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3458 struct hnae3_ring_chain_node *head) 3459 { 3460 struct pci_dev *pdev = tqp_vector->handle->pdev; 3461 struct hnae3_ring_chain_node *chain_tmp, *chain; 3462 3463 chain = head->next; 3464 3465 while (chain) { 3466 chain_tmp = chain->next; 3467 devm_kfree(&pdev->dev, chain); 3468 chain = chain_tmp; 3469 } 3470 } 3471 3472 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3473 struct hns3_enet_ring *ring) 3474 { 3475 ring->next = group->ring; 3476 group->ring = ring; 3477 3478 group->count++; 3479 } 3480 3481 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3482 { 3483 struct pci_dev *pdev = priv->ae_handle->pdev; 3484 struct hns3_enet_tqp_vector *tqp_vector; 3485 int num_vectors = priv->vector_num; 3486 int numa_node; 3487 int vector_i; 3488 3489 numa_node = dev_to_node(&pdev->dev); 3490 3491 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3492 tqp_vector = &priv->tqp_vector[vector_i]; 3493 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3494 &tqp_vector->affinity_mask); 3495 } 3496 } 3497 3498 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3499 { 3500 struct hnae3_ring_chain_node vector_ring_chain; 3501 struct hnae3_handle *h = priv->ae_handle; 3502 struct hns3_enet_tqp_vector *tqp_vector; 3503 int ret = 0; 3504 int i; 3505 3506 hns3_nic_set_cpumask(priv); 3507 3508 for (i = 0; i < priv->vector_num; i++) { 3509 tqp_vector = &priv->tqp_vector[i]; 3510 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3511 tqp_vector->num_tqps = 0; 3512 } 3513 3514 for (i = 0; i < h->kinfo.num_tqps; i++) { 3515 u16 vector_i = i % priv->vector_num; 3516 u16 tqp_num = h->kinfo.num_tqps; 3517 3518 tqp_vector = &priv->tqp_vector[vector_i]; 3519 3520 hns3_add_ring_to_group(&tqp_vector->tx_group, 3521 &priv->ring[i]); 3522 3523 hns3_add_ring_to_group(&tqp_vector->rx_group, 3524 &priv->ring[i + tqp_num]); 3525 3526 priv->ring[i].tqp_vector = tqp_vector; 3527 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3528 tqp_vector->num_tqps++; 3529 } 3530 3531 for (i = 0; i < priv->vector_num; i++) { 3532 tqp_vector = &priv->tqp_vector[i]; 3533 3534 tqp_vector->rx_group.total_bytes = 0; 3535 tqp_vector->rx_group.total_packets = 0; 3536 tqp_vector->tx_group.total_bytes = 0; 3537 tqp_vector->tx_group.total_packets = 0; 3538 tqp_vector->handle = h; 3539 3540 ret = hns3_get_vector_ring_chain(tqp_vector, 3541 &vector_ring_chain); 3542 if (ret) 3543 goto map_ring_fail; 3544 3545 ret = h->ae_algo->ops->map_ring_to_vector(h, 3546 tqp_vector->vector_irq, &vector_ring_chain); 3547 3548 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3549 3550 if (ret) 3551 goto map_ring_fail; 3552 3553 netif_napi_add(priv->netdev, &tqp_vector->napi, 3554 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3555 } 3556 3557 return 0; 3558 3559 map_ring_fail: 3560 while (i--) 3561 netif_napi_del(&priv->tqp_vector[i].napi); 3562 3563 return ret; 3564 } 3565 3566 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3567 { 3568 #define HNS3_VECTOR_PF_MAX_NUM 64 3569 3570 struct hnae3_handle *h = priv->ae_handle; 3571 struct hns3_enet_tqp_vector *tqp_vector; 3572 struct hnae3_vector_info *vector; 3573 struct pci_dev *pdev = h->pdev; 3574 u16 tqp_num = h->kinfo.num_tqps; 3575 u16 vector_num; 3576 int ret = 0; 3577 u16 i; 3578 3579 /* RSS size, cpu online and vector_num should be the same */ 3580 /* Should consider 2p/4p later */ 3581 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3582 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3583 3584 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3585 GFP_KERNEL); 3586 if (!vector) 3587 return -ENOMEM; 3588 3589 /* save the actual available vector number */ 3590 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3591 3592 priv->vector_num = vector_num; 3593 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3594 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3595 GFP_KERNEL); 3596 if (!priv->tqp_vector) { 3597 ret = -ENOMEM; 3598 goto out; 3599 } 3600 3601 for (i = 0; i < priv->vector_num; i++) { 3602 tqp_vector = &priv->tqp_vector[i]; 3603 tqp_vector->idx = i; 3604 tqp_vector->mask_addr = vector[i].io_addr; 3605 tqp_vector->vector_irq = vector[i].vector; 3606 hns3_vector_gl_rl_init(tqp_vector, priv); 3607 } 3608 3609 out: 3610 devm_kfree(&pdev->dev, vector); 3611 return ret; 3612 } 3613 3614 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3615 { 3616 group->ring = NULL; 3617 group->count = 0; 3618 } 3619 3620 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3621 { 3622 struct hnae3_ring_chain_node vector_ring_chain; 3623 struct hnae3_handle *h = priv->ae_handle; 3624 struct hns3_enet_tqp_vector *tqp_vector; 3625 int i; 3626 3627 for (i = 0; i < priv->vector_num; i++) { 3628 tqp_vector = &priv->tqp_vector[i]; 3629 3630 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3631 continue; 3632 3633 /* Since the mapping can be overwritten, when fail to get the 3634 * chain between vector and ring, we should go on to deal with 3635 * the remaining options. 3636 */ 3637 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 3638 dev_warn(priv->dev, "failed to get ring chain\n"); 3639 3640 h->ae_algo->ops->unmap_ring_from_vector(h, 3641 tqp_vector->vector_irq, &vector_ring_chain); 3642 3643 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3644 3645 hns3_clear_ring_group(&tqp_vector->rx_group); 3646 hns3_clear_ring_group(&tqp_vector->tx_group); 3647 netif_napi_del(&priv->tqp_vector[i].napi); 3648 } 3649 } 3650 3651 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3652 { 3653 struct hnae3_handle *h = priv->ae_handle; 3654 struct pci_dev *pdev = h->pdev; 3655 int i, ret; 3656 3657 for (i = 0; i < priv->vector_num; i++) { 3658 struct hns3_enet_tqp_vector *tqp_vector; 3659 3660 tqp_vector = &priv->tqp_vector[i]; 3661 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3662 if (ret) 3663 return; 3664 } 3665 3666 devm_kfree(&pdev->dev, priv->tqp_vector); 3667 } 3668 3669 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3670 unsigned int ring_type) 3671 { 3672 int queue_num = priv->ae_handle->kinfo.num_tqps; 3673 struct hns3_enet_ring *ring; 3674 int desc_num; 3675 3676 if (ring_type == HNAE3_RING_TYPE_TX) { 3677 ring = &priv->ring[q->tqp_index]; 3678 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3679 ring->queue_index = q->tqp_index; 3680 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3681 } else { 3682 ring = &priv->ring[q->tqp_index + queue_num]; 3683 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3684 ring->queue_index = q->tqp_index; 3685 ring->io_base = q->io_base; 3686 } 3687 3688 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3689 3690 ring->tqp = q; 3691 ring->desc = NULL; 3692 ring->desc_cb = NULL; 3693 ring->dev = priv->dev; 3694 ring->desc_dma_addr = 0; 3695 ring->buf_size = q->buf_size; 3696 ring->desc_num = desc_num; 3697 ring->next_to_use = 0; 3698 ring->next_to_clean = 0; 3699 } 3700 3701 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3702 struct hns3_nic_priv *priv) 3703 { 3704 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3705 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3706 } 3707 3708 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3709 { 3710 struct hnae3_handle *h = priv->ae_handle; 3711 struct pci_dev *pdev = h->pdev; 3712 int i; 3713 3714 priv->ring = devm_kzalloc(&pdev->dev, 3715 array3_size(h->kinfo.num_tqps, 3716 sizeof(*priv->ring), 2), 3717 GFP_KERNEL); 3718 if (!priv->ring) 3719 return -ENOMEM; 3720 3721 for (i = 0; i < h->kinfo.num_tqps; i++) 3722 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3723 3724 return 0; 3725 } 3726 3727 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3728 { 3729 if (!priv->ring) 3730 return; 3731 3732 devm_kfree(priv->dev, priv->ring); 3733 priv->ring = NULL; 3734 } 3735 3736 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3737 { 3738 int ret; 3739 3740 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3741 return -EINVAL; 3742 3743 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3744 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3745 if (!ring->desc_cb) { 3746 ret = -ENOMEM; 3747 goto out; 3748 } 3749 3750 ret = hns3_alloc_desc(ring); 3751 if (ret) 3752 goto out_with_desc_cb; 3753 3754 if (!HNAE3_IS_TX_RING(ring)) { 3755 ret = hns3_alloc_ring_buffers(ring); 3756 if (ret) 3757 goto out_with_desc; 3758 } 3759 3760 return 0; 3761 3762 out_with_desc: 3763 hns3_free_desc(ring); 3764 out_with_desc_cb: 3765 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3766 ring->desc_cb = NULL; 3767 out: 3768 return ret; 3769 } 3770 3771 void hns3_fini_ring(struct hns3_enet_ring *ring) 3772 { 3773 hns3_free_desc(ring); 3774 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3775 ring->desc_cb = NULL; 3776 ring->next_to_clean = 0; 3777 ring->next_to_use = 0; 3778 ring->pending_buf = 0; 3779 if (ring->skb) { 3780 dev_kfree_skb_any(ring->skb); 3781 ring->skb = NULL; 3782 } 3783 } 3784 3785 static int hns3_buf_size2type(u32 buf_size) 3786 { 3787 int bd_size_type; 3788 3789 switch (buf_size) { 3790 case 512: 3791 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3792 break; 3793 case 1024: 3794 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3795 break; 3796 case 2048: 3797 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3798 break; 3799 case 4096: 3800 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3801 break; 3802 default: 3803 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3804 } 3805 3806 return bd_size_type; 3807 } 3808 3809 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3810 { 3811 dma_addr_t dma = ring->desc_dma_addr; 3812 struct hnae3_queue *q = ring->tqp; 3813 3814 if (!HNAE3_IS_TX_RING(ring)) { 3815 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3816 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3817 (u32)((dma >> 31) >> 1)); 3818 3819 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3820 hns3_buf_size2type(ring->buf_size)); 3821 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3822 ring->desc_num / 8 - 1); 3823 3824 } else { 3825 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3826 (u32)dma); 3827 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3828 (u32)((dma >> 31) >> 1)); 3829 3830 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3831 ring->desc_num / 8 - 1); 3832 } 3833 } 3834 3835 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3836 { 3837 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3838 int i; 3839 3840 for (i = 0; i < HNAE3_MAX_TC; i++) { 3841 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3842 int j; 3843 3844 if (!tc_info->enable) 3845 continue; 3846 3847 for (j = 0; j < tc_info->tqp_count; j++) { 3848 struct hnae3_queue *q; 3849 3850 q = priv->ring[tc_info->tqp_offset + j].tqp; 3851 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3852 tc_info->tc); 3853 } 3854 } 3855 } 3856 3857 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3858 { 3859 struct hnae3_handle *h = priv->ae_handle; 3860 int ring_num = h->kinfo.num_tqps * 2; 3861 int i, j; 3862 int ret; 3863 3864 for (i = 0; i < ring_num; i++) { 3865 ret = hns3_alloc_ring_memory(&priv->ring[i]); 3866 if (ret) { 3867 dev_err(priv->dev, 3868 "Alloc ring memory fail! ret=%d\n", ret); 3869 goto out_when_alloc_ring_memory; 3870 } 3871 3872 u64_stats_init(&priv->ring[i].syncp); 3873 } 3874 3875 return 0; 3876 3877 out_when_alloc_ring_memory: 3878 for (j = i - 1; j >= 0; j--) 3879 hns3_fini_ring(&priv->ring[j]); 3880 3881 return -ENOMEM; 3882 } 3883 3884 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3885 { 3886 struct hnae3_handle *h = priv->ae_handle; 3887 int i; 3888 3889 for (i = 0; i < h->kinfo.num_tqps; i++) { 3890 hns3_fini_ring(&priv->ring[i]); 3891 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 3892 } 3893 return 0; 3894 } 3895 3896 /* Set mac addr if it is configured. or leave it to the AE driver */ 3897 static int hns3_init_mac_addr(struct net_device *netdev) 3898 { 3899 struct hns3_nic_priv *priv = netdev_priv(netdev); 3900 struct hnae3_handle *h = priv->ae_handle; 3901 u8 mac_addr_temp[ETH_ALEN]; 3902 int ret = 0; 3903 3904 if (h->ae_algo->ops->get_mac_addr) 3905 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3906 3907 /* Check if the MAC address is valid, if not get a random one */ 3908 if (!is_valid_ether_addr(mac_addr_temp)) { 3909 eth_hw_addr_random(netdev); 3910 dev_warn(priv->dev, "using random MAC address %pM\n", 3911 netdev->dev_addr); 3912 } else { 3913 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3914 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 3915 } 3916 3917 if (h->ae_algo->ops->set_mac_addr) 3918 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3919 3920 return ret; 3921 } 3922 3923 static int hns3_init_phy(struct net_device *netdev) 3924 { 3925 struct hnae3_handle *h = hns3_get_handle(netdev); 3926 int ret = 0; 3927 3928 if (h->ae_algo->ops->mac_connect_phy) 3929 ret = h->ae_algo->ops->mac_connect_phy(h); 3930 3931 return ret; 3932 } 3933 3934 static void hns3_uninit_phy(struct net_device *netdev) 3935 { 3936 struct hnae3_handle *h = hns3_get_handle(netdev); 3937 3938 if (h->ae_algo->ops->mac_disconnect_phy) 3939 h->ae_algo->ops->mac_disconnect_phy(h); 3940 } 3941 3942 static int hns3_restore_fd_rules(struct net_device *netdev) 3943 { 3944 struct hnae3_handle *h = hns3_get_handle(netdev); 3945 int ret = 0; 3946 3947 if (h->ae_algo->ops->restore_fd_rules) 3948 ret = h->ae_algo->ops->restore_fd_rules(h); 3949 3950 return ret; 3951 } 3952 3953 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3954 { 3955 struct hnae3_handle *h = hns3_get_handle(netdev); 3956 3957 if (h->ae_algo->ops->del_all_fd_entries) 3958 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3959 } 3960 3961 static int hns3_client_start(struct hnae3_handle *handle) 3962 { 3963 if (!handle->ae_algo->ops->client_start) 3964 return 0; 3965 3966 return handle->ae_algo->ops->client_start(handle); 3967 } 3968 3969 static void hns3_client_stop(struct hnae3_handle *handle) 3970 { 3971 if (!handle->ae_algo->ops->client_stop) 3972 return; 3973 3974 handle->ae_algo->ops->client_stop(handle); 3975 } 3976 3977 static void hns3_info_show(struct hns3_nic_priv *priv) 3978 { 3979 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3980 3981 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 3982 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 3983 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 3984 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 3985 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 3986 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 3987 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 3988 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 3989 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 3990 } 3991 3992 static int hns3_client_init(struct hnae3_handle *handle) 3993 { 3994 struct pci_dev *pdev = handle->pdev; 3995 u16 alloc_tqps, max_rss_size; 3996 struct hns3_nic_priv *priv; 3997 struct net_device *netdev; 3998 int ret; 3999 4000 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 4001 &max_rss_size); 4002 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 4003 if (!netdev) 4004 return -ENOMEM; 4005 4006 priv = netdev_priv(netdev); 4007 priv->dev = &pdev->dev; 4008 priv->netdev = netdev; 4009 priv->ae_handle = handle; 4010 priv->tx_timeout_count = 0; 4011 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 4012 4013 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 4014 4015 handle->kinfo.netdev = netdev; 4016 handle->priv = (void *)priv; 4017 4018 hns3_init_mac_addr(netdev); 4019 4020 hns3_set_default_feature(netdev); 4021 4022 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4023 netdev->priv_flags |= IFF_UNICAST_FLT; 4024 netdev->netdev_ops = &hns3_nic_netdev_ops; 4025 SET_NETDEV_DEV(netdev, &pdev->dev); 4026 hns3_ethtool_set_ops(netdev); 4027 4028 /* Carrier off reporting is important to ethtool even BEFORE open */ 4029 netif_carrier_off(netdev); 4030 4031 ret = hns3_get_ring_config(priv); 4032 if (ret) { 4033 ret = -ENOMEM; 4034 goto out_get_ring_cfg; 4035 } 4036 4037 ret = hns3_nic_alloc_vector_data(priv); 4038 if (ret) { 4039 ret = -ENOMEM; 4040 goto out_alloc_vector_data; 4041 } 4042 4043 ret = hns3_nic_init_vector_data(priv); 4044 if (ret) { 4045 ret = -ENOMEM; 4046 goto out_init_vector_data; 4047 } 4048 4049 ret = hns3_init_all_ring(priv); 4050 if (ret) { 4051 ret = -ENOMEM; 4052 goto out_init_ring; 4053 } 4054 4055 ret = hns3_init_phy(netdev); 4056 if (ret) 4057 goto out_init_phy; 4058 4059 ret = register_netdev(netdev); 4060 if (ret) { 4061 dev_err(priv->dev, "probe register netdev fail!\n"); 4062 goto out_reg_netdev_fail; 4063 } 4064 4065 /* the device can work without cpu rmap, only aRFS needs it */ 4066 ret = hns3_set_rx_cpu_rmap(netdev); 4067 if (ret) 4068 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4069 4070 ret = hns3_nic_init_irq(priv); 4071 if (ret) { 4072 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4073 hns3_free_rx_cpu_rmap(netdev); 4074 goto out_init_irq_fail; 4075 } 4076 4077 ret = hns3_client_start(handle); 4078 if (ret) { 4079 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4080 goto out_client_start; 4081 } 4082 4083 hns3_dcbnl_setup(handle); 4084 4085 hns3_dbg_init(handle); 4086 4087 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 4088 netdev->max_mtu = HNS3_MAX_MTU; 4089 4090 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4091 4092 if (netif_msg_drv(handle)) 4093 hns3_info_show(priv); 4094 4095 return ret; 4096 4097 out_client_start: 4098 hns3_free_rx_cpu_rmap(netdev); 4099 hns3_nic_uninit_irq(priv); 4100 out_init_irq_fail: 4101 unregister_netdev(netdev); 4102 out_reg_netdev_fail: 4103 hns3_uninit_phy(netdev); 4104 out_init_phy: 4105 hns3_uninit_all_ring(priv); 4106 out_init_ring: 4107 hns3_nic_uninit_vector_data(priv); 4108 out_init_vector_data: 4109 hns3_nic_dealloc_vector_data(priv); 4110 out_alloc_vector_data: 4111 priv->ring = NULL; 4112 out_get_ring_cfg: 4113 priv->ae_handle = NULL; 4114 free_netdev(netdev); 4115 return ret; 4116 } 4117 4118 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4119 { 4120 struct net_device *netdev = handle->kinfo.netdev; 4121 struct hns3_nic_priv *priv = netdev_priv(netdev); 4122 int ret; 4123 4124 hns3_remove_hw_addr(netdev); 4125 4126 if (netdev->reg_state != NETREG_UNINITIALIZED) 4127 unregister_netdev(netdev); 4128 4129 hns3_client_stop(handle); 4130 4131 hns3_uninit_phy(netdev); 4132 4133 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4134 netdev_warn(netdev, "already uninitialized\n"); 4135 goto out_netdev_free; 4136 } 4137 4138 hns3_free_rx_cpu_rmap(netdev); 4139 4140 hns3_nic_uninit_irq(priv); 4141 4142 hns3_del_all_fd_rules(netdev, true); 4143 4144 hns3_clear_all_ring(handle, true); 4145 4146 hns3_nic_uninit_vector_data(priv); 4147 4148 hns3_nic_dealloc_vector_data(priv); 4149 4150 ret = hns3_uninit_all_ring(priv); 4151 if (ret) 4152 netdev_err(netdev, "uninit ring error\n"); 4153 4154 hns3_put_ring_config(priv); 4155 4156 hns3_dbg_uninit(handle); 4157 4158 out_netdev_free: 4159 free_netdev(netdev); 4160 } 4161 4162 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4163 { 4164 struct net_device *netdev = handle->kinfo.netdev; 4165 4166 if (!netdev) 4167 return; 4168 4169 if (linkup) { 4170 netif_carrier_on(netdev); 4171 netif_tx_wake_all_queues(netdev); 4172 if (netif_msg_link(handle)) 4173 netdev_info(netdev, "link up\n"); 4174 } else { 4175 netif_carrier_off(netdev); 4176 netif_tx_stop_all_queues(netdev); 4177 if (netif_msg_link(handle)) 4178 netdev_info(netdev, "link down\n"); 4179 } 4180 } 4181 4182 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4183 { 4184 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4185 struct net_device *ndev = kinfo->netdev; 4186 4187 if (tc > HNAE3_MAX_TC) 4188 return -EINVAL; 4189 4190 if (!ndev) 4191 return -ENODEV; 4192 4193 return hns3_nic_set_real_num_queue(ndev); 4194 } 4195 4196 static int hns3_recover_hw_addr(struct net_device *ndev) 4197 { 4198 struct netdev_hw_addr_list *list; 4199 struct netdev_hw_addr *ha, *tmp; 4200 int ret = 0; 4201 4202 netif_addr_lock_bh(ndev); 4203 /* go through and sync uc_addr entries to the device */ 4204 list = &ndev->uc; 4205 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4206 ret = hns3_nic_uc_sync(ndev, ha->addr); 4207 if (ret) 4208 goto out; 4209 } 4210 4211 /* go through and sync mc_addr entries to the device */ 4212 list = &ndev->mc; 4213 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4214 ret = hns3_nic_mc_sync(ndev, ha->addr); 4215 if (ret) 4216 goto out; 4217 } 4218 4219 out: 4220 netif_addr_unlock_bh(ndev); 4221 return ret; 4222 } 4223 4224 static void hns3_remove_hw_addr(struct net_device *netdev) 4225 { 4226 struct netdev_hw_addr_list *list; 4227 struct netdev_hw_addr *ha, *tmp; 4228 4229 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 4230 4231 netif_addr_lock_bh(netdev); 4232 /* go through and unsync uc_addr entries to the device */ 4233 list = &netdev->uc; 4234 list_for_each_entry_safe(ha, tmp, &list->list, list) 4235 hns3_nic_uc_unsync(netdev, ha->addr); 4236 4237 /* go through and unsync mc_addr entries to the device */ 4238 list = &netdev->mc; 4239 list_for_each_entry_safe(ha, tmp, &list->list, list) 4240 if (ha->refcount > 1) 4241 hns3_nic_mc_unsync(netdev, ha->addr); 4242 4243 netif_addr_unlock_bh(netdev); 4244 } 4245 4246 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4247 { 4248 while (ring->next_to_clean != ring->next_to_use) { 4249 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4250 hns3_free_buffer_detach(ring, ring->next_to_clean); 4251 ring_ptr_move_fw(ring, next_to_clean); 4252 } 4253 } 4254 4255 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4256 { 4257 struct hns3_desc_cb res_cbs; 4258 int ret; 4259 4260 while (ring->next_to_use != ring->next_to_clean) { 4261 /* When a buffer is not reused, it's memory has been 4262 * freed in hns3_handle_rx_bd or will be freed by 4263 * stack, so we need to replace the buffer here. 4264 */ 4265 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4266 ret = hns3_reserve_buffer_map(ring, &res_cbs); 4267 if (ret) { 4268 u64_stats_update_begin(&ring->syncp); 4269 ring->stats.sw_err_cnt++; 4270 u64_stats_update_end(&ring->syncp); 4271 /* if alloc new buffer fail, exit directly 4272 * and reclear in up flow. 4273 */ 4274 netdev_warn(ring_to_netdev(ring), 4275 "reserve buffer map failed, ret = %d\n", 4276 ret); 4277 return ret; 4278 } 4279 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4280 } 4281 ring_ptr_move_fw(ring, next_to_use); 4282 } 4283 4284 /* Free the pending skb in rx ring */ 4285 if (ring->skb) { 4286 dev_kfree_skb_any(ring->skb); 4287 ring->skb = NULL; 4288 ring->pending_buf = 0; 4289 } 4290 4291 return 0; 4292 } 4293 4294 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4295 { 4296 while (ring->next_to_use != ring->next_to_clean) { 4297 /* When a buffer is not reused, it's memory has been 4298 * freed in hns3_handle_rx_bd or will be freed by 4299 * stack, so only need to unmap the buffer here. 4300 */ 4301 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4302 hns3_unmap_buffer(ring, 4303 &ring->desc_cb[ring->next_to_use]); 4304 ring->desc_cb[ring->next_to_use].dma = 0; 4305 } 4306 4307 ring_ptr_move_fw(ring, next_to_use); 4308 } 4309 } 4310 4311 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4312 { 4313 struct net_device *ndev = h->kinfo.netdev; 4314 struct hns3_nic_priv *priv = netdev_priv(ndev); 4315 u32 i; 4316 4317 for (i = 0; i < h->kinfo.num_tqps; i++) { 4318 struct hns3_enet_ring *ring; 4319 4320 ring = &priv->ring[i]; 4321 hns3_clear_tx_ring(ring); 4322 4323 ring = &priv->ring[i + h->kinfo.num_tqps]; 4324 /* Continue to clear other rings even if clearing some 4325 * rings failed. 4326 */ 4327 if (force) 4328 hns3_force_clear_rx_ring(ring); 4329 else 4330 hns3_clear_rx_ring(ring); 4331 } 4332 } 4333 4334 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4335 { 4336 struct net_device *ndev = h->kinfo.netdev; 4337 struct hns3_nic_priv *priv = netdev_priv(ndev); 4338 struct hns3_enet_ring *rx_ring; 4339 int i, j; 4340 int ret; 4341 4342 for (i = 0; i < h->kinfo.num_tqps; i++) { 4343 ret = h->ae_algo->ops->reset_queue(h, i); 4344 if (ret) 4345 return ret; 4346 4347 hns3_init_ring_hw(&priv->ring[i]); 4348 4349 /* We need to clear tx ring here because self test will 4350 * use the ring and will not run down before up 4351 */ 4352 hns3_clear_tx_ring(&priv->ring[i]); 4353 priv->ring[i].next_to_clean = 0; 4354 priv->ring[i].next_to_use = 0; 4355 4356 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4357 hns3_init_ring_hw(rx_ring); 4358 ret = hns3_clear_rx_ring(rx_ring); 4359 if (ret) 4360 return ret; 4361 4362 /* We can not know the hardware head and tail when this 4363 * function is called in reset flow, so we reuse all desc. 4364 */ 4365 for (j = 0; j < rx_ring->desc_num; j++) 4366 hns3_reuse_buffer(rx_ring, j); 4367 4368 rx_ring->next_to_clean = 0; 4369 rx_ring->next_to_use = 0; 4370 } 4371 4372 hns3_init_tx_ring_tc(priv); 4373 4374 return 0; 4375 } 4376 4377 static void hns3_store_coal(struct hns3_nic_priv *priv) 4378 { 4379 /* ethtool only support setting and querying one coal 4380 * configuration for now, so save the vector 0' coal 4381 * configuration here in order to restore it. 4382 */ 4383 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4384 sizeof(struct hns3_enet_coalesce)); 4385 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4386 sizeof(struct hns3_enet_coalesce)); 4387 } 4388 4389 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4390 { 4391 u16 vector_num = priv->vector_num; 4392 int i; 4393 4394 for (i = 0; i < vector_num; i++) { 4395 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4396 sizeof(struct hns3_enet_coalesce)); 4397 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4398 sizeof(struct hns3_enet_coalesce)); 4399 } 4400 } 4401 4402 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4403 { 4404 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4405 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4406 struct net_device *ndev = kinfo->netdev; 4407 struct hns3_nic_priv *priv = netdev_priv(ndev); 4408 4409 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4410 return 0; 4411 4412 /* it is cumbersome for hardware to pick-and-choose entries for deletion 4413 * from table space. Hence, for function reset software intervention is 4414 * required to delete the entries 4415 */ 4416 if (hns3_dev_ongoing_func_reset(ae_dev)) { 4417 hns3_remove_hw_addr(ndev); 4418 hns3_del_all_fd_rules(ndev, false); 4419 } 4420 4421 if (!netif_running(ndev)) 4422 return 0; 4423 4424 return hns3_nic_net_stop(ndev); 4425 } 4426 4427 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4428 { 4429 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4430 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4431 int ret = 0; 4432 4433 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4434 4435 if (netif_running(kinfo->netdev)) { 4436 ret = hns3_nic_net_open(kinfo->netdev); 4437 if (ret) { 4438 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4439 netdev_err(kinfo->netdev, 4440 "net up fail, ret=%d!\n", ret); 4441 return ret; 4442 } 4443 } 4444 4445 return ret; 4446 } 4447 4448 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4449 { 4450 struct net_device *netdev = handle->kinfo.netdev; 4451 struct hns3_nic_priv *priv = netdev_priv(netdev); 4452 int ret; 4453 4454 /* Carrier off reporting is important to ethtool even BEFORE open */ 4455 netif_carrier_off(netdev); 4456 4457 ret = hns3_get_ring_config(priv); 4458 if (ret) 4459 return ret; 4460 4461 ret = hns3_nic_alloc_vector_data(priv); 4462 if (ret) 4463 goto err_put_ring; 4464 4465 hns3_restore_coal(priv); 4466 4467 ret = hns3_nic_init_vector_data(priv); 4468 if (ret) 4469 goto err_dealloc_vector; 4470 4471 ret = hns3_init_all_ring(priv); 4472 if (ret) 4473 goto err_uninit_vector; 4474 4475 /* the device can work without cpu rmap, only aRFS needs it */ 4476 ret = hns3_set_rx_cpu_rmap(netdev); 4477 if (ret) 4478 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4479 4480 ret = hns3_nic_init_irq(priv); 4481 if (ret) { 4482 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4483 hns3_free_rx_cpu_rmap(netdev); 4484 goto err_init_irq_fail; 4485 } 4486 4487 ret = hns3_client_start(handle); 4488 if (ret) { 4489 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4490 goto err_client_start_fail; 4491 } 4492 4493 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4494 4495 return ret; 4496 4497 err_client_start_fail: 4498 hns3_free_rx_cpu_rmap(netdev); 4499 hns3_nic_uninit_irq(priv); 4500 err_init_irq_fail: 4501 hns3_uninit_all_ring(priv); 4502 err_uninit_vector: 4503 hns3_nic_uninit_vector_data(priv); 4504 err_dealloc_vector: 4505 hns3_nic_dealloc_vector_data(priv); 4506 err_put_ring: 4507 hns3_put_ring_config(priv); 4508 4509 return ret; 4510 } 4511 4512 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4513 { 4514 struct net_device *netdev = handle->kinfo.netdev; 4515 bool vlan_filter_enable; 4516 int ret; 4517 4518 ret = hns3_init_mac_addr(netdev); 4519 if (ret) 4520 return ret; 4521 4522 ret = hns3_recover_hw_addr(netdev); 4523 if (ret) 4524 return ret; 4525 4526 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4527 if (ret) 4528 return ret; 4529 4530 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4531 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4532 4533 if (handle->ae_algo->ops->restore_vlan_table) 4534 handle->ae_algo->ops->restore_vlan_table(handle); 4535 4536 return hns3_restore_fd_rules(netdev); 4537 } 4538 4539 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4540 { 4541 struct net_device *netdev = handle->kinfo.netdev; 4542 struct hns3_nic_priv *priv = netdev_priv(netdev); 4543 int ret; 4544 4545 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4546 netdev_warn(netdev, "already uninitialized\n"); 4547 return 0; 4548 } 4549 4550 hns3_free_rx_cpu_rmap(netdev); 4551 hns3_nic_uninit_irq(priv); 4552 hns3_clear_all_ring(handle, true); 4553 hns3_reset_tx_queue(priv->ae_handle); 4554 4555 hns3_nic_uninit_vector_data(priv); 4556 4557 hns3_store_coal(priv); 4558 4559 hns3_nic_dealloc_vector_data(priv); 4560 4561 ret = hns3_uninit_all_ring(priv); 4562 if (ret) 4563 netdev_err(netdev, "uninit ring error\n"); 4564 4565 hns3_put_ring_config(priv); 4566 4567 return ret; 4568 } 4569 4570 static int hns3_reset_notify(struct hnae3_handle *handle, 4571 enum hnae3_reset_notify_type type) 4572 { 4573 int ret = 0; 4574 4575 switch (type) { 4576 case HNAE3_UP_CLIENT: 4577 ret = hns3_reset_notify_up_enet(handle); 4578 break; 4579 case HNAE3_DOWN_CLIENT: 4580 ret = hns3_reset_notify_down_enet(handle); 4581 break; 4582 case HNAE3_INIT_CLIENT: 4583 ret = hns3_reset_notify_init_enet(handle); 4584 break; 4585 case HNAE3_UNINIT_CLIENT: 4586 ret = hns3_reset_notify_uninit_enet(handle); 4587 break; 4588 case HNAE3_RESTORE_CLIENT: 4589 ret = hns3_reset_notify_restore_enet(handle); 4590 break; 4591 default: 4592 break; 4593 } 4594 4595 return ret; 4596 } 4597 4598 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4599 bool rxfh_configured) 4600 { 4601 int ret; 4602 4603 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4604 rxfh_configured); 4605 if (ret) { 4606 dev_err(&handle->pdev->dev, 4607 "Change tqp num(%u) fail.\n", new_tqp_num); 4608 return ret; 4609 } 4610 4611 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4612 if (ret) 4613 return ret; 4614 4615 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4616 if (ret) 4617 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4618 4619 return ret; 4620 } 4621 4622 int hns3_set_channels(struct net_device *netdev, 4623 struct ethtool_channels *ch) 4624 { 4625 struct hnae3_handle *h = hns3_get_handle(netdev); 4626 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4627 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4628 u32 new_tqp_num = ch->combined_count; 4629 u16 org_tqp_num; 4630 int ret; 4631 4632 if (hns3_nic_resetting(netdev)) 4633 return -EBUSY; 4634 4635 if (ch->rx_count || ch->tx_count) 4636 return -EINVAL; 4637 4638 if (new_tqp_num > hns3_get_max_available_channels(h) || 4639 new_tqp_num < 1) { 4640 dev_err(&netdev->dev, 4641 "Change tqps fail, the tqp range is from 1 to %u", 4642 hns3_get_max_available_channels(h)); 4643 return -EINVAL; 4644 } 4645 4646 if (kinfo->rss_size == new_tqp_num) 4647 return 0; 4648 4649 netif_dbg(h, drv, netdev, 4650 "set channels: tqp_num=%u, rxfh=%d\n", 4651 new_tqp_num, rxfh_configured); 4652 4653 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4654 if (ret) 4655 return ret; 4656 4657 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4658 if (ret) 4659 return ret; 4660 4661 org_tqp_num = h->kinfo.num_tqps; 4662 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4663 if (ret) { 4664 int ret1; 4665 4666 netdev_warn(netdev, 4667 "Change channels fail, revert to old value\n"); 4668 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4669 if (ret1) { 4670 netdev_err(netdev, 4671 "revert to old channel fail\n"); 4672 return ret1; 4673 } 4674 4675 return ret; 4676 } 4677 4678 return 0; 4679 } 4680 4681 static const struct hns3_hw_error_info hns3_hw_err[] = { 4682 { .type = HNAE3_PPU_POISON_ERROR, 4683 .msg = "PPU poison" }, 4684 { .type = HNAE3_CMDQ_ECC_ERROR, 4685 .msg = "IMP CMDQ error" }, 4686 { .type = HNAE3_IMP_RD_POISON_ERROR, 4687 .msg = "IMP RD poison" }, 4688 }; 4689 4690 static void hns3_process_hw_error(struct hnae3_handle *handle, 4691 enum hnae3_hw_error_type type) 4692 { 4693 int i; 4694 4695 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4696 if (hns3_hw_err[i].type == type) { 4697 dev_err(&handle->pdev->dev, "Detected %s!\n", 4698 hns3_hw_err[i].msg); 4699 break; 4700 } 4701 } 4702 } 4703 4704 static const struct hnae3_client_ops client_ops = { 4705 .init_instance = hns3_client_init, 4706 .uninit_instance = hns3_client_uninit, 4707 .link_status_change = hns3_link_status_change, 4708 .setup_tc = hns3_client_setup_tc, 4709 .reset_notify = hns3_reset_notify, 4710 .process_hw_error = hns3_process_hw_error, 4711 }; 4712 4713 /* hns3_init_module - Driver registration routine 4714 * hns3_init_module is the first routine called when the driver is 4715 * loaded. All it does is register with the PCI subsystem. 4716 */ 4717 static int __init hns3_init_module(void) 4718 { 4719 int ret; 4720 4721 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4722 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4723 4724 client.type = HNAE3_CLIENT_KNIC; 4725 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 4726 hns3_driver_name); 4727 4728 client.ops = &client_ops; 4729 4730 INIT_LIST_HEAD(&client.node); 4731 4732 hns3_dbg_register_debugfs(hns3_driver_name); 4733 4734 ret = hnae3_register_client(&client); 4735 if (ret) 4736 goto err_reg_client; 4737 4738 ret = pci_register_driver(&hns3_driver); 4739 if (ret) 4740 goto err_reg_driver; 4741 4742 return ret; 4743 4744 err_reg_driver: 4745 hnae3_unregister_client(&client); 4746 err_reg_client: 4747 hns3_dbg_unregister_debugfs(); 4748 return ret; 4749 } 4750 module_init(hns3_init_module); 4751 4752 /* hns3_exit_module - Driver exit cleanup routine 4753 * hns3_exit_module is called just before the driver is removed 4754 * from memory. 4755 */ 4756 static void __exit hns3_exit_module(void) 4757 { 4758 pci_unregister_driver(&hns3_driver); 4759 hnae3_unregister_client(&client); 4760 hns3_dbg_unregister_debugfs(); 4761 } 4762 module_exit(hns3_exit_module); 4763 4764 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4765 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4766 MODULE_LICENSE("GPL"); 4767 MODULE_ALIAS("pci:hns-nic"); 4768 MODULE_VERSION(HNS3_MOD_VERSION); 4769