1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <linux/clk.h> 39 #include <linux/component.h> 40 #include <linux/i2c.h> 41 #include <linux/of_address.h> 42 #include <linux/of_gpio.h> 43 #include <linux/of_platform.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/rational.h> 46 #include <sound/dmaengine_pcm.h> 47 #include <sound/pcm_drm_eld.h> 48 #include <sound/pcm_params.h> 49 #include <sound/soc.h> 50 #include "media/cec.h" 51 #include "vc4_drv.h" 52 #include "vc4_regs.h" 53 54 #define HSM_CLOCK_FREQ 163682864 55 #define CEC_CLOCK_FREQ 40000 56 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) 57 58 /* HDMI audio information */ 59 struct vc4_hdmi_audio { 60 struct snd_soc_card card; 61 struct snd_soc_dai_link link; 62 struct snd_soc_dai_link_component cpu; 63 struct snd_soc_dai_link_component codec; 64 struct snd_soc_dai_link_component platform; 65 int samplerate; 66 int channels; 67 struct snd_dmaengine_dai_dma_data dma_data; 68 struct snd_pcm_substream *substream; 69 }; 70 71 /* General HDMI hardware state. */ 72 struct vc4_hdmi { 73 struct platform_device *pdev; 74 75 struct drm_encoder *encoder; 76 struct drm_connector *connector; 77 78 struct vc4_hdmi_audio audio; 79 80 struct i2c_adapter *ddc; 81 void __iomem *hdmicore_regs; 82 void __iomem *hd_regs; 83 int hpd_gpio; 84 bool hpd_active_low; 85 86 struct cec_adapter *cec_adap; 87 struct cec_msg cec_rx_msg; 88 bool cec_tx_ok; 89 bool cec_irq_was_rx; 90 91 struct clk *pixel_clock; 92 struct clk *hsm_clock; 93 94 struct debugfs_regset32 hdmi_regset; 95 struct debugfs_regset32 hd_regset; 96 }; 97 98 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 99 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 100 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 101 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 102 103 /* VC4 HDMI encoder KMS struct */ 104 struct vc4_hdmi_encoder { 105 struct vc4_encoder base; 106 bool hdmi_monitor; 107 bool limited_rgb_range; 108 }; 109 110 static inline struct vc4_hdmi_encoder * 111 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 112 { 113 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 114 } 115 116 /* VC4 HDMI connector KMS struct */ 117 struct vc4_hdmi_connector { 118 struct drm_connector base; 119 120 /* Since the connector is attached to just the one encoder, 121 * this is the reference to it so we can do the best_encoder() 122 * hook. 123 */ 124 struct drm_encoder *encoder; 125 }; 126 127 static inline struct vc4_hdmi_connector * 128 to_vc4_hdmi_connector(struct drm_connector *connector) 129 { 130 return container_of(connector, struct vc4_hdmi_connector, base); 131 } 132 133 static const struct debugfs_reg32 hdmi_regs[] = { 134 VC4_REG32(VC4_HDMI_CORE_REV), 135 VC4_REG32(VC4_HDMI_SW_RESET_CONTROL), 136 VC4_REG32(VC4_HDMI_HOTPLUG_INT), 137 VC4_REG32(VC4_HDMI_HOTPLUG), 138 VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP), 139 VC4_REG32(VC4_HDMI_MAI_CONFIG), 140 VC4_REG32(VC4_HDMI_MAI_FORMAT), 141 VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG), 142 VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG), 143 VC4_REG32(VC4_HDMI_HORZA), 144 VC4_REG32(VC4_HDMI_HORZB), 145 VC4_REG32(VC4_HDMI_FIFO_CTL), 146 VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL), 147 VC4_REG32(VC4_HDMI_VERTA0), 148 VC4_REG32(VC4_HDMI_VERTA1), 149 VC4_REG32(VC4_HDMI_VERTB0), 150 VC4_REG32(VC4_HDMI_VERTB1), 151 VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL), 152 VC4_REG32(VC4_HDMI_TX_PHY_CTL0), 153 154 VC4_REG32(VC4_HDMI_CEC_CNTRL_1), 155 VC4_REG32(VC4_HDMI_CEC_CNTRL_2), 156 VC4_REG32(VC4_HDMI_CEC_CNTRL_3), 157 VC4_REG32(VC4_HDMI_CEC_CNTRL_4), 158 VC4_REG32(VC4_HDMI_CEC_CNTRL_5), 159 VC4_REG32(VC4_HDMI_CPU_STATUS), 160 VC4_REG32(VC4_HDMI_CPU_MASK_STATUS), 161 162 VC4_REG32(VC4_HDMI_CEC_RX_DATA_1), 163 VC4_REG32(VC4_HDMI_CEC_RX_DATA_2), 164 VC4_REG32(VC4_HDMI_CEC_RX_DATA_3), 165 VC4_REG32(VC4_HDMI_CEC_RX_DATA_4), 166 VC4_REG32(VC4_HDMI_CEC_TX_DATA_1), 167 VC4_REG32(VC4_HDMI_CEC_TX_DATA_2), 168 VC4_REG32(VC4_HDMI_CEC_TX_DATA_3), 169 VC4_REG32(VC4_HDMI_CEC_TX_DATA_4), 170 }; 171 172 static const struct debugfs_reg32 hd_regs[] = { 173 VC4_REG32(VC4_HD_M_CTL), 174 VC4_REG32(VC4_HD_MAI_CTL), 175 VC4_REG32(VC4_HD_MAI_THR), 176 VC4_REG32(VC4_HD_MAI_FMT), 177 VC4_REG32(VC4_HD_MAI_SMP), 178 VC4_REG32(VC4_HD_VID_CTL), 179 VC4_REG32(VC4_HD_CSC_CTL), 180 VC4_REG32(VC4_HD_FRAME_COUNT), 181 }; 182 183 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 184 { 185 struct drm_info_node *node = (struct drm_info_node *)m->private; 186 struct drm_device *dev = node->minor->dev; 187 struct vc4_dev *vc4 = to_vc4_dev(dev); 188 struct vc4_hdmi *hdmi = vc4->hdmi; 189 struct drm_printer p = drm_seq_file_printer(m); 190 191 drm_print_regset32(&p, &hdmi->hdmi_regset); 192 drm_print_regset32(&p, &hdmi->hd_regset); 193 194 return 0; 195 } 196 197 static enum drm_connector_status 198 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 199 { 200 struct drm_device *dev = connector->dev; 201 struct vc4_dev *vc4 = to_vc4_dev(dev); 202 203 if (vc4->hdmi->hpd_gpio) { 204 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 205 vc4->hdmi->hpd_active_low) 206 return connector_status_connected; 207 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 208 return connector_status_disconnected; 209 } 210 211 if (drm_probe_ddc(vc4->hdmi->ddc)) 212 return connector_status_connected; 213 214 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 215 return connector_status_connected; 216 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 217 return connector_status_disconnected; 218 } 219 220 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 221 { 222 drm_connector_unregister(connector); 223 drm_connector_cleanup(connector); 224 } 225 226 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 227 { 228 struct vc4_hdmi_connector *vc4_connector = 229 to_vc4_hdmi_connector(connector); 230 struct drm_encoder *encoder = vc4_connector->encoder; 231 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 232 struct drm_device *dev = connector->dev; 233 struct vc4_dev *vc4 = to_vc4_dev(dev); 234 int ret = 0; 235 struct edid *edid; 236 237 edid = drm_get_edid(connector, vc4->hdmi->ddc); 238 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid); 239 if (!edid) 240 return -ENODEV; 241 242 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 243 244 drm_connector_update_edid_property(connector, edid); 245 ret = drm_add_edid_modes(connector, edid); 246 kfree(edid); 247 248 return ret; 249 } 250 251 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 252 { 253 drm_atomic_helper_connector_reset(connector); 254 drm_atomic_helper_connector_tv_reset(connector); 255 } 256 257 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 258 .detect = vc4_hdmi_connector_detect, 259 .fill_modes = drm_helper_probe_single_connector_modes, 260 .destroy = vc4_hdmi_connector_destroy, 261 .reset = vc4_hdmi_connector_reset, 262 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 263 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 264 }; 265 266 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 267 .get_modes = vc4_hdmi_connector_get_modes, 268 }; 269 270 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 271 struct drm_encoder *encoder, 272 struct i2c_adapter *ddc) 273 { 274 struct drm_connector *connector; 275 struct vc4_hdmi_connector *hdmi_connector; 276 int ret; 277 278 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 279 GFP_KERNEL); 280 if (!hdmi_connector) 281 return ERR_PTR(-ENOMEM); 282 connector = &hdmi_connector->base; 283 284 hdmi_connector->encoder = encoder; 285 286 drm_connector_init_with_ddc(dev, connector, 287 &vc4_hdmi_connector_funcs, 288 DRM_MODE_CONNECTOR_HDMIA, 289 ddc); 290 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 291 292 /* Create and attach TV margin props to this connector. */ 293 ret = drm_mode_create_tv_margin_properties(dev); 294 if (ret) 295 return ERR_PTR(ret); 296 297 drm_connector_attach_tv_margin_properties(connector); 298 299 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 300 DRM_CONNECTOR_POLL_DISCONNECT); 301 302 connector->interlace_allowed = 1; 303 connector->doublescan_allowed = 0; 304 305 drm_connector_attach_encoder(connector, encoder); 306 307 return connector; 308 } 309 310 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 311 enum hdmi_infoframe_type type) 312 { 313 struct drm_device *dev = encoder->dev; 314 struct vc4_dev *vc4 = to_vc4_dev(dev); 315 u32 packet_id = type - 0x80; 316 317 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 318 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 319 320 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 321 BIT(packet_id)), 100); 322 } 323 324 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 325 union hdmi_infoframe *frame) 326 { 327 struct drm_device *dev = encoder->dev; 328 struct vc4_dev *vc4 = to_vc4_dev(dev); 329 u32 packet_id = frame->any.type - 0x80; 330 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 331 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 332 ssize_t len, i; 333 int ret; 334 335 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 336 VC4_HDMI_RAM_PACKET_ENABLE), 337 "Packet RAM has to be on to store the packet."); 338 339 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 340 if (len < 0) 341 return; 342 343 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 344 if (ret) { 345 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 346 return; 347 } 348 349 for (i = 0; i < len; i += 7) { 350 HDMI_WRITE(packet_reg, 351 buffer[i + 0] << 0 | 352 buffer[i + 1] << 8 | 353 buffer[i + 2] << 16); 354 packet_reg += 4; 355 356 HDMI_WRITE(packet_reg, 357 buffer[i + 3] << 0 | 358 buffer[i + 4] << 8 | 359 buffer[i + 5] << 16 | 360 buffer[i + 6] << 24); 361 packet_reg += 4; 362 } 363 364 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 365 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 366 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 367 BIT(packet_id)), 100); 368 if (ret) 369 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 370 } 371 372 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 373 { 374 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 375 struct vc4_dev *vc4 = encoder->dev->dev_private; 376 struct vc4_hdmi *hdmi = vc4->hdmi; 377 struct drm_connector_state *cstate = hdmi->connector->state; 378 struct drm_crtc *crtc = encoder->crtc; 379 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 380 union hdmi_infoframe frame; 381 int ret; 382 383 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 384 hdmi->connector, mode); 385 if (ret < 0) { 386 DRM_ERROR("couldn't fill AVI infoframe\n"); 387 return; 388 } 389 390 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 391 hdmi->connector, mode, 392 vc4_encoder->limited_rgb_range ? 393 HDMI_QUANTIZATION_RANGE_LIMITED : 394 HDMI_QUANTIZATION_RANGE_FULL); 395 396 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 397 398 vc4_hdmi_write_infoframe(encoder, &frame); 399 } 400 401 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 402 { 403 union hdmi_infoframe frame; 404 int ret; 405 406 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 407 if (ret < 0) { 408 DRM_ERROR("couldn't fill SPD infoframe\n"); 409 return; 410 } 411 412 frame.spd.sdi = HDMI_SPD_SDI_PC; 413 414 vc4_hdmi_write_infoframe(encoder, &frame); 415 } 416 417 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 418 { 419 struct drm_device *drm = encoder->dev; 420 struct vc4_dev *vc4 = drm->dev_private; 421 struct vc4_hdmi *hdmi = vc4->hdmi; 422 union hdmi_infoframe frame; 423 int ret; 424 425 ret = hdmi_audio_infoframe_init(&frame.audio); 426 427 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 428 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 429 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 430 frame.audio.channels = hdmi->audio.channels; 431 432 vc4_hdmi_write_infoframe(encoder, &frame); 433 } 434 435 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 436 { 437 vc4_hdmi_set_avi_infoframe(encoder); 438 vc4_hdmi_set_spd_infoframe(encoder); 439 } 440 441 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 442 { 443 struct drm_device *dev = encoder->dev; 444 struct vc4_dev *vc4 = to_vc4_dev(dev); 445 struct vc4_hdmi *hdmi = vc4->hdmi; 446 int ret; 447 448 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 449 450 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 451 HD_WRITE(VC4_HD_VID_CTL, 452 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 453 454 clk_disable_unprepare(hdmi->pixel_clock); 455 456 ret = pm_runtime_put(&hdmi->pdev->dev); 457 if (ret < 0) 458 DRM_ERROR("Failed to release power domain: %d\n", ret); 459 } 460 461 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 462 { 463 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 464 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 465 struct drm_device *dev = encoder->dev; 466 struct vc4_dev *vc4 = to_vc4_dev(dev); 467 struct vc4_hdmi *hdmi = vc4->hdmi; 468 bool debug_dump_regs = false; 469 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 470 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 471 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 472 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 473 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 474 VC4_HDMI_VERTA_VSP) | 475 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 476 VC4_HDMI_VERTA_VFP) | 477 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 478 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 479 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 480 VC4_HDMI_VERTB_VBP)); 481 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 482 VC4_SET_FIELD(mode->crtc_vtotal - 483 mode->crtc_vsync_end - 484 interlaced, 485 VC4_HDMI_VERTB_VBP)); 486 u32 csc_ctl; 487 int ret; 488 489 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 490 if (ret < 0) { 491 DRM_ERROR("Failed to retain power domain: %d\n", ret); 492 return; 493 } 494 495 ret = clk_set_rate(hdmi->pixel_clock, 496 mode->clock * 1000 * 497 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 498 if (ret) { 499 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 500 return; 501 } 502 503 ret = clk_prepare_enable(hdmi->pixel_clock); 504 if (ret) { 505 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 506 return; 507 } 508 509 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 510 VC4_HDMI_SW_RESET_HDMI | 511 VC4_HDMI_SW_RESET_FORMAT_DETECT); 512 513 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 514 515 /* PHY should be in reset, like 516 * vc4_hdmi_encoder_disable() does. 517 */ 518 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 519 520 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 521 522 if (debug_dump_regs) { 523 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 524 525 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n"); 526 drm_print_regset32(&p, &hdmi->hdmi_regset); 527 drm_print_regset32(&p, &hdmi->hd_regset); 528 } 529 530 HD_WRITE(VC4_HD_VID_CTL, 0); 531 532 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 533 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 534 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 535 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 536 537 HDMI_WRITE(VC4_HDMI_HORZA, 538 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 539 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 540 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 541 VC4_HDMI_HORZA_HAP)); 542 543 HDMI_WRITE(VC4_HDMI_HORZB, 544 VC4_SET_FIELD((mode->htotal - 545 mode->hsync_end) * pixel_rep, 546 VC4_HDMI_HORZB_HBP) | 547 VC4_SET_FIELD((mode->hsync_end - 548 mode->hsync_start) * pixel_rep, 549 VC4_HDMI_HORZB_HSP) | 550 VC4_SET_FIELD((mode->hsync_start - 551 mode->hdisplay) * pixel_rep, 552 VC4_HDMI_HORZB_HFP)); 553 554 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 555 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 556 557 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 558 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 559 560 HD_WRITE(VC4_HD_VID_CTL, 561 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 562 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 563 564 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 565 VC4_HD_CSC_CTL_ORDER); 566 567 if (vc4_encoder->hdmi_monitor && 568 drm_default_rgb_quant_range(mode) == 569 HDMI_QUANTIZATION_RANGE_LIMITED) { 570 /* CEA VICs other than #1 requre limited range RGB 571 * output unless overridden by an AVI infoframe. 572 * Apply a colorspace conversion to squash 0-255 down 573 * to 16-235. The matrix here is: 574 * 575 * [ 0 0 0.8594 16] 576 * [ 0 0.8594 0 16] 577 * [ 0.8594 0 0 16] 578 * [ 0 0 0 1] 579 */ 580 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 581 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 582 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 583 VC4_HD_CSC_CTL_MODE); 584 585 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 586 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 587 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 588 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 589 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 590 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 591 vc4_encoder->limited_rgb_range = true; 592 } else { 593 vc4_encoder->limited_rgb_range = false; 594 } 595 596 /* The RGB order applies even when CSC is disabled. */ 597 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 598 599 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 600 601 if (debug_dump_regs) { 602 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 603 604 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n"); 605 drm_print_regset32(&p, &hdmi->hdmi_regset); 606 drm_print_regset32(&p, &hdmi->hd_regset); 607 } 608 609 HD_WRITE(VC4_HD_VID_CTL, 610 HD_READ(VC4_HD_VID_CTL) | 611 VC4_HD_VID_CTL_ENABLE | 612 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 613 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 614 615 if (vc4_encoder->hdmi_monitor) { 616 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 617 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 618 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 619 620 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 621 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 622 WARN_ONCE(ret, "Timeout waiting for " 623 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 624 } else { 625 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 626 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 627 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 628 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 629 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 630 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 631 632 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 633 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 634 WARN_ONCE(ret, "Timeout waiting for " 635 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 636 } 637 638 if (vc4_encoder->hdmi_monitor) { 639 u32 drift; 640 641 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 642 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 643 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 644 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 645 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 646 647 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 648 VC4_HDMI_RAM_PACKET_ENABLE); 649 650 vc4_hdmi_set_infoframes(encoder); 651 652 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 653 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 654 655 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 656 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 657 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 658 drift | VC4_HDMI_FIFO_CTL_RECENTER); 659 usleep_range(1000, 1100); 660 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 661 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 662 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 663 drift | VC4_HDMI_FIFO_CTL_RECENTER); 664 665 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 666 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 667 WARN_ONCE(ret, "Timeout waiting for " 668 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 669 } 670 } 671 672 static enum drm_mode_status 673 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc, 674 const struct drm_display_mode *mode) 675 { 676 /* 677 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 678 * be faster than pixel clock, infinitesimally faster, tested in 679 * simulation. Otherwise, exact value is unimportant for HDMI 680 * operation." This conflicts with bcm2835's vc4 documentation, which 681 * states HSM's clock has to be at least 108% of the pixel clock. 682 * 683 * Real life tests reveal that vc4's firmware statement holds up, and 684 * users are able to use pixel clocks closer to HSM's, namely for 685 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 686 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 687 * 162MHz. 688 * 689 * Additionally, the AXI clock needs to be at least 25% of 690 * pixel clock, but HSM ends up being the limiting factor. 691 */ 692 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 101 / 100)) 693 return MODE_CLOCK_HIGH; 694 695 return MODE_OK; 696 } 697 698 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 699 .mode_valid = vc4_hdmi_encoder_mode_valid, 700 .disable = vc4_hdmi_encoder_disable, 701 .enable = vc4_hdmi_encoder_enable, 702 }; 703 704 /* HDMI audio codec callbacks */ 705 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 706 { 707 struct drm_device *drm = hdmi->encoder->dev; 708 struct vc4_dev *vc4 = to_vc4_dev(drm); 709 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 710 unsigned long n, m; 711 712 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 713 VC4_HD_MAI_SMP_N_MASK >> 714 VC4_HD_MAI_SMP_N_SHIFT, 715 (VC4_HD_MAI_SMP_M_MASK >> 716 VC4_HD_MAI_SMP_M_SHIFT) + 1, 717 &n, &m); 718 719 HD_WRITE(VC4_HD_MAI_SMP, 720 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 721 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 722 } 723 724 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 725 { 726 struct drm_encoder *encoder = hdmi->encoder; 727 struct drm_crtc *crtc = encoder->crtc; 728 struct drm_device *drm = encoder->dev; 729 struct vc4_dev *vc4 = to_vc4_dev(drm); 730 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 731 u32 samplerate = hdmi->audio.samplerate; 732 u32 n, cts; 733 u64 tmp; 734 735 n = 128 * samplerate / 1000; 736 tmp = (u64)(mode->clock * 1000) * n; 737 do_div(tmp, 128 * samplerate); 738 cts = tmp; 739 740 HDMI_WRITE(VC4_HDMI_CRP_CFG, 741 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 742 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 743 744 /* 745 * We could get slightly more accurate clocks in some cases by 746 * providing a CTS_1 value. The two CTS values are alternated 747 * between based on the period fields 748 */ 749 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 750 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 751 } 752 753 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 754 { 755 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 756 757 return snd_soc_card_get_drvdata(card); 758 } 759 760 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 761 struct snd_soc_dai *dai) 762 { 763 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 764 struct drm_encoder *encoder = hdmi->encoder; 765 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 766 int ret; 767 768 if (hdmi->audio.substream && hdmi->audio.substream != substream) 769 return -EINVAL; 770 771 hdmi->audio.substream = substream; 772 773 /* 774 * If the HDMI encoder hasn't probed, or the encoder is 775 * currently in DVI mode, treat the codec dai as missing. 776 */ 777 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 778 VC4_HDMI_RAM_PACKET_ENABLE)) 779 return -ENODEV; 780 781 ret = snd_pcm_hw_constraint_eld(substream->runtime, 782 hdmi->connector->eld); 783 if (ret) 784 return ret; 785 786 return 0; 787 } 788 789 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 790 { 791 return 0; 792 } 793 794 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 795 { 796 struct drm_encoder *encoder = hdmi->encoder; 797 struct drm_device *drm = encoder->dev; 798 struct device *dev = &hdmi->pdev->dev; 799 struct vc4_dev *vc4 = to_vc4_dev(drm); 800 int ret; 801 802 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 803 if (ret) 804 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 805 806 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 807 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 808 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 809 } 810 811 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 812 struct snd_soc_dai *dai) 813 { 814 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 815 816 if (substream != hdmi->audio.substream) 817 return; 818 819 vc4_hdmi_audio_reset(hdmi); 820 821 hdmi->audio.substream = NULL; 822 } 823 824 /* HDMI audio codec callbacks */ 825 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 826 struct snd_pcm_hw_params *params, 827 struct snd_soc_dai *dai) 828 { 829 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 830 struct drm_encoder *encoder = hdmi->encoder; 831 struct drm_device *drm = encoder->dev; 832 struct device *dev = &hdmi->pdev->dev; 833 struct vc4_dev *vc4 = to_vc4_dev(drm); 834 u32 audio_packet_config, channel_mask; 835 u32 channel_map, i; 836 837 if (substream != hdmi->audio.substream) 838 return -EINVAL; 839 840 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 841 params_rate(params), params_width(params), 842 params_channels(params)); 843 844 hdmi->audio.channels = params_channels(params); 845 hdmi->audio.samplerate = params_rate(params); 846 847 HD_WRITE(VC4_HD_MAI_CTL, 848 VC4_HD_MAI_CTL_RESET | 849 VC4_HD_MAI_CTL_FLUSH | 850 VC4_HD_MAI_CTL_DLATE | 851 VC4_HD_MAI_CTL_ERRORE | 852 VC4_HD_MAI_CTL_ERRORF); 853 854 vc4_hdmi_audio_set_mai_clock(hdmi); 855 856 audio_packet_config = 857 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 858 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 859 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 860 861 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 862 audio_packet_config |= VC4_SET_FIELD(channel_mask, 863 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 864 865 /* Set the MAI threshold. This logic mimics the firmware's. */ 866 if (hdmi->audio.samplerate > 96000) { 867 HD_WRITE(VC4_HD_MAI_THR, 868 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 869 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 870 } else if (hdmi->audio.samplerate > 48000) { 871 HD_WRITE(VC4_HD_MAI_THR, 872 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 873 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 874 } else { 875 HD_WRITE(VC4_HD_MAI_THR, 876 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 877 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 878 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 879 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 880 } 881 882 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 883 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 884 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 885 886 channel_map = 0; 887 for (i = 0; i < 8; i++) { 888 if (channel_mask & BIT(i)) 889 channel_map |= i << (3 * i); 890 } 891 892 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 893 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 894 vc4_hdmi_set_n_cts(hdmi); 895 896 return 0; 897 } 898 899 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 900 struct snd_soc_dai *dai) 901 { 902 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 903 struct drm_encoder *encoder = hdmi->encoder; 904 struct drm_device *drm = encoder->dev; 905 struct vc4_dev *vc4 = to_vc4_dev(drm); 906 907 switch (cmd) { 908 case SNDRV_PCM_TRIGGER_START: 909 vc4_hdmi_set_audio_infoframe(encoder); 910 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 911 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 912 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 913 HD_WRITE(VC4_HD_MAI_CTL, 914 VC4_SET_FIELD(hdmi->audio.channels, 915 VC4_HD_MAI_CTL_CHNUM) | 916 VC4_HD_MAI_CTL_ENABLE); 917 break; 918 case SNDRV_PCM_TRIGGER_STOP: 919 HD_WRITE(VC4_HD_MAI_CTL, 920 VC4_HD_MAI_CTL_DLATE | 921 VC4_HD_MAI_CTL_ERRORE | 922 VC4_HD_MAI_CTL_ERRORF); 923 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 924 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 925 VC4_HDMI_TX_PHY_RNG_PWRDN); 926 break; 927 default: 928 break; 929 } 930 931 return 0; 932 } 933 934 static inline struct vc4_hdmi * 935 snd_component_to_hdmi(struct snd_soc_component *component) 936 { 937 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 938 939 return snd_soc_card_get_drvdata(card); 940 } 941 942 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 943 struct snd_ctl_elem_info *uinfo) 944 { 945 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 946 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 947 948 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 949 uinfo->count = sizeof(hdmi->connector->eld); 950 951 return 0; 952 } 953 954 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 955 struct snd_ctl_elem_value *ucontrol) 956 { 957 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 958 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 959 960 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 961 sizeof(hdmi->connector->eld)); 962 963 return 0; 964 } 965 966 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 967 { 968 .access = SNDRV_CTL_ELEM_ACCESS_READ | 969 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 970 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 971 .name = "ELD", 972 .info = vc4_hdmi_audio_eld_ctl_info, 973 .get = vc4_hdmi_audio_eld_ctl_get, 974 }, 975 }; 976 977 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 978 SND_SOC_DAPM_OUTPUT("TX"), 979 }; 980 981 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 982 { "TX", NULL, "Playback" }, 983 }; 984 985 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 986 .controls = vc4_hdmi_audio_controls, 987 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 988 .dapm_widgets = vc4_hdmi_audio_widgets, 989 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 990 .dapm_routes = vc4_hdmi_audio_routes, 991 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 992 .idle_bias_on = 1, 993 .use_pmdown_time = 1, 994 .endianness = 1, 995 .non_legacy_dai_naming = 1, 996 }; 997 998 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 999 .startup = vc4_hdmi_audio_startup, 1000 .shutdown = vc4_hdmi_audio_shutdown, 1001 .hw_params = vc4_hdmi_audio_hw_params, 1002 .set_fmt = vc4_hdmi_audio_set_fmt, 1003 .trigger = vc4_hdmi_audio_trigger, 1004 }; 1005 1006 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1007 .name = "vc4-hdmi-hifi", 1008 .playback = { 1009 .stream_name = "Playback", 1010 .channels_min = 2, 1011 .channels_max = 8, 1012 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1013 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1014 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1015 SNDRV_PCM_RATE_192000, 1016 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1017 }, 1018 }; 1019 1020 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1021 .name = "vc4-hdmi-cpu-dai-component", 1022 }; 1023 1024 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1025 { 1026 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1027 1028 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1029 1030 return 0; 1031 } 1032 1033 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1034 .name = "vc4-hdmi-cpu-dai", 1035 .probe = vc4_hdmi_audio_cpu_dai_probe, 1036 .playback = { 1037 .stream_name = "Playback", 1038 .channels_min = 1, 1039 .channels_max = 8, 1040 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1041 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1042 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1043 SNDRV_PCM_RATE_192000, 1044 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1045 }, 1046 .ops = &vc4_hdmi_audio_dai_ops, 1047 }; 1048 1049 static const struct snd_dmaengine_pcm_config pcm_conf = { 1050 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1051 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1052 }; 1053 1054 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1055 { 1056 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1057 struct snd_soc_card *card = &hdmi->audio.card; 1058 struct device *dev = &hdmi->pdev->dev; 1059 const __be32 *addr; 1060 int ret; 1061 1062 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1063 dev_warn(dev, 1064 "'dmas' DT property is missing, no HDMI audio\n"); 1065 return 0; 1066 } 1067 1068 /* 1069 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1070 * the bus address specified in the DT, because the physical address 1071 * (the one returned by platform_get_resource()) is not appropriate 1072 * for DMA transfers. 1073 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1074 */ 1075 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1076 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1077 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1078 hdmi->audio.dma_data.maxburst = 2; 1079 1080 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1081 if (ret) { 1082 dev_err(dev, "Could not register PCM component: %d\n", ret); 1083 return ret; 1084 } 1085 1086 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1087 &vc4_hdmi_audio_cpu_dai_drv, 1); 1088 if (ret) { 1089 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1090 return ret; 1091 } 1092 1093 /* register component and codec dai */ 1094 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1095 &vc4_hdmi_audio_codec_dai_drv, 1); 1096 if (ret) { 1097 dev_err(dev, "Could not register component: %d\n", ret); 1098 return ret; 1099 } 1100 1101 dai_link->cpus = &hdmi->audio.cpu; 1102 dai_link->codecs = &hdmi->audio.codec; 1103 dai_link->platforms = &hdmi->audio.platform; 1104 1105 dai_link->num_cpus = 1; 1106 dai_link->num_codecs = 1; 1107 dai_link->num_platforms = 1; 1108 1109 dai_link->name = "MAI"; 1110 dai_link->stream_name = "MAI PCM"; 1111 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1112 dai_link->cpus->dai_name = dev_name(dev); 1113 dai_link->codecs->name = dev_name(dev); 1114 dai_link->platforms->name = dev_name(dev); 1115 1116 card->dai_link = dai_link; 1117 card->num_links = 1; 1118 card->name = "vc4-hdmi"; 1119 card->dev = dev; 1120 1121 /* 1122 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1123 * stores a pointer to the snd card object in dev->driver_data. This 1124 * means we cannot use it for something else. The hdmi back-pointer is 1125 * now stored in card->drvdata and should be retrieved with 1126 * snd_soc_card_get_drvdata() if needed. 1127 */ 1128 snd_soc_card_set_drvdata(card, hdmi); 1129 ret = devm_snd_soc_register_card(dev, card); 1130 if (ret) 1131 dev_err(dev, "Could not register sound card: %d\n", ret); 1132 1133 return ret; 1134 1135 } 1136 1137 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1138 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1139 { 1140 struct vc4_dev *vc4 = priv; 1141 struct vc4_hdmi *hdmi = vc4->hdmi; 1142 1143 if (hdmi->cec_irq_was_rx) { 1144 if (hdmi->cec_rx_msg.len) 1145 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg); 1146 } else if (hdmi->cec_tx_ok) { 1147 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK, 1148 0, 0, 0, 0); 1149 } else { 1150 /* 1151 * This CEC implementation makes 1 retry, so if we 1152 * get a NACK, then that means it made 2 attempts. 1153 */ 1154 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK, 1155 0, 2, 0, 0); 1156 } 1157 return IRQ_HANDLED; 1158 } 1159 1160 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) 1161 { 1162 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg; 1163 unsigned int i; 1164 1165 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1166 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1167 for (i = 0; i < msg->len; i += 4) { 1168 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); 1169 1170 msg->msg[i] = val & 0xff; 1171 msg->msg[i + 1] = (val >> 8) & 0xff; 1172 msg->msg[i + 2] = (val >> 16) & 0xff; 1173 msg->msg[i + 3] = (val >> 24) & 0xff; 1174 } 1175 } 1176 1177 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1178 { 1179 struct vc4_dev *vc4 = priv; 1180 struct vc4_hdmi *hdmi = vc4->hdmi; 1181 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); 1182 u32 cntrl1, cntrl5; 1183 1184 if (!(stat & VC4_HDMI_CPU_CEC)) 1185 return IRQ_NONE; 1186 hdmi->cec_rx_msg.len = 0; 1187 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1188 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1189 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1190 if (hdmi->cec_irq_was_rx) { 1191 vc4_cec_read_msg(vc4, cntrl1); 1192 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1193 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1194 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1195 } else { 1196 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1197 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1198 } 1199 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1200 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1201 1202 return IRQ_WAKE_THREAD; 1203 } 1204 1205 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1206 { 1207 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1208 /* clock period in microseconds */ 1209 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1210 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1211 1212 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1213 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1214 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1215 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1216 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1217 1218 if (enable) { 1219 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1220 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1221 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); 1222 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, 1223 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1224 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1225 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1226 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1227 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1228 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, 1229 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1230 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1231 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1232 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1233 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, 1234 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1235 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1236 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1237 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1238 1239 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1240 } else { 1241 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1242 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1243 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1244 } 1245 return 0; 1246 } 1247 1248 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1249 { 1250 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1251 1252 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, 1253 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1254 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1255 return 0; 1256 } 1257 1258 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1259 u32 signal_free_time, struct cec_msg *msg) 1260 { 1261 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1262 u32 val; 1263 unsigned int i; 1264 1265 for (i = 0; i < msg->len; i += 4) 1266 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, 1267 (msg->msg[i]) | 1268 (msg->msg[i + 1] << 8) | 1269 (msg->msg[i + 2] << 16) | 1270 (msg->msg[i + 3] << 24)); 1271 1272 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1273 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1274 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1275 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1276 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1277 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1278 1279 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1280 return 0; 1281 } 1282 1283 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1284 .adap_enable = vc4_hdmi_cec_adap_enable, 1285 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1286 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1287 }; 1288 #endif 1289 1290 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1291 { 1292 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1293 struct cec_connector_info conn_info; 1294 #endif 1295 struct platform_device *pdev = to_platform_device(dev); 1296 struct drm_device *drm = dev_get_drvdata(master); 1297 struct vc4_dev *vc4 = drm->dev_private; 1298 struct vc4_hdmi *hdmi; 1299 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1300 struct device_node *ddc_node; 1301 u32 value; 1302 int ret; 1303 1304 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1305 if (!hdmi) 1306 return -ENOMEM; 1307 1308 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1309 GFP_KERNEL); 1310 if (!vc4_hdmi_encoder) 1311 return -ENOMEM; 1312 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1313 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1314 1315 hdmi->pdev = pdev; 1316 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1317 if (IS_ERR(hdmi->hdmicore_regs)) 1318 return PTR_ERR(hdmi->hdmicore_regs); 1319 1320 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1321 if (IS_ERR(hdmi->hd_regs)) 1322 return PTR_ERR(hdmi->hd_regs); 1323 1324 hdmi->hdmi_regset.base = hdmi->hdmicore_regs; 1325 hdmi->hdmi_regset.regs = hdmi_regs; 1326 hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs); 1327 hdmi->hd_regset.base = hdmi->hd_regs; 1328 hdmi->hd_regset.regs = hd_regs; 1329 hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs); 1330 1331 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1332 if (IS_ERR(hdmi->pixel_clock)) { 1333 DRM_ERROR("Failed to get pixel clock\n"); 1334 return PTR_ERR(hdmi->pixel_clock); 1335 } 1336 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1337 if (IS_ERR(hdmi->hsm_clock)) { 1338 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1339 return PTR_ERR(hdmi->hsm_clock); 1340 } 1341 1342 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1343 if (!ddc_node) { 1344 DRM_ERROR("Failed to find ddc node in device tree\n"); 1345 return -ENODEV; 1346 } 1347 1348 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1349 of_node_put(ddc_node); 1350 if (!hdmi->ddc) { 1351 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1352 return -EPROBE_DEFER; 1353 } 1354 1355 /* This is the rate that is set by the firmware. The number 1356 * needs to be a bit higher than the pixel clock rate 1357 * (generally 148.5Mhz). 1358 */ 1359 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ); 1360 if (ret) { 1361 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1362 goto err_put_i2c; 1363 } 1364 1365 ret = clk_prepare_enable(hdmi->hsm_clock); 1366 if (ret) { 1367 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1368 ret); 1369 goto err_put_i2c; 1370 } 1371 1372 /* Only use the GPIO HPD pin if present in the DT, otherwise 1373 * we'll use the HDMI core's register. 1374 */ 1375 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1376 enum of_gpio_flags hpd_gpio_flags; 1377 1378 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1379 "hpd-gpios", 0, 1380 &hpd_gpio_flags); 1381 if (hdmi->hpd_gpio < 0) { 1382 ret = hdmi->hpd_gpio; 1383 goto err_unprepare_hsm; 1384 } 1385 1386 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1387 } 1388 1389 vc4->hdmi = hdmi; 1390 1391 /* HDMI core must be enabled. */ 1392 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1393 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1394 udelay(1); 1395 HD_WRITE(VC4_HD_M_CTL, 0); 1396 1397 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1398 } 1399 pm_runtime_enable(dev); 1400 1401 drm_simple_encoder_init(drm, hdmi->encoder, DRM_MODE_ENCODER_TMDS); 1402 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1403 1404 hdmi->connector = 1405 vc4_hdmi_connector_init(drm, hdmi->encoder, hdmi->ddc); 1406 if (IS_ERR(hdmi->connector)) { 1407 ret = PTR_ERR(hdmi->connector); 1408 goto err_destroy_encoder; 1409 } 1410 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1411 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1412 vc4, "vc4", 1413 CEC_CAP_DEFAULTS | 1414 CEC_CAP_CONNECTOR_INFO, 1); 1415 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 1416 if (ret < 0) 1417 goto err_destroy_conn; 1418 1419 cec_fill_conn_info_from_drm(&conn_info, hdmi->connector); 1420 cec_s_conn_info(hdmi->cec_adap, &conn_info); 1421 1422 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); 1423 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1424 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1425 /* 1426 * Set the logical address to Unregistered and set the clock 1427 * divider: the hsm_clock rate and this divider setting will 1428 * give a 40 kHz CEC clock. 1429 */ 1430 value |= VC4_HDMI_CEC_ADDR_MASK | 1431 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1432 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); 1433 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1434 vc4_cec_irq_handler, 1435 vc4_cec_irq_handler_thread, 0, 1436 "vc4 hdmi cec", vc4); 1437 if (ret) 1438 goto err_delete_cec_adap; 1439 ret = cec_register_adapter(hdmi->cec_adap, dev); 1440 if (ret < 0) 1441 goto err_delete_cec_adap; 1442 #endif 1443 1444 ret = vc4_hdmi_audio_init(hdmi); 1445 if (ret) 1446 goto err_destroy_encoder; 1447 1448 vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi); 1449 1450 return 0; 1451 1452 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1453 err_delete_cec_adap: 1454 cec_delete_adapter(hdmi->cec_adap); 1455 err_destroy_conn: 1456 vc4_hdmi_connector_destroy(hdmi->connector); 1457 #endif 1458 err_destroy_encoder: 1459 drm_encoder_cleanup(hdmi->encoder); 1460 err_unprepare_hsm: 1461 clk_disable_unprepare(hdmi->hsm_clock); 1462 pm_runtime_disable(dev); 1463 err_put_i2c: 1464 put_device(&hdmi->ddc->dev); 1465 1466 return ret; 1467 } 1468 1469 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1470 void *data) 1471 { 1472 struct drm_device *drm = dev_get_drvdata(master); 1473 struct vc4_dev *vc4 = drm->dev_private; 1474 struct vc4_hdmi *hdmi = vc4->hdmi; 1475 1476 cec_unregister_adapter(hdmi->cec_adap); 1477 vc4_hdmi_connector_destroy(hdmi->connector); 1478 drm_encoder_cleanup(hdmi->encoder); 1479 1480 clk_disable_unprepare(hdmi->hsm_clock); 1481 pm_runtime_disable(dev); 1482 1483 put_device(&hdmi->ddc->dev); 1484 1485 vc4->hdmi = NULL; 1486 } 1487 1488 static const struct component_ops vc4_hdmi_ops = { 1489 .bind = vc4_hdmi_bind, 1490 .unbind = vc4_hdmi_unbind, 1491 }; 1492 1493 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1494 { 1495 return component_add(&pdev->dev, &vc4_hdmi_ops); 1496 } 1497 1498 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1499 { 1500 component_del(&pdev->dev, &vc4_hdmi_ops); 1501 return 0; 1502 } 1503 1504 static const struct of_device_id vc4_hdmi_dt_match[] = { 1505 { .compatible = "brcm,bcm2835-hdmi" }, 1506 {} 1507 }; 1508 1509 struct platform_driver vc4_hdmi_driver = { 1510 .probe = vc4_hdmi_dev_probe, 1511 .remove = vc4_hdmi_dev_remove, 1512 .driver = { 1513 .name = "vc4_hdmi", 1514 .of_match_table = vc4_hdmi_dt_match, 1515 }, 1516 }; 1517