1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #ifndef _QLCNIC_H_ 9 #define _QLCNIC_H_ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/ioport.h> 15 #include <linux/pci.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/ip.h> 19 #include <linux/in.h> 20 #include <linux/tcp.h> 21 #include <linux/skbuff.h> 22 #include <linux/firmware.h> 23 #include <linux/ethtool.h> 24 #include <linux/mii.h> 25 #include <linux/timer.h> 26 #include <linux/irq.h> 27 #include <linux/vmalloc.h> 28 #include <linux/io.h> 29 #include <asm/byteorder.h> 30 #include <linux/bitops.h> 31 #include <linux/if_vlan.h> 32 33 #include "qlcnic_hdr.h" 34 #include "qlcnic_hw.h" 35 #include "qlcnic_83xx_hw.h" 36 #include "qlcnic_dcb.h" 37 38 #define _QLCNIC_LINUX_MAJOR 5 39 #define _QLCNIC_LINUX_MINOR 3 40 #define _QLCNIC_LINUX_SUBVERSION 66 41 #define QLCNIC_LINUX_VERSIONID "5.3.66" 42 #define QLCNIC_DRV_IDC_VER 0x01 43 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 44 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 45 46 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 47 #define _major(v) (((v) >> 24) & 0xff) 48 #define _minor(v) (((v) >> 16) & 0xff) 49 #define _build(v) ((v) & 0xffff) 50 51 /* version in image has weird encoding: 52 * 7:0 - major 53 * 15:8 - minor 54 * 31:16 - build (little endian) 55 */ 56 #define QLCNIC_DECODE_VERSION(v) \ 57 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 58 59 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2) 60 #define QLCNIC_NUM_FLASH_SECTORS (64) 61 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) 62 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ 63 * QLCNIC_FLASH_SECTOR_SIZE) 64 65 #define RCV_DESC_RINGSIZE(rds_ring) \ 66 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 67 #define RCV_BUFF_RINGSIZE(rds_ring) \ 68 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) 69 #define STATUS_DESC_RINGSIZE(sds_ring) \ 70 (sizeof(struct status_desc) * (sds_ring)->num_desc) 71 #define TX_BUFF_RINGSIZE(tx_ring) \ 72 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) 73 #define TX_DESC_RINGSIZE(tx_ring) \ 74 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 75 76 #define QLCNIC_P3P_A0 0x50 77 #define QLCNIC_P3P_C0 0x58 78 79 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) 80 81 #define FIRST_PAGE_GROUP_START 0 82 #define FIRST_PAGE_GROUP_END 0x100000 83 84 #define P3P_MAX_MTU (9600) 85 #define P3P_MIN_MTU (68) 86 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ 87 88 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) 89 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU) 90 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 91 #define QLCNIC_LRO_BUFFER_EXTRA 2048 92 93 /* Tx defines */ 94 #define QLCNIC_MAX_FRAGS_PER_TX 14 95 #define MAX_TSO_HEADER_DESC 2 96 #define MGMT_CMD_DESC_RESV 4 97 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 98 + MGMT_CMD_DESC_RESV) 99 #define QLCNIC_MAX_TX_TIMEOUTS 2 100 101 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */ 102 #define QLCNIC_SINGLE_RING 1 103 #define QLCNIC_DEF_SDS_RINGS 4 104 #define QLCNIC_DEF_TX_RINGS 4 105 #define QLCNIC_MAX_VNIC_TX_RINGS 4 106 #define QLCNIC_MAX_VNIC_SDS_RINGS 4 107 #define QLCNIC_83XX_MINIMUM_VECTOR 3 108 #define QLCNIC_82XX_MINIMUM_VECTOR 2 109 110 enum qlcnic_queue_type { 111 QLCNIC_TX_QUEUE = 1, 112 QLCNIC_RX_QUEUE, 113 }; 114 115 /* Operational mode for driver */ 116 #define QLCNIC_VNIC_MODE 0xFF 117 #define QLCNIC_DEFAULT_MODE 0x0 118 119 /* Virtual NIC function count */ 120 #define QLC_DEFAULT_VNIC_COUNT 8 121 #define QLC_84XX_VNIC_COUNT 16 122 123 /* 124 * Following are the states of the Phantom. Phantom will set them and 125 * Host will read to check if the fields are correct. 126 */ 127 #define PHAN_INITIALIZE_FAILED 0xffff 128 #define PHAN_INITIALIZE_COMPLETE 0xff01 129 130 /* Host writes the following to notify that it has done the init-handshake */ 131 #define PHAN_INITIALIZE_ACK 0xf00f 132 #define PHAN_PEG_RCV_INITIALIZED 0xff01 133 134 #define NUM_RCV_DESC_RINGS 3 135 136 #define RCV_RING_NORMAL 0 137 #define RCV_RING_JUMBO 1 138 139 #define MIN_CMD_DESCRIPTORS 64 140 #define MIN_RCV_DESCRIPTORS 64 141 #define MIN_JUMBO_DESCRIPTORS 32 142 143 #define MAX_CMD_DESCRIPTORS 1024 144 #define MAX_RCV_DESCRIPTORS_1G 4096 145 #define MAX_RCV_DESCRIPTORS_10G 8192 146 #define MAX_RCV_DESCRIPTORS_VF 2048 147 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 148 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 149 150 #define DEFAULT_RCV_DESCRIPTORS_1G 2048 151 #define DEFAULT_RCV_DESCRIPTORS_10G 4096 152 #define DEFAULT_RCV_DESCRIPTORS_VF 1024 153 #define MAX_RDS_RINGS 2 154 155 #define get_next_index(index, length) \ 156 (((index) + 1) & ((length) - 1)) 157 158 /* 159 * Following data structures describe the descriptors that will be used. 160 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 161 * we are doing LSO (above the 1500 size packet) only. 162 */ 163 struct cmd_desc_type0 { 164 u8 tcp_hdr_offset; /* For LSO only */ 165 u8 ip_hdr_offset; /* For LSO only */ 166 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 167 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 168 169 __le64 addr_buffer2; 170 171 __le16 encap_descr; /* 15:10 offset of outer L3 header, 172 * 9:6 number of 32bit words in outer L3 header, 173 * 5 offload outer L4 checksum, 174 * 4 offload outer L3 checksum, 175 * 3 Inner L4 type, TCP=0, UDP=1, 176 * 2 Inner L3 type, IPv4=0, IPv6=1, 177 * 1 Outer L3 type,IPv4=0, IPv6=1, 178 * 0 type of encapsulation, GRE=0, VXLAN=1 179 */ 180 __le16 mss; 181 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 182 u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 183 u8 outer_hdr_length; /* Encapsulation only */ 184 u8 rsvd1; 185 186 __le64 addr_buffer3; 187 __le64 addr_buffer1; 188 189 __le16 buffer_length[4]; 190 191 __le64 addr_buffer4; 192 193 u8 eth_addr[ETH_ALEN]; 194 __le16 vlan_TCI; /* In case of encapsulation, 195 * this is for outer VLAN 196 */ 197 198 } __attribute__ ((aligned(64))); 199 200 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 201 struct rcv_desc { 202 __le16 reference_handle; 203 __le16 reserved; 204 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 205 __le64 addr_buffer; 206 } __packed; 207 208 struct status_desc { 209 __le64 status_desc_data[2]; 210 } __attribute__ ((aligned(16))); 211 212 /* UNIFIED ROMIMAGE */ 213 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 214 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 215 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 216 #define QLCNIC_UNI_DIR_SECT_FW 0x7 217 218 /*Offsets */ 219 #define QLCNIC_UNI_CHIP_REV_OFF 10 220 #define QLCNIC_UNI_FLAGS_OFF 11 221 #define QLCNIC_UNI_BIOS_VERSION_OFF 12 222 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 223 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 224 225 struct uni_table_desc{ 226 __le32 findex; 227 __le32 num_entries; 228 __le32 entry_size; 229 __le32 reserved[5]; 230 }; 231 232 struct uni_data_desc{ 233 __le32 findex; 234 __le32 size; 235 __le32 reserved[5]; 236 }; 237 238 /* Flash Defines and Structures */ 239 #define QLCNIC_FLT_LOCATION 0x3F1000 240 #define QLCNIC_FDT_LOCATION 0x3F0000 241 #define QLCNIC_B0_FW_IMAGE_REGION 0x74 242 #define QLCNIC_C0_FW_IMAGE_REGION 0x97 243 #define QLCNIC_BOOTLD_REGION 0X72 244 struct qlcnic_flt_header { 245 u16 version; 246 u16 len; 247 u16 checksum; 248 u16 reserved; 249 }; 250 251 struct qlcnic_flt_entry { 252 u8 region; 253 u8 reserved0; 254 u8 attrib; 255 u8 reserved1; 256 u32 size; 257 u32 start_addr; 258 u32 end_addr; 259 }; 260 261 /* Flash Descriptor Table */ 262 struct qlcnic_fdt { 263 u32 valid; 264 u16 ver; 265 u16 len; 266 u16 cksum; 267 u16 unused; 268 u8 model[16]; 269 u8 mfg_id; 270 u16 id; 271 u8 flag; 272 u8 erase_cmd; 273 u8 alt_erase_cmd; 274 u8 write_enable_cmd; 275 u8 write_enable_bits; 276 u8 write_statusreg_cmd; 277 u8 unprotected_sec_cmd; 278 u8 read_manuf_cmd; 279 u32 block_size; 280 u32 alt_block_size; 281 u32 flash_size; 282 u32 write_enable_data; 283 u8 readid_addr_len; 284 u8 write_disable_bits; 285 u8 read_dev_id_len; 286 u8 chip_erase_cmd; 287 u16 read_timeo; 288 u8 protected_sec_cmd; 289 u8 resvd[65]; 290 }; 291 /* Magic number to let user know flash is programmed */ 292 #define QLCNIC_BDINFO_MAGIC 0x12345678 293 294 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021 295 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022 296 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023 297 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024 298 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025 299 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026 300 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027 301 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028 302 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029 303 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a 304 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b 305 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031 306 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032 307 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080 308 309 #define QLCNIC_MSIX_TABLE_OFFSET 0x44 310 311 /* Flash memory map */ 312 #define QLCNIC_BRDCFG_START 0x4000 /* board config */ 313 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ 314 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ 315 #define QLCNIC_USER_START 0x3E8000 /* Firmware info */ 316 317 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) 318 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) 319 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) 320 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) 321 322 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) 323 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) 324 325 #define QLCNIC_FW_MIN_SIZE (0x3fffff) 326 #define QLCNIC_UNIFIED_ROMIMAGE 0 327 #define QLCNIC_FLASH_ROMIMAGE 1 328 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff 329 330 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 331 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" 332 333 extern char qlcnic_driver_name[]; 334 335 extern int qlcnic_use_msi; 336 extern int qlcnic_use_msi_x; 337 extern int qlcnic_auto_fw_reset; 338 extern int qlcnic_load_fw_file; 339 340 /* Number of status descriptors to handle per interrupt */ 341 #define MAX_STATUS_HANDLE (64) 342 343 /* 344 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This 345 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. 346 */ 347 struct qlcnic_skb_frag { 348 u64 dma; 349 u64 length; 350 }; 351 352 /* Following defines are for the state of the buffers */ 353 #define QLCNIC_BUFFER_FREE 0 354 #define QLCNIC_BUFFER_BUSY 1 355 356 /* 357 * There will be one qlcnic_buffer per skb packet. These will be 358 * used to save the dma info for pci_unmap_page() 359 */ 360 struct qlcnic_cmd_buffer { 361 struct sk_buff *skb; 362 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 363 u32 frag_count; 364 }; 365 366 /* In rx_buffer, we do not need multiple fragments as is a single buffer */ 367 struct qlcnic_rx_buffer { 368 u16 ref_handle; 369 struct sk_buff *skb; 370 struct list_head list; 371 u64 dma; 372 }; 373 374 /* Board types */ 375 #define QLCNIC_GBE 0x01 376 #define QLCNIC_XGBE 0x02 377 378 /* 379 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 380 * adjusted based on configured MTU. 381 */ 382 #define QLCNIC_INTR_COAL_TYPE_RX 1 383 #define QLCNIC_INTR_COAL_TYPE_TX 2 384 #define QLCNIC_INTR_COAL_TYPE_RX_TX 3 385 386 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3 387 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256 388 389 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64 390 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64 391 392 #define QLCNIC_INTR_DEFAULT 0x04 393 #define QLCNIC_CONFIG_INTR_COALESCE 3 394 #define QLCNIC_DEV_INFO_SIZE 2 395 396 struct qlcnic_nic_intr_coalesce { 397 u8 type; 398 u8 sts_ring_mask; 399 u16 rx_packets; 400 u16 rx_time_us; 401 u16 tx_packets; 402 u16 tx_time_us; 403 u16 flag; 404 u32 timer_out; 405 }; 406 407 struct qlcnic_83xx_dump_template_hdr { 408 u32 type; 409 u32 offset; 410 u32 size; 411 u32 cap_mask; 412 u32 num_entries; 413 u32 version; 414 u32 timestamp; 415 u32 checksum; 416 u32 drv_cap_mask; 417 u32 sys_info[3]; 418 u32 saved_state[16]; 419 u32 cap_sizes[8]; 420 u32 ocm_wnd_reg[16]; 421 u32 rsvd[]; 422 }; 423 424 struct qlcnic_82xx_dump_template_hdr { 425 u32 type; 426 u32 offset; 427 u32 size; 428 u32 cap_mask; 429 u32 num_entries; 430 u32 version; 431 u32 timestamp; 432 u32 checksum; 433 u32 drv_cap_mask; 434 u32 sys_info[3]; 435 u32 saved_state[16]; 436 u32 cap_sizes[8]; 437 u32 rsvd[7]; 438 u32 capabilities; 439 u32 rsvd1[]; 440 }; 441 442 #define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16) 443 444 struct qlcnic_fw_dump { 445 u8 clr; /* flag to indicate if dump is cleared */ 446 bool enable; /* enable/disable dump */ 447 u32 size; /* total size of the dump */ 448 u32 cap_mask; /* Current capture mask */ 449 void *data; /* dump data area */ 450 void *tmpl_hdr; 451 dma_addr_t phys_addr; 452 void *dma_buffer; 453 bool use_pex_dma; 454 /* Read only elements which are common between 82xx and 83xx 455 * template header. Update these values immediately after we read 456 * template header from Firmware 457 */ 458 u32 tmpl_hdr_size; 459 u32 version; 460 u32 num_entries; 461 u32 offset; 462 }; 463 464 /* 465 * One hardware_context{} per adapter 466 * contains interrupt info as well shared hardware info. 467 */ 468 struct qlcnic_hardware_context { 469 void __iomem *pci_base0; 470 void __iomem *ocm_win_crb; 471 472 unsigned long pci_len0; 473 474 rwlock_t crb_lock; 475 struct mutex mem_lock; 476 477 u8 revision_id; 478 u8 pci_func; 479 u8 linkup; 480 u8 loopback_state; 481 u8 beacon_state; 482 u8 has_link_events; 483 u8 fw_type; 484 u8 physical_port; 485 u8 reset_context; 486 u8 msix_supported; 487 u8 max_mac_filters; 488 u8 mc_enabled; 489 u8 max_mc_count; 490 u8 diag_test; 491 u8 num_msix; 492 u8 nic_mode; 493 int diag_cnt; 494 495 u16 max_uc_count; 496 u16 port_type; 497 u16 board_type; 498 u16 supported_type; 499 500 u32 link_speed; 501 u16 link_duplex; 502 u16 link_autoneg; 503 u16 module_type; 504 505 u16 op_mode; 506 u16 switch_mode; 507 u16 max_tx_ques; 508 u16 max_rx_ques; 509 u16 max_mtu; 510 u32 msg_enable; 511 u16 total_nic_func; 512 u16 max_pci_func; 513 u32 max_vnic_func; 514 u32 total_pci_func; 515 516 u32 capabilities; 517 u32 extra_capability[3]; 518 u32 temp; 519 u32 int_vec_bit; 520 u32 fw_hal_version; 521 u32 port_config; 522 struct qlcnic_hardware_ops *hw_ops; 523 struct qlcnic_nic_intr_coalesce coal; 524 struct qlcnic_fw_dump fw_dump; 525 struct qlcnic_fdt fdt; 526 struct qlc_83xx_reset reset; 527 struct qlc_83xx_idc idc; 528 struct qlc_83xx_fw_info *fw_info; 529 struct qlcnic_intrpt_config *intr_tbl; 530 struct qlcnic_sriov *sriov; 531 u32 *reg_tbl; 532 u32 *ext_reg_tbl; 533 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT]; 534 u32 mbox_reg[4]; 535 struct qlcnic_mailbox *mailbox; 536 u8 extend_lb_time; 537 u8 phys_port_id[ETH_ALEN]; 538 u8 lb_mode; 539 struct device *hwmon_dev; 540 u32 post_mode; 541 bool run_post; 542 }; 543 544 struct qlcnic_adapter_stats { 545 u64 xmitcalled; 546 u64 xmitfinished; 547 u64 rxdropped; 548 u64 txdropped; 549 u64 csummed; 550 u64 rx_pkts; 551 u64 lro_pkts; 552 u64 rxbytes; 553 u64 txbytes; 554 u64 lrobytes; 555 u64 lso_frames; 556 u64 encap_lso_frames; 557 u64 encap_tx_csummed; 558 u64 encap_rx_csummed; 559 u64 xmit_on; 560 u64 xmit_off; 561 u64 skb_alloc_failure; 562 u64 null_rxbuf; 563 u64 rx_dma_map_error; 564 u64 tx_dma_map_error; 565 u64 spurious_intr; 566 u64 mac_filter_limit_overrun; 567 u64 mbx_spurious_intr; 568 }; 569 570 /* 571 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 572 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 573 */ 574 struct qlcnic_host_rds_ring { 575 void __iomem *crb_rcv_producer; 576 struct rcv_desc *desc_head; 577 struct qlcnic_rx_buffer *rx_buf_arr; 578 u32 num_desc; 579 u32 producer; 580 u32 dma_size; 581 u32 skb_size; 582 u32 flags; 583 struct list_head free_list; 584 spinlock_t lock; 585 dma_addr_t phys_addr; 586 } ____cacheline_internodealigned_in_smp; 587 588 struct qlcnic_host_sds_ring { 589 u32 consumer; 590 u32 num_desc; 591 void __iomem *crb_sts_consumer; 592 593 struct qlcnic_host_tx_ring *tx_ring; 594 struct status_desc *desc_head; 595 struct qlcnic_adapter *adapter; 596 struct napi_struct napi; 597 struct list_head free_list[NUM_RCV_DESC_RINGS]; 598 599 void __iomem *crb_intr_mask; 600 int irq; 601 602 dma_addr_t phys_addr; 603 char name[IFNAMSIZ + 12]; 604 } ____cacheline_internodealigned_in_smp; 605 606 struct qlcnic_tx_queue_stats { 607 u64 xmit_on; 608 u64 xmit_off; 609 u64 xmit_called; 610 u64 xmit_finished; 611 u64 tx_bytes; 612 }; 613 614 struct qlcnic_host_tx_ring { 615 int irq; 616 void __iomem *crb_intr_mask; 617 char name[IFNAMSIZ + 12]; 618 u16 ctx_id; 619 620 u32 state; 621 u32 producer; 622 u32 sw_consumer; 623 u32 num_desc; 624 625 struct qlcnic_tx_queue_stats tx_stats; 626 627 void __iomem *crb_cmd_producer; 628 struct cmd_desc_type0 *desc_head; 629 struct qlcnic_adapter *adapter; 630 struct napi_struct napi; 631 struct qlcnic_cmd_buffer *cmd_buf_arr; 632 __le32 *hw_consumer; 633 634 dma_addr_t phys_addr; 635 dma_addr_t hw_cons_phys_addr; 636 struct netdev_queue *txq; 637 /* Lock to protect Tx descriptors cleanup */ 638 spinlock_t tx_clean_lock; 639 } ____cacheline_internodealigned_in_smp; 640 641 /* 642 * Receive context. There is one such structure per instance of the 643 * receive processing. Any state information that is relevant to 644 * the receive, and is must be in this structure. The global data may be 645 * present elsewhere. 646 */ 647 struct qlcnic_recv_context { 648 struct qlcnic_host_rds_ring *rds_rings; 649 struct qlcnic_host_sds_ring *sds_rings; 650 u32 state; 651 u16 context_id; 652 u16 virt_port; 653 }; 654 655 /* HW context creation */ 656 657 #define QLCNIC_OS_CRB_RETRY_COUNT 4000 658 659 #define QLCNIC_CDRP_CMD_BIT 0x80000000 660 661 /* 662 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared 663 * in the crb QLCNIC_CDRP_CRB_OFFSET. 664 */ 665 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) 666 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) 667 668 #define QLCNIC_CDRP_RSP_OK 0x00000001 669 #define QLCNIC_CDRP_RSP_FAIL 0x00000002 670 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 671 672 /* 673 * All commands must have the QLCNIC_CDRP_CMD_BIT set in 674 * the crb QLCNIC_CDRP_CRB_OFFSET. 675 */ 676 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) 677 678 #define QLCNIC_RCODE_SUCCESS 0 679 #define QLCNIC_RCODE_INVALID_ARGS 6 680 #define QLCNIC_RCODE_NOT_SUPPORTED 9 681 #define QLCNIC_RCODE_NOT_PERMITTED 10 682 #define QLCNIC_RCODE_NOT_IMPL 15 683 #define QLCNIC_RCODE_INVALID 16 684 #define QLCNIC_RCODE_TIMEOUT 17 685 #define QLCNIC_DESTROY_CTX_RESET 0 686 687 /* 688 * Capabilities Announced 689 */ 690 #define QLCNIC_CAP0_LEGACY_CONTEXT (1) 691 #define QLCNIC_CAP0_LEGACY_MN (1 << 2) 692 #define QLCNIC_CAP0_LSO (1 << 6) 693 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) 694 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) 695 #define QLCNIC_CAP0_VALIDOFF (1 << 11) 696 #define QLCNIC_CAP0_LRO_MSS (1 << 21) 697 #define QLCNIC_CAP0_TX_MULTI (1 << 22) 698 699 /* 700 * Context state 701 */ 702 #define QLCNIC_HOST_CTX_STATE_FREED 0 703 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 704 705 /* 706 * Rx context 707 */ 708 709 struct qlcnic_hostrq_sds_ring { 710 __le64 host_phys_addr; /* Ring base addr */ 711 __le32 ring_size; /* Ring entries */ 712 __le16 msi_index; 713 __le16 rsvd; /* Padding */ 714 } __packed; 715 716 struct qlcnic_hostrq_rds_ring { 717 __le64 host_phys_addr; /* Ring base addr */ 718 __le64 buff_size; /* Packet buffer size */ 719 __le32 ring_size; /* Ring entries */ 720 __le32 ring_kind; /* Class of ring */ 721 } __packed; 722 723 struct qlcnic_hostrq_rx_ctx { 724 __le64 host_rsp_dma_addr; /* Response dma'd here */ 725 __le32 capabilities[4]; /* Flag bit vector */ 726 __le32 host_int_crb_mode; /* Interrupt crb usage */ 727 __le32 host_rds_crb_mode; /* RDS crb usage */ 728 /* These ring offsets are relative to data[0] below */ 729 __le32 rds_ring_offset; /* Offset to RDS config */ 730 __le32 sds_ring_offset; /* Offset to SDS config */ 731 __le16 num_rds_rings; /* Count of RDS rings */ 732 __le16 num_sds_rings; /* Count of SDS rings */ 733 __le16 valid_field_offset; 734 u8 txrx_sds_binding; 735 u8 msix_handler; 736 u8 reserved[128]; /* reserve space for future expansion*/ 737 /* MUST BE 64-bit aligned. 738 The following is packed: 739 - N hostrq_rds_rings 740 - N hostrq_sds_rings */ 741 char data[]; 742 } __packed; 743 744 struct qlcnic_cardrsp_rds_ring{ 745 __le32 host_producer_crb; /* Crb to use */ 746 __le32 rsvd1; /* Padding */ 747 } __packed; 748 749 struct qlcnic_cardrsp_sds_ring { 750 __le32 host_consumer_crb; /* Crb to use */ 751 __le32 interrupt_crb; /* Crb to use */ 752 } __packed; 753 754 struct qlcnic_cardrsp_rx_ctx { 755 /* These ring offsets are relative to data[0] below */ 756 __le32 rds_ring_offset; /* Offset to RDS config */ 757 __le32 sds_ring_offset; /* Offset to SDS config */ 758 __le32 host_ctx_state; /* Starting State */ 759 __le32 num_fn_per_port; /* How many PCI fn share the port */ 760 __le16 num_rds_rings; /* Count of RDS rings */ 761 __le16 num_sds_rings; /* Count of SDS rings */ 762 __le16 context_id; /* Handle for context */ 763 u8 phys_port; /* Physical id of port */ 764 u8 virt_port; /* Virtual/Logical id of port */ 765 u8 reserved[128]; /* save space for future expansion */ 766 /* MUST BE 64-bit aligned. 767 The following is packed: 768 - N cardrsp_rds_rings 769 - N cardrs_sds_rings */ 770 char data[]; 771 } __packed; 772 773 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 774 (sizeof(HOSTRQ_RX) + \ 775 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ 776 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) 777 778 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 779 (sizeof(CARDRSP_RX) + \ 780 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ 781 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) 782 783 /* 784 * Tx context 785 */ 786 787 struct qlcnic_hostrq_cds_ring { 788 __le64 host_phys_addr; /* Ring base addr */ 789 __le32 ring_size; /* Ring entries */ 790 __le32 rsvd; /* Padding */ 791 } __packed; 792 793 struct qlcnic_hostrq_tx_ctx { 794 __le64 host_rsp_dma_addr; /* Response dma'd here */ 795 __le64 cmd_cons_dma_addr; /* */ 796 __le64 dummy_dma_addr; /* */ 797 __le32 capabilities[4]; /* Flag bit vector */ 798 __le32 host_int_crb_mode; /* Interrupt crb usage */ 799 __le32 rsvd1; /* Padding */ 800 __le16 rsvd2; /* Padding */ 801 __le16 interrupt_ctl; 802 __le16 msi_index; 803 __le16 rsvd3; /* Padding */ 804 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ 805 u8 reserved[128]; /* future expansion */ 806 } __packed; 807 808 struct qlcnic_cardrsp_cds_ring { 809 __le32 host_producer_crb; /* Crb to use */ 810 __le32 interrupt_crb; /* Crb to use */ 811 } __packed; 812 813 struct qlcnic_cardrsp_tx_ctx { 814 __le32 host_ctx_state; /* Starting state */ 815 __le16 context_id; /* Handle for context */ 816 u8 phys_port; /* Physical id of port */ 817 u8 virt_port; /* Virtual/Logical id of port */ 818 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ 819 u8 reserved[128]; /* future expansion */ 820 } __packed; 821 822 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 823 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 824 825 /* CRB */ 826 827 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 828 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 829 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 830 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 831 832 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 833 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 834 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 835 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 836 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 837 838 839 /* MAC */ 840 841 #define MC_COUNT_P3P 38 842 843 #define QLCNIC_MAC_NOOP 0 844 #define QLCNIC_MAC_ADD 1 845 #define QLCNIC_MAC_DEL 2 846 #define QLCNIC_MAC_VLAN_ADD 3 847 #define QLCNIC_MAC_VLAN_DEL 4 848 849 enum qlcnic_mac_type { 850 QLCNIC_UNICAST_MAC, 851 QLCNIC_MULTICAST_MAC, 852 QLCNIC_BROADCAST_MAC, 853 }; 854 855 struct qlcnic_mac_vlan_list { 856 struct list_head list; 857 uint8_t mac_addr[ETH_ALEN+2]; 858 u16 vlan_id; 859 enum qlcnic_mac_type mac_type; 860 }; 861 862 /* MAC Learn */ 863 #define NO_MAC_LEARN 0 864 #define DRV_MAC_LEARN 1 865 #define FDB_MAC_LEARN 2 866 867 #define QLCNIC_HOST_REQUEST 0x13 868 #define QLCNIC_REQUEST 0x14 869 870 #define QLCNIC_MAC_EVENT 0x1 871 872 #define QLCNIC_IP_UP 2 873 #define QLCNIC_IP_DOWN 3 874 875 #define QLCNIC_ILB_MODE 0x1 876 #define QLCNIC_ELB_MODE 0x2 877 #define QLCNIC_LB_MODE_MASK 0x3 878 879 #define QLCNIC_LINKEVENT 0x1 880 #define QLCNIC_LB_RESPONSE 0x2 881 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ 882 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE)) 883 884 /* 885 * Driver --> Firmware 886 */ 887 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1 888 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3 889 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4 890 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7 891 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc 892 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12 893 894 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15 895 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17 896 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18 897 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13 898 899 /* 900 * Firmware --> Driver 901 */ 902 903 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f 904 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D 905 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90 906 907 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 908 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 909 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 910 911 #define QLCNIC_LRO_REQUEST_CLEANUP 4 912 913 /* Capabilites received */ 914 #define QLCNIC_FW_CAPABILITY_TSO BIT_1 915 #define QLCNIC_FW_CAPABILITY_BDG BIT_8 916 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9 917 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10 918 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4 919 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27 920 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31 921 922 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2 923 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3 924 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5 925 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7 926 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9 927 #define QLCNIC_FW_CAPABILITY_2_EXT_ISCSI_DUMP BIT_13 928 929 #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0 930 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1 931 #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4 932 933 /* module types */ 934 #define LINKEVENT_MODULE_NOT_PRESENT 1 935 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 936 #define LINKEVENT_MODULE_OPTICAL_SRLR 3 937 #define LINKEVENT_MODULE_OPTICAL_LRM 4 938 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 939 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 940 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 941 #define LINKEVENT_MODULE_TWINAX 8 942 943 #define LINKSPEED_10GBPS 10000 944 #define LINKSPEED_1GBPS 1000 945 #define LINKSPEED_100MBPS 100 946 #define LINKSPEED_10MBPS 10 947 948 #define LINKSPEED_ENCODED_10MBPS 0 949 #define LINKSPEED_ENCODED_100MBPS 1 950 #define LINKSPEED_ENCODED_1GBPS 2 951 952 #define LINKEVENT_AUTONEG_DISABLED 0 953 #define LINKEVENT_AUTONEG_ENABLED 1 954 955 #define LINKEVENT_HALF_DUPLEX 0 956 #define LINKEVENT_FULL_DUPLEX 1 957 958 #define LINKEVENT_LINKSPEED_MBPS 0 959 #define LINKEVENT_LINKSPEED_ENCODED 1 960 961 /* firmware response header: 962 * 63:58 - message type 963 * 57:56 - owner 964 * 55:53 - desc count 965 * 52:48 - reserved 966 * 47:40 - completion id 967 * 39:32 - opcode 968 * 31:16 - error code 969 * 15:00 - reserved 970 */ 971 #define qlcnic_get_nic_msg_opcode(msg_hdr) \ 972 ((msg_hdr >> 32) & 0xFF) 973 974 struct qlcnic_fw_msg { 975 union { 976 struct { 977 u64 hdr; 978 u64 body[7]; 979 }; 980 u64 words[8]; 981 }; 982 }; 983 984 struct qlcnic_nic_req { 985 __le64 qhdr; 986 __le64 req_hdr; 987 __le64 words[6]; 988 } __packed; 989 990 struct qlcnic_mac_req { 991 u8 op; 992 u8 tag; 993 u8 mac_addr[6]; 994 }; 995 996 struct qlcnic_vlan_req { 997 __le16 vlan_id; 998 __le16 rsvd[3]; 999 } __packed; 1000 1001 struct qlcnic_ipaddr { 1002 __be32 ipv4; 1003 __be32 ipv6[4]; 1004 }; 1005 1006 #define QLCNIC_MSI_ENABLED 0x02 1007 #define QLCNIC_MSIX_ENABLED 0x04 1008 #define QLCNIC_LRO_ENABLED 0x01 1009 #define QLCNIC_LRO_DISABLED 0x00 1010 #define QLCNIC_BRIDGE_ENABLED 0X10 1011 #define QLCNIC_DIAG_ENABLED 0x20 1012 #define QLCNIC_ESWITCH_ENABLED 0x40 1013 #define QLCNIC_ADAPTER_INITIALIZED 0x80 1014 #define QLCNIC_TAGGING_ENABLED 0x100 1015 #define QLCNIC_MACSPOOF 0x200 1016 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400 1017 #define QLCNIC_PROMISC_DISABLED 0x800 1018 #define QLCNIC_NEED_FLR 0x1000 1019 #define QLCNIC_FW_RESET_OWNER 0x2000 1020 #define QLCNIC_FW_HANG 0x4000 1021 #define QLCNIC_FW_LRO_MSS_CAP 0x8000 1022 #define QLCNIC_TX_INTR_SHARED 0x10000 1023 #define QLCNIC_APP_CHANGED_FLAGS 0x20000 1024 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000 1025 #define QLCNIC_TSS_RSS 0x80000 1026 1027 #define QLCNIC_VLAN_FILTERING 0x800000 1028 1029 #define QLCNIC_IS_MSI_FAMILY(adapter) \ 1030 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) 1031 #define QLCNIC_IS_TSO_CAPABLE(adapter) \ 1032 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO) 1033 1034 #define QLCNIC_BEACON_EANBLE 0xC 1035 #define QLCNIC_BEACON_DISABLE 0xD 1036 1037 #define QLCNIC_BEACON_ON 2 1038 #define QLCNIC_BEACON_OFF 0 1039 1040 #define QLCNIC_MSIX_TBL_SPACE 8192 1041 #define QLCNIC_PCI_REG_MSIX_TBL 0x44 1042 #define QLCNIC_MSIX_TBL_PGSIZE 4096 1043 1044 #define QLCNIC_ADAPTER_UP_MAGIC 777 1045 1046 #define __QLCNIC_FW_ATTACHED 0 1047 #define __QLCNIC_DEV_UP 1 1048 #define __QLCNIC_RESETTING 2 1049 #define __QLCNIC_START_FW 4 1050 #define __QLCNIC_AER 5 1051 #define __QLCNIC_DIAG_RES_ALLOC 6 1052 #define __QLCNIC_LED_ENABLE 7 1053 #define __QLCNIC_ELB_INPROGRESS 8 1054 #define __QLCNIC_MULTI_TX_UNIQUE 9 1055 #define __QLCNIC_SRIOV_ENABLE 10 1056 #define __QLCNIC_SRIOV_CAPABLE 11 1057 #define __QLCNIC_MBX_POLL_ENABLE 12 1058 #define __QLCNIC_DIAG_MODE 13 1059 #define __QLCNIC_MAINTENANCE_MODE 16 1060 1061 #define QLCNIC_INTERRUPT_TEST 1 1062 #define QLCNIC_LOOPBACK_TEST 2 1063 #define QLCNIC_LED_TEST 3 1064 1065 #define QLCNIC_FILTER_AGE 80 1066 #define QLCNIC_READD_AGE 20 1067 #define QLCNIC_LB_MAX_FILTERS 64 1068 #define QLCNIC_LB_BUCKET_SIZE 32 1069 #define QLCNIC_ILB_MAX_RCV_LOOP 10 1070 1071 struct qlcnic_filter { 1072 struct hlist_node fnode; 1073 u8 faddr[ETH_ALEN]; 1074 u16 vlan_id; 1075 unsigned long ftime; 1076 }; 1077 1078 struct qlcnic_filter_hash { 1079 struct hlist_head *fhead; 1080 u8 fnum; 1081 u16 fmax; 1082 u16 fbucket_size; 1083 }; 1084 1085 /* Mailbox specific data structures */ 1086 struct qlcnic_mailbox { 1087 struct workqueue_struct *work_q; 1088 struct qlcnic_adapter *adapter; 1089 const struct qlcnic_mbx_ops *ops; 1090 struct work_struct work; 1091 struct completion completion; 1092 struct list_head cmd_q; 1093 unsigned long status; 1094 spinlock_t queue_lock; /* Mailbox queue lock */ 1095 spinlock_t aen_lock; /* Mailbox response/AEN lock */ 1096 u32 rsp_status; 1097 u32 num_cmds; 1098 }; 1099 1100 struct qlcnic_adapter { 1101 struct qlcnic_hardware_context *ahw; 1102 struct qlcnic_recv_context *recv_ctx; 1103 struct qlcnic_host_tx_ring *tx_ring; 1104 struct net_device *netdev; 1105 struct pci_dev *pdev; 1106 1107 unsigned long state; 1108 u32 flags; 1109 1110 u16 num_txd; 1111 u16 num_rxd; 1112 u16 num_jumbo_rxd; 1113 u16 max_rxd; 1114 u16 max_jumbo_rxd; 1115 1116 u8 max_rds_rings; 1117 1118 u8 max_sds_rings; /* max sds rings supported by adapter */ 1119 u8 max_tx_rings; /* max tx rings supported by adapter */ 1120 1121 u8 drv_tx_rings; /* max tx rings supported by driver */ 1122 u8 drv_sds_rings; /* max sds rings supported by driver */ 1123 1124 u8 drv_tss_rings; /* tss ring input */ 1125 u8 drv_rss_rings; /* rss ring input */ 1126 1127 u8 rx_csum; 1128 u8 portnum; 1129 1130 u8 fw_wait_cnt; 1131 u8 fw_fail_cnt; 1132 u8 tx_timeo_cnt; 1133 u8 need_fw_reset; 1134 u8 reset_ctx_cnt; 1135 1136 u16 is_up; 1137 u16 rx_pvid; 1138 u16 tx_pvid; 1139 1140 u32 irq; 1141 u32 heartbeat; 1142 1143 u8 dev_state; 1144 u8 reset_ack_timeo; 1145 u8 dev_init_timeo; 1146 1147 u8 mac_addr[ETH_ALEN]; 1148 1149 u64 dev_rst_time; 1150 bool drv_mac_learn; 1151 bool fdb_mac_learn; 1152 bool rx_mac_learn; 1153 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1154 u8 flash_mfg_id; 1155 struct qlcnic_npar_info *npars; 1156 struct qlcnic_eswitch *eswitch; 1157 struct qlcnic_nic_template *nic_ops; 1158 1159 struct qlcnic_adapter_stats stats; 1160 struct list_head mac_list; 1161 1162 void __iomem *tgt_mask_reg; 1163 void __iomem *tgt_status_reg; 1164 void __iomem *crb_int_state_reg; 1165 void __iomem *isr_int_vec; 1166 1167 struct msix_entry *msix_entries; 1168 struct workqueue_struct *qlcnic_wq; 1169 struct delayed_work fw_work; 1170 struct delayed_work idc_aen_work; 1171 struct delayed_work mbx_poll_work; 1172 struct qlcnic_dcb *dcb; 1173 1174 struct qlcnic_filter_hash fhash; 1175 struct qlcnic_filter_hash rx_fhash; 1176 struct list_head vf_mc_list; 1177 1178 spinlock_t mac_learn_lock; 1179 /* spinlock for catching rcv filters for eswitch traffic */ 1180 spinlock_t rx_mac_learn_lock; 1181 u32 file_prd_off; /*File fw product offset*/ 1182 u32 fw_version; 1183 u32 offload_flags; 1184 const struct firmware *fw; 1185 }; 1186 1187 struct qlcnic_info_le { 1188 __le16 pci_func; 1189 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */ 1190 __le16 phys_port; 1191 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */ 1192 1193 __le32 capabilities; 1194 u8 max_mac_filters; 1195 u8 reserved1; 1196 __le16 max_mtu; 1197 1198 __le16 max_tx_ques; 1199 __le16 max_rx_ques; 1200 __le16 min_tx_bw; 1201 __le16 max_tx_bw; 1202 __le32 op_type; 1203 __le16 max_bw_reg_offset; 1204 __le16 max_linkspeed_reg_offset; 1205 __le32 capability1; 1206 __le32 capability2; 1207 __le32 capability3; 1208 __le16 max_tx_mac_filters; 1209 __le16 max_rx_mcast_mac_filters; 1210 __le16 max_rx_ucast_mac_filters; 1211 __le16 max_rx_ip_addr; 1212 __le16 max_rx_lro_flow; 1213 __le16 max_rx_status_rings; 1214 __le16 max_rx_buf_rings; 1215 __le16 max_tx_vlan_keys; 1216 u8 total_pf; 1217 u8 total_rss_engines; 1218 __le16 max_vports; 1219 __le16 linkstate_reg_offset; 1220 __le16 bit_offsets; 1221 __le16 max_local_ipv6_addrs; 1222 __le16 max_remote_ipv6_addrs; 1223 u8 reserved2[56]; 1224 } __packed; 1225 1226 struct qlcnic_info { 1227 u16 pci_func; 1228 u16 op_mode; 1229 u16 phys_port; 1230 u16 switch_mode; 1231 u32 capabilities; 1232 u8 max_mac_filters; 1233 u16 max_mtu; 1234 u16 max_tx_ques; 1235 u16 max_rx_ques; 1236 u16 min_tx_bw; 1237 u16 max_tx_bw; 1238 u32 op_type; 1239 u16 max_bw_reg_offset; 1240 u16 max_linkspeed_reg_offset; 1241 u32 capability1; 1242 u32 capability2; 1243 u32 capability3; 1244 u16 max_tx_mac_filters; 1245 u16 max_rx_mcast_mac_filters; 1246 u16 max_rx_ucast_mac_filters; 1247 u16 max_rx_ip_addr; 1248 u16 max_rx_lro_flow; 1249 u16 max_rx_status_rings; 1250 u16 max_rx_buf_rings; 1251 u16 max_tx_vlan_keys; 1252 u8 total_pf; 1253 u8 total_rss_engines; 1254 u16 max_vports; 1255 u16 linkstate_reg_offset; 1256 u16 bit_offsets; 1257 u16 max_local_ipv6_addrs; 1258 u16 max_remote_ipv6_addrs; 1259 }; 1260 1261 struct qlcnic_pci_info_le { 1262 __le16 id; /* pci function id */ 1263 __le16 active; /* 1 = Enabled */ 1264 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */ 1265 __le16 default_port; /* default port number */ 1266 1267 __le16 tx_min_bw; /* Multiple of 100mbpc */ 1268 __le16 tx_max_bw; 1269 __le16 reserved1[2]; 1270 1271 u8 mac[ETH_ALEN]; 1272 __le16 func_count; 1273 u8 reserved2[104]; 1274 1275 } __packed; 1276 1277 struct qlcnic_pci_info { 1278 u16 id; 1279 u16 active; 1280 u16 type; 1281 u16 default_port; 1282 u16 tx_min_bw; 1283 u16 tx_max_bw; 1284 u8 mac[ETH_ALEN]; 1285 u16 func_count; 1286 }; 1287 1288 struct qlcnic_npar_info { 1289 bool eswitch_status; 1290 u16 pvid; 1291 u16 min_bw; 1292 u16 max_bw; 1293 u8 phy_port; 1294 u8 type; 1295 u8 active; 1296 u8 enable_pm; 1297 u8 dest_npar; 1298 u8 discard_tagged; 1299 u8 mac_override; 1300 u8 mac_anti_spoof; 1301 u8 promisc_mode; 1302 u8 offload_flags; 1303 u8 pci_func; 1304 u8 mac[ETH_ALEN]; 1305 }; 1306 1307 struct qlcnic_eswitch { 1308 u8 port; 1309 u8 active_vports; 1310 u8 active_vlans; 1311 u8 active_ucast_filters; 1312 u8 max_ucast_filters; 1313 u8 max_active_vlans; 1314 1315 u32 flags; 1316 #define QLCNIC_SWITCH_ENABLE BIT_1 1317 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2 1318 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3 1319 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4 1320 }; 1321 1322 1323 #define MAX_BW 100 /* % of link speed */ 1324 #define MIN_BW 1 /* % of link speed */ 1325 #define MAX_VLAN_ID 4095 1326 #define MIN_VLAN_ID 2 1327 #define DEFAULT_MAC_LEARN 1 1328 1329 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID) 1330 #define IS_VALID_BW(bw) (bw <= MAX_BW) 1331 1332 struct qlcnic_pci_func_cfg { 1333 u16 func_type; 1334 u16 min_bw; 1335 u16 max_bw; 1336 u16 port_num; 1337 u8 pci_func; 1338 u8 func_state; 1339 u8 def_mac_addr[ETH_ALEN]; 1340 }; 1341 1342 struct qlcnic_npar_func_cfg { 1343 u32 fw_capab; 1344 u16 port_num; 1345 u16 min_bw; 1346 u16 max_bw; 1347 u16 max_tx_queues; 1348 u16 max_rx_queues; 1349 u8 pci_func; 1350 u8 op_mode; 1351 }; 1352 1353 struct qlcnic_pm_func_cfg { 1354 u8 pci_func; 1355 u8 action; 1356 u8 dest_npar; 1357 u8 reserved[5]; 1358 }; 1359 1360 struct qlcnic_esw_func_cfg { 1361 u16 vlan_id; 1362 u8 op_mode; 1363 u8 op_type; 1364 u8 pci_func; 1365 u8 host_vlan_tag; 1366 u8 promisc_mode; 1367 u8 discard_tagged; 1368 u8 mac_override; 1369 u8 mac_anti_spoof; 1370 u8 offload_flags; 1371 u8 reserved[5]; 1372 }; 1373 1374 #define QLCNIC_STATS_VERSION 1 1375 #define QLCNIC_STATS_PORT 1 1376 #define QLCNIC_STATS_ESWITCH 2 1377 #define QLCNIC_QUERY_RX_COUNTER 0 1378 #define QLCNIC_QUERY_TX_COUNTER 1 1379 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL 1380 #define QLCNIC_FILL_STATS(VAL1) \ 1381 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1) 1382 #define QLCNIC_MAC_STATS 1 1383 #define QLCNIC_ESW_STATS 2 1384 1385 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\ 1386 do { \ 1387 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \ 1388 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1389 (VAL1) = (VAL2); \ 1390 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \ 1391 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \ 1392 (VAL1) += (VAL2); \ 1393 } while (0) 1394 1395 struct qlcnic_mac_statistics_le { 1396 __le64 mac_tx_frames; 1397 __le64 mac_tx_bytes; 1398 __le64 mac_tx_mcast_pkts; 1399 __le64 mac_tx_bcast_pkts; 1400 __le64 mac_tx_pause_cnt; 1401 __le64 mac_tx_ctrl_pkt; 1402 __le64 mac_tx_lt_64b_pkts; 1403 __le64 mac_tx_lt_127b_pkts; 1404 __le64 mac_tx_lt_255b_pkts; 1405 __le64 mac_tx_lt_511b_pkts; 1406 __le64 mac_tx_lt_1023b_pkts; 1407 __le64 mac_tx_lt_1518b_pkts; 1408 __le64 mac_tx_gt_1518b_pkts; 1409 __le64 rsvd1[3]; 1410 1411 __le64 mac_rx_frames; 1412 __le64 mac_rx_bytes; 1413 __le64 mac_rx_mcast_pkts; 1414 __le64 mac_rx_bcast_pkts; 1415 __le64 mac_rx_pause_cnt; 1416 __le64 mac_rx_ctrl_pkt; 1417 __le64 mac_rx_lt_64b_pkts; 1418 __le64 mac_rx_lt_127b_pkts; 1419 __le64 mac_rx_lt_255b_pkts; 1420 __le64 mac_rx_lt_511b_pkts; 1421 __le64 mac_rx_lt_1023b_pkts; 1422 __le64 mac_rx_lt_1518b_pkts; 1423 __le64 mac_rx_gt_1518b_pkts; 1424 __le64 rsvd2[3]; 1425 1426 __le64 mac_rx_length_error; 1427 __le64 mac_rx_length_small; 1428 __le64 mac_rx_length_large; 1429 __le64 mac_rx_jabber; 1430 __le64 mac_rx_dropped; 1431 __le64 mac_rx_crc_error; 1432 __le64 mac_align_error; 1433 } __packed; 1434 1435 struct qlcnic_mac_statistics { 1436 u64 mac_tx_frames; 1437 u64 mac_tx_bytes; 1438 u64 mac_tx_mcast_pkts; 1439 u64 mac_tx_bcast_pkts; 1440 u64 mac_tx_pause_cnt; 1441 u64 mac_tx_ctrl_pkt; 1442 u64 mac_tx_lt_64b_pkts; 1443 u64 mac_tx_lt_127b_pkts; 1444 u64 mac_tx_lt_255b_pkts; 1445 u64 mac_tx_lt_511b_pkts; 1446 u64 mac_tx_lt_1023b_pkts; 1447 u64 mac_tx_lt_1518b_pkts; 1448 u64 mac_tx_gt_1518b_pkts; 1449 u64 rsvd1[3]; 1450 u64 mac_rx_frames; 1451 u64 mac_rx_bytes; 1452 u64 mac_rx_mcast_pkts; 1453 u64 mac_rx_bcast_pkts; 1454 u64 mac_rx_pause_cnt; 1455 u64 mac_rx_ctrl_pkt; 1456 u64 mac_rx_lt_64b_pkts; 1457 u64 mac_rx_lt_127b_pkts; 1458 u64 mac_rx_lt_255b_pkts; 1459 u64 mac_rx_lt_511b_pkts; 1460 u64 mac_rx_lt_1023b_pkts; 1461 u64 mac_rx_lt_1518b_pkts; 1462 u64 mac_rx_gt_1518b_pkts; 1463 u64 rsvd2[3]; 1464 u64 mac_rx_length_error; 1465 u64 mac_rx_length_small; 1466 u64 mac_rx_length_large; 1467 u64 mac_rx_jabber; 1468 u64 mac_rx_dropped; 1469 u64 mac_rx_crc_error; 1470 u64 mac_align_error; 1471 }; 1472 1473 struct qlcnic_esw_stats_le { 1474 __le16 context_id; 1475 __le16 version; 1476 __le16 size; 1477 __le16 unused; 1478 __le64 unicast_frames; 1479 __le64 multicast_frames; 1480 __le64 broadcast_frames; 1481 __le64 dropped_frames; 1482 __le64 errors; 1483 __le64 local_frames; 1484 __le64 numbytes; 1485 __le64 rsvd[3]; 1486 } __packed; 1487 1488 struct __qlcnic_esw_statistics { 1489 u16 context_id; 1490 u16 version; 1491 u16 size; 1492 u16 unused; 1493 u64 unicast_frames; 1494 u64 multicast_frames; 1495 u64 broadcast_frames; 1496 u64 dropped_frames; 1497 u64 errors; 1498 u64 local_frames; 1499 u64 numbytes; 1500 u64 rsvd[3]; 1501 }; 1502 1503 struct qlcnic_esw_statistics { 1504 struct __qlcnic_esw_statistics rx; 1505 struct __qlcnic_esw_statistics tx; 1506 }; 1507 1508 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed 1509 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed 1510 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed 1511 #define QLCNIC_FORCE_FW_RESET 0xdeaddead 1512 #define QLCNIC_SET_QUIESCENT 0xadd00010 1513 #define QLCNIC_RESET_QUIESCENT 0xadd00020 1514 1515 struct _cdrp_cmd { 1516 u32 num; 1517 u32 *arg; 1518 }; 1519 1520 struct qlcnic_cmd_args { 1521 struct completion completion; 1522 struct list_head list; 1523 struct _cdrp_cmd req; 1524 struct _cdrp_cmd rsp; 1525 atomic_t rsp_status; 1526 int pay_size; 1527 u32 rsp_opcode; 1528 u32 total_cmds; 1529 u32 op_type; 1530 u32 type; 1531 u32 cmd_op; 1532 u32 *hdr; /* Back channel message header */ 1533 u32 *pay; /* Back channel message payload */ 1534 u8 func_num; 1535 }; 1536 1537 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter); 1538 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config); 1539 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); 1540 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); 1541 1542 #define ADDR_IN_RANGE(addr, low, high) \ 1543 (((addr) < (high)) && ((addr) >= (low))) 1544 1545 #define QLCRD32(adapter, off, err) \ 1546 (adapter->ahw->hw_ops->read_reg)(adapter, off, err) 1547 1548 #define QLCWR32(adapter, off, val) \ 1549 adapter->ahw->hw_ops->write_reg(adapter, off, val) 1550 1551 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); 1552 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); 1553 1554 #define qlcnic_rom_lock(a) \ 1555 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) 1556 #define qlcnic_rom_unlock(a) \ 1557 qlcnic_pcie_sem_unlock((a), 2) 1558 #define qlcnic_phy_lock(a) \ 1559 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) 1560 #define qlcnic_phy_unlock(a) \ 1561 qlcnic_pcie_sem_unlock((a), 3) 1562 #define qlcnic_sw_lock(a) \ 1563 qlcnic_pcie_sem_lock((a), 6, 0) 1564 #define qlcnic_sw_unlock(a) \ 1565 qlcnic_pcie_sem_unlock((a), 6) 1566 #define crb_win_lock(a) \ 1567 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) 1568 #define crb_win_unlock(a) \ 1569 qlcnic_pcie_sem_unlock((a), 7) 1570 1571 #define __QLCNIC_MAX_LED_RATE 0xf 1572 #define __QLCNIC_MAX_LED_STATE 0x2 1573 1574 #define MAX_CTL_CHECK 1000 1575 1576 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter); 1577 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter); 1578 int qlcnic_dump_fw(struct qlcnic_adapter *); 1579 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *); 1580 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *); 1581 1582 /* Functions from qlcnic_init.c */ 1583 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int); 1584 int qlcnic_load_firmware(struct qlcnic_adapter *adapter); 1585 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); 1586 void qlcnic_request_firmware(struct qlcnic_adapter *adapter); 1587 void qlcnic_release_firmware(struct qlcnic_adapter *adapter); 1588 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); 1589 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); 1590 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter); 1591 1592 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp); 1593 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, 1594 u8 *bytes, size_t size); 1595 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); 1596 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); 1597 1598 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32); 1599 1600 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); 1601 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); 1602 1603 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter); 1604 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter); 1605 1606 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter); 1607 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); 1608 void qlcnic_release_tx_buffers(struct qlcnic_adapter *, 1609 struct qlcnic_host_tx_ring *); 1610 1611 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter); 1612 void qlcnic_watchdog_task(struct work_struct *work); 1613 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, 1614 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id); 1615 void qlcnic_set_multi(struct net_device *netdev); 1616 void qlcnic_flush_mcast_mac(struct qlcnic_adapter *); 1617 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16, 1618 enum qlcnic_mac_type); 1619 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *); 1620 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter); 1621 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *); 1622 1623 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); 1624 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32); 1625 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); 1626 netdev_features_t qlcnic_fix_features(struct net_device *netdev, 1627 netdev_features_t features); 1628 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features); 1629 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable); 1630 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *); 1631 1632 /* Functions from qlcnic_ethtool.c */ 1633 int qlcnic_check_loopback_buff(unsigned char *, u8 []); 1634 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8); 1635 1636 /* Functions from qlcnic_main.c */ 1637 int qlcnic_reset_context(struct qlcnic_adapter *); 1638 void qlcnic_diag_free_res(struct net_device *netdev, int); 1639 int qlcnic_diag_alloc_res(struct net_device *netdev, int); 1640 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *); 1641 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8); 1642 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8); 1643 int qlcnic_setup_rings(struct qlcnic_adapter *); 1644 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int); 1645 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter); 1646 int qlcnic_enable_msix(struct qlcnic_adapter *, u32); 1647 void qlcnic_set_drv_version(struct qlcnic_adapter *); 1648 1649 /* eSwitch management functions */ 1650 int qlcnic_config_switch_port(struct qlcnic_adapter *, 1651 struct qlcnic_esw_func_cfg *); 1652 1653 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *, 1654 struct qlcnic_esw_func_cfg *); 1655 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8); 1656 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8, 1657 struct __qlcnic_esw_statistics *); 1658 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8, 1659 struct __qlcnic_esw_statistics *); 1660 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8); 1661 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *); 1662 1663 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd); 1664 1665 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int); 1666 void qlcnic_free_sds_rings(struct qlcnic_recv_context *); 1667 void qlcnic_advert_link_change(struct qlcnic_adapter *, int); 1668 void qlcnic_free_tx_rings(struct qlcnic_adapter *); 1669 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *); 1670 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1671 1672 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter); 1673 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter); 1674 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter); 1675 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter); 1676 1677 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32); 1678 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32); 1679 void qlcnic_set_vlan_config(struct qlcnic_adapter *, 1680 struct qlcnic_esw_func_cfg *); 1681 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *, 1682 struct qlcnic_esw_func_cfg *); 1683 int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *); 1684 void qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1685 int qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1686 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *); 1687 void qlcnic_detach(struct qlcnic_adapter *); 1688 void qlcnic_teardown_intr(struct qlcnic_adapter *); 1689 int qlcnic_attach(struct qlcnic_adapter *); 1690 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *); 1691 void qlcnic_restore_indev_addr(struct net_device *, unsigned long); 1692 1693 int qlcnic_check_temp(struct qlcnic_adapter *); 1694 int qlcnic_init_pci_info(struct qlcnic_adapter *); 1695 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *); 1696 int qlcnic_reset_npar_config(struct qlcnic_adapter *); 1697 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *); 1698 int qlcnic_set_vxlan_port(struct qlcnic_adapter *adapter, u16 port); 1699 int qlcnic_set_vxlan_parsing(struct qlcnic_adapter *adapter, u16 port); 1700 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter); 1701 int qlcnic_read_mac_addr(struct qlcnic_adapter *); 1702 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int); 1703 void qlcnic_set_netdev_features(struct qlcnic_adapter *, 1704 struct qlcnic_esw_func_cfg *); 1705 void qlcnic_sriov_vf_set_multi(struct net_device *); 1706 int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8); 1707 int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *, 1708 u16 *); 1709 1710 /* 1711 * QLOGIC Board information 1712 */ 1713 1714 #define QLCNIC_MAX_BOARD_NAME_LEN 100 1715 struct qlcnic_board_info { 1716 unsigned short vendor; 1717 unsigned short device; 1718 unsigned short sub_vendor; 1719 unsigned short sub_device; 1720 char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; 1721 }; 1722 1723 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) 1724 { 1725 if (likely(tx_ring->producer < tx_ring->sw_consumer)) 1726 return tx_ring->sw_consumer - tx_ring->producer; 1727 else 1728 return tx_ring->sw_consumer + tx_ring->num_desc - 1729 tx_ring->producer; 1730 } 1731 1732 struct qlcnic_nic_template { 1733 int (*config_bridged_mode) (struct qlcnic_adapter *, u32); 1734 int (*config_led) (struct qlcnic_adapter *, u32, u32); 1735 int (*start_firmware) (struct qlcnic_adapter *); 1736 int (*init_driver) (struct qlcnic_adapter *); 1737 void (*request_reset) (struct qlcnic_adapter *, u32); 1738 void (*cancel_idc_work) (struct qlcnic_adapter *); 1739 int (*napi_add)(struct qlcnic_adapter *, struct net_device *); 1740 void (*napi_del)(struct qlcnic_adapter *); 1741 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int); 1742 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *); 1743 int (*shutdown)(struct pci_dev *); 1744 int (*resume)(struct qlcnic_adapter *); 1745 }; 1746 1747 struct qlcnic_mbx_ops { 1748 int (*enqueue_cmd) (struct qlcnic_adapter *, 1749 struct qlcnic_cmd_args *, unsigned long *); 1750 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1751 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1752 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1753 void (*nofity_fw) (struct qlcnic_adapter *, u8); 1754 }; 1755 1756 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *); 1757 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *); 1758 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx); 1759 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx); 1760 void qlcnic_update_stats(struct qlcnic_adapter *); 1761 1762 /* Adapter hardware abstraction */ 1763 struct qlcnic_hardware_ops { 1764 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1765 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t); 1766 int (*read_reg) (struct qlcnic_adapter *, ulong, int *); 1767 int (*write_reg) (struct qlcnic_adapter *, ulong, u32); 1768 void (*get_ocm_win) (struct qlcnic_hardware_context *); 1769 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8); 1770 int (*setup_intr) (struct qlcnic_adapter *); 1771 int (*alloc_mbx_args)(struct qlcnic_cmd_args *, 1772 struct qlcnic_adapter *, u32); 1773 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *); 1774 void (*get_func_no) (struct qlcnic_adapter *); 1775 int (*api_lock) (struct qlcnic_adapter *); 1776 void (*api_unlock) (struct qlcnic_adapter *); 1777 void (*add_sysfs) (struct qlcnic_adapter *); 1778 void (*remove_sysfs) (struct qlcnic_adapter *); 1779 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *); 1780 int (*create_rx_ctx) (struct qlcnic_adapter *); 1781 int (*create_tx_ctx) (struct qlcnic_adapter *, 1782 struct qlcnic_host_tx_ring *, int); 1783 void (*del_rx_ctx) (struct qlcnic_adapter *); 1784 void (*del_tx_ctx) (struct qlcnic_adapter *, 1785 struct qlcnic_host_tx_ring *); 1786 int (*setup_link_event) (struct qlcnic_adapter *, int); 1787 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8); 1788 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *); 1789 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *); 1790 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8); 1791 void (*napi_enable) (struct qlcnic_adapter *); 1792 void (*napi_disable) (struct qlcnic_adapter *); 1793 int (*config_intr_coal) (struct qlcnic_adapter *, 1794 struct ethtool_coalesce *); 1795 int (*config_rss) (struct qlcnic_adapter *, int); 1796 int (*config_hw_lro) (struct qlcnic_adapter *, int); 1797 int (*config_loopback) (struct qlcnic_adapter *, u8); 1798 int (*clear_loopback) (struct qlcnic_adapter *, u8); 1799 int (*config_promisc_mode) (struct qlcnic_adapter *, u32); 1800 void (*change_l2_filter)(struct qlcnic_adapter *adapter, u64 *addr, 1801 u16 vlan, struct qlcnic_host_tx_ring *tx_ring); 1802 int (*get_board_info) (struct qlcnic_adapter *); 1803 void (*set_mac_filter_count) (struct qlcnic_adapter *); 1804 void (*free_mac_list) (struct qlcnic_adapter *); 1805 int (*read_phys_port_id) (struct qlcnic_adapter *); 1806 pci_ers_result_t (*io_error_detected) (struct pci_dev *, 1807 pci_channel_state_t); 1808 pci_ers_result_t (*io_slot_reset) (struct pci_dev *); 1809 void (*io_resume) (struct pci_dev *); 1810 void (*get_beacon_state)(struct qlcnic_adapter *); 1811 void (*enable_sds_intr) (struct qlcnic_adapter *, 1812 struct qlcnic_host_sds_ring *); 1813 void (*disable_sds_intr) (struct qlcnic_adapter *, 1814 struct qlcnic_host_sds_ring *); 1815 void (*enable_tx_intr) (struct qlcnic_adapter *, 1816 struct qlcnic_host_tx_ring *); 1817 void (*disable_tx_intr) (struct qlcnic_adapter *, 1818 struct qlcnic_host_tx_ring *); 1819 u32 (*get_saved_state)(void *, u32); 1820 void (*set_saved_state)(void *, u32, u32); 1821 void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *); 1822 u32 (*get_cap_size)(void *, int); 1823 void (*set_sys_info)(void *, int, u32); 1824 void (*store_cap_mask)(void *, u32); 1825 bool (*encap_rx_offload) (struct qlcnic_adapter *adapter); 1826 bool (*encap_tx_offload) (struct qlcnic_adapter *adapter); 1827 }; 1828 1829 extern struct qlcnic_nic_template qlcnic_vf_ops; 1830 1831 static inline bool qlcnic_83xx_encap_tx_offload(struct qlcnic_adapter *adapter) 1832 { 1833 return adapter->ahw->extra_capability[0] & 1834 QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD; 1835 } 1836 1837 static inline bool qlcnic_83xx_encap_rx_offload(struct qlcnic_adapter *adapter) 1838 { 1839 return adapter->ahw->extra_capability[0] & 1840 QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD; 1841 } 1842 1843 static inline bool qlcnic_82xx_encap_tx_offload(struct qlcnic_adapter *adapter) 1844 { 1845 return false; 1846 } 1847 1848 static inline bool qlcnic_82xx_encap_rx_offload(struct qlcnic_adapter *adapter) 1849 { 1850 return false; 1851 } 1852 1853 static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter) 1854 { 1855 return adapter->ahw->hw_ops->encap_rx_offload(adapter); 1856 } 1857 1858 static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter) 1859 { 1860 return adapter->ahw->hw_ops->encap_tx_offload(adapter); 1861 } 1862 1863 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter) 1864 { 1865 return adapter->nic_ops->start_firmware(adapter); 1866 } 1867 1868 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf, 1869 loff_t offset, size_t size) 1870 { 1871 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size); 1872 } 1873 1874 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf, 1875 loff_t offset, size_t size) 1876 { 1877 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size); 1878 } 1879 1880 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, 1881 u8 *mac, u8 function) 1882 { 1883 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function); 1884 } 1885 1886 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter) 1887 { 1888 return adapter->ahw->hw_ops->setup_intr(adapter); 1889 } 1890 1891 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx, 1892 struct qlcnic_adapter *adapter, u32 arg) 1893 { 1894 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg); 1895 } 1896 1897 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter, 1898 struct qlcnic_cmd_args *cmd) 1899 { 1900 if (adapter->ahw->hw_ops->mbx_cmd) 1901 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd); 1902 1903 return -EIO; 1904 } 1905 1906 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter) 1907 { 1908 adapter->ahw->hw_ops->get_func_no(adapter); 1909 } 1910 1911 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter) 1912 { 1913 return adapter->ahw->hw_ops->api_lock(adapter); 1914 } 1915 1916 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter) 1917 { 1918 adapter->ahw->hw_ops->api_unlock(adapter); 1919 } 1920 1921 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter) 1922 { 1923 if (adapter->ahw->hw_ops->add_sysfs) 1924 adapter->ahw->hw_ops->add_sysfs(adapter); 1925 } 1926 1927 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter) 1928 { 1929 if (adapter->ahw->hw_ops->remove_sysfs) 1930 adapter->ahw->hw_ops->remove_sysfs(adapter); 1931 } 1932 1933 static inline void 1934 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring) 1935 { 1936 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring); 1937 } 1938 1939 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) 1940 { 1941 return adapter->ahw->hw_ops->create_rx_ctx(adapter); 1942 } 1943 1944 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter, 1945 struct qlcnic_host_tx_ring *ptr, 1946 int ring) 1947 { 1948 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring); 1949 } 1950 1951 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter) 1952 { 1953 return adapter->ahw->hw_ops->del_rx_ctx(adapter); 1954 } 1955 1956 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter, 1957 struct qlcnic_host_tx_ring *ptr) 1958 { 1959 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr); 1960 } 1961 1962 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, 1963 int enable) 1964 { 1965 return adapter->ahw->hw_ops->setup_link_event(adapter, enable); 1966 } 1967 1968 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, 1969 struct qlcnic_info *info, u8 id) 1970 { 1971 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id); 1972 } 1973 1974 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, 1975 struct qlcnic_pci_info *info) 1976 { 1977 return adapter->ahw->hw_ops->get_pci_info(adapter, info); 1978 } 1979 1980 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, 1981 struct qlcnic_info *info) 1982 { 1983 return adapter->ahw->hw_ops->set_nic_info(adapter, info); 1984 } 1985 1986 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, 1987 u8 *addr, u16 id, u8 cmd) 1988 { 1989 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd); 1990 } 1991 1992 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter, 1993 struct net_device *netdev) 1994 { 1995 return adapter->nic_ops->napi_add(adapter, netdev); 1996 } 1997 1998 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter) 1999 { 2000 adapter->nic_ops->napi_del(adapter); 2001 } 2002 2003 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter) 2004 { 2005 adapter->ahw->hw_ops->napi_enable(adapter); 2006 } 2007 2008 static inline int __qlcnic_shutdown(struct pci_dev *pdev) 2009 { 2010 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 2011 2012 return adapter->nic_ops->shutdown(pdev); 2013 } 2014 2015 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter) 2016 { 2017 return adapter->nic_ops->resume(adapter); 2018 } 2019 2020 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter) 2021 { 2022 adapter->ahw->hw_ops->napi_disable(adapter); 2023 } 2024 2025 static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter, 2026 struct ethtool_coalesce *ethcoal) 2027 { 2028 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal); 2029 } 2030 2031 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable) 2032 { 2033 return adapter->ahw->hw_ops->config_rss(adapter, enable); 2034 } 2035 2036 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, 2037 int enable) 2038 { 2039 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable); 2040 } 2041 2042 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 2043 { 2044 return adapter->ahw->hw_ops->config_loopback(adapter, mode); 2045 } 2046 2047 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode) 2048 { 2049 return adapter->ahw->hw_ops->clear_loopback(adapter, mode); 2050 } 2051 2052 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, 2053 u32 mode) 2054 { 2055 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode); 2056 } 2057 2058 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter, 2059 u64 *addr, u16 vlan, 2060 struct qlcnic_host_tx_ring *tx_ring) 2061 { 2062 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, vlan, tx_ring); 2063 } 2064 2065 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter) 2066 { 2067 return adapter->ahw->hw_ops->get_board_info(adapter); 2068 } 2069 2070 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter) 2071 { 2072 return adapter->ahw->hw_ops->free_mac_list(adapter); 2073 } 2074 2075 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter) 2076 { 2077 if (adapter->ahw->hw_ops->set_mac_filter_count) 2078 adapter->ahw->hw_ops->set_mac_filter_count(adapter); 2079 } 2080 2081 static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter) 2082 { 2083 adapter->ahw->hw_ops->get_beacon_state(adapter); 2084 } 2085 2086 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter) 2087 { 2088 if (adapter->ahw->hw_ops->read_phys_port_id) 2089 adapter->ahw->hw_ops->read_phys_port_id(adapter); 2090 } 2091 2092 static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter, 2093 void *t_hdr, u32 index) 2094 { 2095 return adapter->ahw->hw_ops->get_saved_state(t_hdr, index); 2096 } 2097 2098 static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter, 2099 void *t_hdr, u32 index, u32 value) 2100 { 2101 adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value); 2102 } 2103 2104 static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter, 2105 struct qlcnic_fw_dump *fw_dump) 2106 { 2107 adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump); 2108 } 2109 2110 static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter, 2111 void *tmpl_hdr, int index) 2112 { 2113 return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index); 2114 } 2115 2116 static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter, 2117 void *tmpl_hdr, int idx, u32 value) 2118 { 2119 adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value); 2120 } 2121 2122 static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter, 2123 void *tmpl_hdr, u32 mask) 2124 { 2125 adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask); 2126 } 2127 2128 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter, 2129 u32 key) 2130 { 2131 if (adapter->nic_ops->request_reset) 2132 adapter->nic_ops->request_reset(adapter, key); 2133 } 2134 2135 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter) 2136 { 2137 if (adapter->nic_ops->cancel_idc_work) 2138 adapter->nic_ops->cancel_idc_work(adapter); 2139 } 2140 2141 static inline irqreturn_t 2142 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter) 2143 { 2144 return adapter->nic_ops->clear_legacy_intr(adapter); 2145 } 2146 2147 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, 2148 u32 rate) 2149 { 2150 return adapter->nic_ops->config_led(adapter, state, rate); 2151 } 2152 2153 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, 2154 __be32 ip, int cmd) 2155 { 2156 adapter->nic_ops->config_ipaddr(adapter, ip, cmd); 2157 } 2158 2159 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter) 2160 { 2161 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2162 } 2163 2164 static inline void 2165 qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter, 2166 struct qlcnic_host_tx_ring *tx_ring) 2167 { 2168 if (qlcnic_check_multi_tx(adapter) && 2169 !adapter->ahw->diag_test) 2170 writel(0x0, tx_ring->crb_intr_mask); 2171 } 2172 2173 static inline void 2174 qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter, 2175 struct qlcnic_host_tx_ring *tx_ring) 2176 { 2177 if (qlcnic_check_multi_tx(adapter) && 2178 !adapter->ahw->diag_test) 2179 writel(1, tx_ring->crb_intr_mask); 2180 } 2181 2182 static inline void 2183 qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter, 2184 struct qlcnic_host_tx_ring *tx_ring) 2185 { 2186 writel(0, tx_ring->crb_intr_mask); 2187 } 2188 2189 static inline void 2190 qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter, 2191 struct qlcnic_host_tx_ring *tx_ring) 2192 { 2193 writel(1, tx_ring->crb_intr_mask); 2194 } 2195 2196 /* Enable MSI-x and INT-x interrupts */ 2197 static inline void 2198 qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter, 2199 struct qlcnic_host_sds_ring *sds_ring) 2200 { 2201 writel(0, sds_ring->crb_intr_mask); 2202 } 2203 2204 /* Disable MSI-x and INT-x interrupts */ 2205 static inline void 2206 qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter, 2207 struct qlcnic_host_sds_ring *sds_ring) 2208 { 2209 writel(1, sds_ring->crb_intr_mask); 2210 } 2211 2212 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter) 2213 { 2214 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state); 2215 adapter->drv_tx_rings = QLCNIC_SINGLE_RING; 2216 } 2217 2218 /* When operating in a muti tx mode, driver needs to write 0x1 2219 * to src register, instead of 0x0 to disable receiving interrupt. 2220 */ 2221 static inline void 2222 qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter, 2223 struct qlcnic_host_sds_ring *sds_ring) 2224 { 2225 if (qlcnic_check_multi_tx(adapter) && 2226 !adapter->ahw->diag_test && 2227 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2228 writel(0x1, sds_ring->crb_intr_mask); 2229 else 2230 writel(0, sds_ring->crb_intr_mask); 2231 } 2232 2233 static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter, 2234 struct qlcnic_host_sds_ring *sds_ring) 2235 { 2236 if (adapter->ahw->hw_ops->enable_sds_intr) 2237 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring); 2238 } 2239 2240 static inline void 2241 qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter, 2242 struct qlcnic_host_sds_ring *sds_ring) 2243 { 2244 if (adapter->ahw->hw_ops->disable_sds_intr) 2245 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring); 2246 } 2247 2248 static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter, 2249 struct qlcnic_host_tx_ring *tx_ring) 2250 { 2251 if (adapter->ahw->hw_ops->enable_tx_intr) 2252 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring); 2253 } 2254 2255 static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter, 2256 struct qlcnic_host_tx_ring *tx_ring) 2257 { 2258 if (adapter->ahw->hw_ops->disable_tx_intr) 2259 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring); 2260 } 2261 2262 /* When operating in a muti tx mode, driver needs to write 0x0 2263 * to src register, instead of 0x1 to enable receiving interrupts. 2264 */ 2265 static inline void 2266 qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter, 2267 struct qlcnic_host_sds_ring *sds_ring) 2268 { 2269 if (qlcnic_check_multi_tx(adapter) && 2270 !adapter->ahw->diag_test && 2271 (adapter->flags & QLCNIC_MSIX_ENABLED)) 2272 writel(0, sds_ring->crb_intr_mask); 2273 else 2274 writel(0x1, sds_ring->crb_intr_mask); 2275 2276 if (!QLCNIC_IS_MSI_FAMILY(adapter)) 2277 writel(0xfbff, adapter->tgt_mask_reg); 2278 } 2279 2280 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter) 2281 { 2282 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2283 } 2284 2285 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter) 2286 { 2287 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2288 } 2289 2290 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter) 2291 { 2292 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state); 2293 } 2294 2295 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops; 2296 extern const struct ethtool_ops qlcnic_ethtool_ops; 2297 extern const struct ethtool_ops qlcnic_ethtool_failed_ops; 2298 2299 #define QLCDB(adapter, lvl, _fmt, _args...) do { \ 2300 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \ 2301 printk(KERN_INFO "%s: %s: " _fmt, \ 2302 dev_name(&adapter->pdev->dev), \ 2303 __func__, ##_args); \ 2304 } while (0) 2305 2306 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020 2307 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030 2308 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430 2309 #define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830 2310 #define PCI_DEVICE_ID_QLOGIC_VF_QLE8C30 0x8C30 2311 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040 2312 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440 2313 2314 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter) 2315 { 2316 unsigned short device = adapter->pdev->device; 2317 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false; 2318 } 2319 2320 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter) 2321 { 2322 unsigned short device = adapter->pdev->device; 2323 2324 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2325 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false; 2326 } 2327 2328 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter) 2329 { 2330 unsigned short device = adapter->pdev->device; 2331 bool status; 2332 2333 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) || 2334 (device == PCI_DEVICE_ID_QLOGIC_QLE8830) || 2335 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) || 2336 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || 2337 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || 2338 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false; 2339 2340 return status; 2341 } 2342 2343 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter) 2344 { 2345 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false; 2346 } 2347 2348 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter) 2349 { 2350 unsigned short device = adapter->pdev->device; 2351 bool status; 2352 2353 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || 2354 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) || 2355 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false; 2356 2357 return status; 2358 } 2359 2360 static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter) 2361 { 2362 unsigned short device = adapter->pdev->device; 2363 2364 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false; 2365 } 2366 2367 static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter) 2368 { 2369 unsigned short device = adapter->pdev->device; 2370 2371 return ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) || 2372 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false; 2373 } 2374 2375 static inline bool qlcnic_sriov_check(struct qlcnic_adapter *adapter) 2376 { 2377 bool status; 2378 2379 status = (qlcnic_sriov_pf_check(adapter) || 2380 qlcnic_sriov_vf_check(adapter)) ? true : false; 2381 2382 return status; 2383 } 2384 2385 static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter) 2386 { 2387 if (qlcnic_84xx_check(adapter)) 2388 return QLC_84XX_VNIC_COUNT; 2389 else 2390 return QLC_DEFAULT_VNIC_COUNT; 2391 } 2392 2393 static inline void qlcnic_swap32_buffer(u32 *buffer, int count) 2394 { 2395 #if defined(__BIG_ENDIAN) 2396 u32 *tmp = buffer; 2397 int i; 2398 2399 for (i = 0; i < count; i++) { 2400 *tmp = swab32(*tmp); 2401 tmp++; 2402 } 2403 #endif 2404 } 2405 2406 #ifdef CONFIG_QLCNIC_HWMON 2407 void qlcnic_register_hwmon_dev(struct qlcnic_adapter *); 2408 void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *); 2409 #else 2410 static inline void qlcnic_register_hwmon_dev(struct qlcnic_adapter *adapter) 2411 { 2412 return; 2413 } 2414 static inline void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *adapter) 2415 { 2416 return; 2417 } 2418 #endif 2419 #endif /* __QLCNIC_H_ */ 2420