1 /** 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8 /* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33 #include <linux/compat.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <linux/mmu_notifier.h> 39 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_fb_helper.h> 43 #include <drm/drm_file.h> 44 #include <drm/drm_gem.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_pci.h> 47 #include <drm/drm_pciids.h> 48 #include <drm/drm_probe_helper.h> 49 #include <drm/drm_vblank.h> 50 #include <drm/radeon_drm.h> 51 52 #include "radeon_drv.h" 53 54 /* 55 * KMS wrapper. 56 * - 2.0.0 - initial interface 57 * - 2.1.0 - add square tiling interface 58 * - 2.2.0 - add r6xx/r7xx const buffer support 59 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 60 * - 2.4.0 - add crtc id query 61 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 62 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 63 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 64 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 65 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 66 * 2.10.0 - fusion 2D tiling 67 * 2.11.0 - backend map, initial compute support for the CS checker 68 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 69 * 2.13.0 - virtual memory support, streamout 70 * 2.14.0 - add evergreen tiling informations 71 * 2.15.0 - add max_pipes query 72 * 2.16.0 - fix evergreen 2D tiled surface calculation 73 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 74 * 2.18.0 - r600-eg: allow "invalid" DB formats 75 * 2.19.0 - r600-eg: MSAA textures 76 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 77 * 2.21.0 - r600-r700: FMASK and CMASK 78 * 2.22.0 - r600 only: RESOLVE_BOX allowed 79 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 80 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 81 * 2.25.0 - eg+: new info request for num SE and num SH 82 * 2.26.0 - r600-eg: fix htile size computation 83 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 84 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 85 * 2.29.0 - R500 FP16 color clear registers 86 * 2.30.0 - fix for FMASK texturing 87 * 2.31.0 - Add fastfb support for rs690 88 * 2.32.0 - new info request for rings working 89 * 2.33.0 - Add SI tiling mode array query 90 * 2.34.0 - Add CIK tiling mode array query 91 * 2.35.0 - Add CIK macrotile mode array query 92 * 2.36.0 - Fix CIK DCE tiling setup 93 * 2.37.0 - allow GS ring setup on r6xx/r7xx 94 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 95 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 96 * 2.39.0 - Add INFO query for number of active CUs 97 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 98 * CS to GPU on >= r600 99 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 100 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 101 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 102 * 2.44.0 - SET_APPEND_CNT packet3 support 103 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 104 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 105 * 2.47.0 - Add UVD_NO_OP register support 106 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 107 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 108 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 109 */ 110 #define KMS_DRIVER_MAJOR 2 111 #define KMS_DRIVER_MINOR 50 112 #define KMS_DRIVER_PATCHLEVEL 0 113 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 114 void radeon_driver_unload_kms(struct drm_device *dev); 115 void radeon_driver_lastclose_kms(struct drm_device *dev); 116 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 117 void radeon_driver_postclose_kms(struct drm_device *dev, 118 struct drm_file *file_priv); 119 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 120 bool fbcon, bool freeze); 121 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 122 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 123 int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 124 void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 125 void radeon_driver_irq_preinstall_kms(struct drm_device *dev); 126 int radeon_driver_irq_postinstall_kms(struct drm_device *dev); 127 void radeon_driver_irq_uninstall_kms(struct drm_device *dev); 128 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); 129 void radeon_gem_object_free(struct drm_gem_object *obj); 130 int radeon_gem_object_open(struct drm_gem_object *obj, 131 struct drm_file *file_priv); 132 void radeon_gem_object_close(struct drm_gem_object *obj, 133 struct drm_file *file_priv); 134 struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj, 135 int flags); 136 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, 137 unsigned int flags, int *vpos, int *hpos, 138 ktime_t *stime, ktime_t *etime, 139 const struct drm_display_mode *mode); 140 extern bool radeon_is_px(struct drm_device *dev); 141 extern const struct drm_ioctl_desc radeon_ioctls_kms[]; 142 extern int radeon_max_kms_ioctl; 143 int radeon_mmap(struct file *filp, struct vm_area_struct *vma); 144 int radeon_mode_dumb_mmap(struct drm_file *filp, 145 struct drm_device *dev, 146 uint32_t handle, uint64_t *offset_p); 147 int radeon_mode_dumb_create(struct drm_file *file_priv, 148 struct drm_device *dev, 149 struct drm_mode_create_dumb *args); 150 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 151 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev, 152 struct dma_buf_attachment *, 153 struct sg_table *sg); 154 int radeon_gem_prime_pin(struct drm_gem_object *obj); 155 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 156 void *radeon_gem_prime_vmap(struct drm_gem_object *obj); 157 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 158 159 /* atpx handler */ 160 #if defined(CONFIG_VGA_SWITCHEROO) 161 void radeon_register_atpx_handler(void); 162 void radeon_unregister_atpx_handler(void); 163 bool radeon_has_atpx_dgpu_power_cntl(void); 164 bool radeon_is_atpx_hybrid(void); 165 #else 166 static inline void radeon_register_atpx_handler(void) {} 167 static inline void radeon_unregister_atpx_handler(void) {} 168 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 169 static inline bool radeon_is_atpx_hybrid(void) { return false; } 170 #endif 171 172 int radeon_no_wb; 173 int radeon_modeset = -1; 174 int radeon_dynclks = -1; 175 int radeon_r4xx_atom = 0; 176 #ifdef __powerpc__ 177 /* Default to PCI on PowerPC (fdo #95017) */ 178 int radeon_agpmode = -1; 179 #else 180 int radeon_agpmode = 0; 181 #endif 182 int radeon_vram_limit = 0; 183 int radeon_gart_size = -1; /* auto */ 184 int radeon_benchmarking = 0; 185 int radeon_testing = 0; 186 int radeon_connector_table = 0; 187 int radeon_tv = 1; 188 int radeon_audio = -1; 189 int radeon_disp_priority = 0; 190 int radeon_hw_i2c = 0; 191 int radeon_pcie_gen2 = -1; 192 int radeon_msi = -1; 193 int radeon_lockup_timeout = 10000; 194 int radeon_fastfb = 0; 195 int radeon_dpm = -1; 196 int radeon_aspm = -1; 197 int radeon_runtime_pm = -1; 198 int radeon_hard_reset = 0; 199 int radeon_vm_size = 8; 200 int radeon_vm_block_size = -1; 201 int radeon_deep_color = 0; 202 int radeon_use_pflipirq = 2; 203 int radeon_bapm = -1; 204 int radeon_backlight = -1; 205 int radeon_auxch = -1; 206 int radeon_mst = 0; 207 int radeon_uvd = 1; 208 int radeon_vce = 1; 209 210 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 211 module_param_named(no_wb, radeon_no_wb, int, 0444); 212 213 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 214 module_param_named(modeset, radeon_modeset, int, 0400); 215 216 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 217 module_param_named(dynclks, radeon_dynclks, int, 0444); 218 219 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 220 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 221 222 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 223 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 224 225 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 226 module_param_named(agpmode, radeon_agpmode, int, 0444); 227 228 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 229 module_param_named(gartsize, radeon_gart_size, int, 0600); 230 231 MODULE_PARM_DESC(benchmark, "Run benchmark"); 232 module_param_named(benchmark, radeon_benchmarking, int, 0444); 233 234 MODULE_PARM_DESC(test, "Run tests"); 235 module_param_named(test, radeon_testing, int, 0444); 236 237 MODULE_PARM_DESC(connector_table, "Force connector table"); 238 module_param_named(connector_table, radeon_connector_table, int, 0444); 239 240 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 241 module_param_named(tv, radeon_tv, int, 0444); 242 243 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 244 module_param_named(audio, radeon_audio, int, 0444); 245 246 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 247 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 248 249 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 250 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 251 252 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 253 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 254 255 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 256 module_param_named(msi, radeon_msi, int, 0444); 257 258 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 259 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 260 261 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 262 module_param_named(fastfb, radeon_fastfb, int, 0444); 263 264 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 265 module_param_named(dpm, radeon_dpm, int, 0444); 266 267 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 268 module_param_named(aspm, radeon_aspm, int, 0444); 269 270 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 271 module_param_named(runpm, radeon_runtime_pm, int, 0444); 272 273 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 274 module_param_named(hard_reset, radeon_hard_reset, int, 0444); 275 276 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 277 module_param_named(vm_size, radeon_vm_size, int, 0444); 278 279 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 280 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 281 282 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 283 module_param_named(deep_color, radeon_deep_color, int, 0444); 284 285 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 286 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 287 288 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 289 module_param_named(bapm, radeon_bapm, int, 0444); 290 291 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 292 module_param_named(backlight, radeon_backlight, int, 0444); 293 294 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 295 module_param_named(auxch, radeon_auxch, int, 0444); 296 297 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); 298 module_param_named(mst, radeon_mst, int, 0444); 299 300 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 301 module_param_named(uvd, radeon_uvd, int, 0444); 302 303 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 304 module_param_named(vce, radeon_vce, int, 0444); 305 306 int radeon_si_support = 1; 307 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 308 module_param_named(si_support, radeon_si_support, int, 0444); 309 310 int radeon_cik_support = 1; 311 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 312 module_param_named(cik_support, radeon_cik_support, int, 0444); 313 314 static struct pci_device_id pciidlist[] = { 315 radeon_PCI_IDS 316 }; 317 318 MODULE_DEVICE_TABLE(pci, pciidlist); 319 320 static struct drm_driver kms_driver; 321 322 bool radeon_device_is_virtual(void); 323 324 static int radeon_pci_probe(struct pci_dev *pdev, 325 const struct pci_device_id *ent) 326 { 327 unsigned long flags = 0; 328 int ret; 329 330 if (!ent) 331 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 332 333 flags = ent->driver_data; 334 335 if (!radeon_si_support) { 336 switch (flags & RADEON_FAMILY_MASK) { 337 case CHIP_TAHITI: 338 case CHIP_PITCAIRN: 339 case CHIP_VERDE: 340 case CHIP_OLAND: 341 case CHIP_HAINAN: 342 dev_info(&pdev->dev, 343 "SI support disabled by module param\n"); 344 return -ENODEV; 345 } 346 } 347 if (!radeon_cik_support) { 348 switch (flags & RADEON_FAMILY_MASK) { 349 case CHIP_KAVERI: 350 case CHIP_BONAIRE: 351 case CHIP_HAWAII: 352 case CHIP_KABINI: 353 case CHIP_MULLINS: 354 dev_info(&pdev->dev, 355 "CIK support disabled by module param\n"); 356 return -ENODEV; 357 } 358 } 359 360 if (vga_switcheroo_client_probe_defer(pdev)) 361 return -EPROBE_DEFER; 362 363 /* Get rid of things like offb */ 364 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb"); 365 if (ret) 366 return ret; 367 368 return drm_get_pci_dev(pdev, ent, &kms_driver); 369 } 370 371 static void 372 radeon_pci_remove(struct pci_dev *pdev) 373 { 374 struct drm_device *dev = pci_get_drvdata(pdev); 375 376 drm_put_dev(dev); 377 } 378 379 static void 380 radeon_pci_shutdown(struct pci_dev *pdev) 381 { 382 /* if we are running in a VM, make sure the device 383 * torn down properly on reboot/shutdown 384 */ 385 if (radeon_device_is_virtual()) 386 radeon_pci_remove(pdev); 387 388 #ifdef CONFIG_PPC64 389 /* 390 * Some adapters need to be suspended before a 391 * shutdown occurs in order to prevent an error 392 * during kexec. 393 * Make this power specific becauase it breaks 394 * some non-power boards. 395 */ 396 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 397 #endif 398 } 399 400 static int radeon_pmops_suspend(struct device *dev) 401 { 402 struct drm_device *drm_dev = dev_get_drvdata(dev); 403 return radeon_suspend_kms(drm_dev, true, true, false); 404 } 405 406 static int radeon_pmops_resume(struct device *dev) 407 { 408 struct drm_device *drm_dev = dev_get_drvdata(dev); 409 410 /* GPU comes up enabled by the bios on resume */ 411 if (radeon_is_px(drm_dev)) { 412 pm_runtime_disable(dev); 413 pm_runtime_set_active(dev); 414 pm_runtime_enable(dev); 415 } 416 417 return radeon_resume_kms(drm_dev, true, true); 418 } 419 420 static int radeon_pmops_freeze(struct device *dev) 421 { 422 struct drm_device *drm_dev = dev_get_drvdata(dev); 423 return radeon_suspend_kms(drm_dev, false, true, true); 424 } 425 426 static int radeon_pmops_thaw(struct device *dev) 427 { 428 struct drm_device *drm_dev = dev_get_drvdata(dev); 429 return radeon_resume_kms(drm_dev, false, true); 430 } 431 432 static int radeon_pmops_runtime_suspend(struct device *dev) 433 { 434 struct pci_dev *pdev = to_pci_dev(dev); 435 struct drm_device *drm_dev = pci_get_drvdata(pdev); 436 int ret; 437 438 if (!radeon_is_px(drm_dev)) { 439 pm_runtime_forbid(dev); 440 return -EBUSY; 441 } 442 443 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 444 drm_kms_helper_poll_disable(drm_dev); 445 446 ret = radeon_suspend_kms(drm_dev, false, false, false); 447 pci_save_state(pdev); 448 pci_disable_device(pdev); 449 pci_ignore_hotplug(pdev); 450 if (radeon_is_atpx_hybrid()) 451 pci_set_power_state(pdev, PCI_D3cold); 452 else if (!radeon_has_atpx_dgpu_power_cntl()) 453 pci_set_power_state(pdev, PCI_D3hot); 454 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 455 456 return 0; 457 } 458 459 static int radeon_pmops_runtime_resume(struct device *dev) 460 { 461 struct pci_dev *pdev = to_pci_dev(dev); 462 struct drm_device *drm_dev = pci_get_drvdata(pdev); 463 int ret; 464 465 if (!radeon_is_px(drm_dev)) 466 return -EINVAL; 467 468 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 469 470 if (radeon_is_atpx_hybrid() || 471 !radeon_has_atpx_dgpu_power_cntl()) 472 pci_set_power_state(pdev, PCI_D0); 473 pci_restore_state(pdev); 474 ret = pci_enable_device(pdev); 475 if (ret) 476 return ret; 477 pci_set_master(pdev); 478 479 ret = radeon_resume_kms(drm_dev, false, false); 480 drm_kms_helper_poll_enable(drm_dev); 481 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 482 return 0; 483 } 484 485 static int radeon_pmops_runtime_idle(struct device *dev) 486 { 487 struct drm_device *drm_dev = dev_get_drvdata(dev); 488 struct drm_crtc *crtc; 489 490 if (!radeon_is_px(drm_dev)) { 491 pm_runtime_forbid(dev); 492 return -EBUSY; 493 } 494 495 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 496 if (crtc->enabled) { 497 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 498 return -EBUSY; 499 } 500 } 501 502 pm_runtime_mark_last_busy(dev); 503 pm_runtime_autosuspend(dev); 504 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 505 return 1; 506 } 507 508 long radeon_drm_ioctl(struct file *filp, 509 unsigned int cmd, unsigned long arg) 510 { 511 struct drm_file *file_priv = filp->private_data; 512 struct drm_device *dev; 513 long ret; 514 dev = file_priv->minor->dev; 515 ret = pm_runtime_get_sync(dev->dev); 516 if (ret < 0) 517 return ret; 518 519 ret = drm_ioctl(filp, cmd, arg); 520 521 pm_runtime_mark_last_busy(dev->dev); 522 pm_runtime_put_autosuspend(dev->dev); 523 return ret; 524 } 525 526 #ifdef CONFIG_COMPAT 527 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 528 { 529 unsigned int nr = DRM_IOCTL_NR(cmd); 530 int ret; 531 532 if (nr < DRM_COMMAND_BASE) 533 return drm_compat_ioctl(filp, cmd, arg); 534 535 ret = radeon_drm_ioctl(filp, cmd, arg); 536 537 return ret; 538 } 539 #endif 540 541 static const struct dev_pm_ops radeon_pm_ops = { 542 .suspend = radeon_pmops_suspend, 543 .resume = radeon_pmops_resume, 544 .freeze = radeon_pmops_freeze, 545 .thaw = radeon_pmops_thaw, 546 .poweroff = radeon_pmops_freeze, 547 .restore = radeon_pmops_resume, 548 .runtime_suspend = radeon_pmops_runtime_suspend, 549 .runtime_resume = radeon_pmops_runtime_resume, 550 .runtime_idle = radeon_pmops_runtime_idle, 551 }; 552 553 static const struct file_operations radeon_driver_kms_fops = { 554 .owner = THIS_MODULE, 555 .open = drm_open, 556 .release = drm_release, 557 .unlocked_ioctl = radeon_drm_ioctl, 558 .mmap = radeon_mmap, 559 .poll = drm_poll, 560 .read = drm_read, 561 #ifdef CONFIG_COMPAT 562 .compat_ioctl = radeon_kms_compat_ioctl, 563 #endif 564 }; 565 566 static bool 567 radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 568 bool in_vblank_irq, int *vpos, int *hpos, 569 ktime_t *stime, ktime_t *etime, 570 const struct drm_display_mode *mode) 571 { 572 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 573 stime, etime, mode); 574 } 575 576 static struct drm_driver kms_driver = { 577 .driver_features = 578 DRIVER_USE_AGP | DRIVER_GEM | DRIVER_RENDER, 579 .load = radeon_driver_load_kms, 580 .open = radeon_driver_open_kms, 581 .postclose = radeon_driver_postclose_kms, 582 .lastclose = radeon_driver_lastclose_kms, 583 .unload = radeon_driver_unload_kms, 584 .get_vblank_counter = radeon_get_vblank_counter_kms, 585 .enable_vblank = radeon_enable_vblank_kms, 586 .disable_vblank = radeon_disable_vblank_kms, 587 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 588 .get_scanout_position = radeon_get_crtc_scanout_position, 589 .irq_preinstall = radeon_driver_irq_preinstall_kms, 590 .irq_postinstall = radeon_driver_irq_postinstall_kms, 591 .irq_uninstall = radeon_driver_irq_uninstall_kms, 592 .irq_handler = radeon_driver_irq_handler_kms, 593 .ioctls = radeon_ioctls_kms, 594 .gem_free_object_unlocked = radeon_gem_object_free, 595 .gem_open_object = radeon_gem_object_open, 596 .gem_close_object = radeon_gem_object_close, 597 .dumb_create = radeon_mode_dumb_create, 598 .dumb_map_offset = radeon_mode_dumb_mmap, 599 .fops = &radeon_driver_kms_fops, 600 601 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 602 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 603 .gem_prime_export = radeon_gem_prime_export, 604 .gem_prime_pin = radeon_gem_prime_pin, 605 .gem_prime_unpin = radeon_gem_prime_unpin, 606 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, 607 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 608 .gem_prime_vmap = radeon_gem_prime_vmap, 609 .gem_prime_vunmap = radeon_gem_prime_vunmap, 610 611 .name = DRIVER_NAME, 612 .desc = DRIVER_DESC, 613 .date = DRIVER_DATE, 614 .major = KMS_DRIVER_MAJOR, 615 .minor = KMS_DRIVER_MINOR, 616 .patchlevel = KMS_DRIVER_PATCHLEVEL, 617 }; 618 619 static struct drm_driver *driver; 620 static struct pci_driver *pdriver; 621 622 static struct pci_driver radeon_kms_pci_driver = { 623 .name = DRIVER_NAME, 624 .id_table = pciidlist, 625 .probe = radeon_pci_probe, 626 .remove = radeon_pci_remove, 627 .shutdown = radeon_pci_shutdown, 628 .driver.pm = &radeon_pm_ops, 629 }; 630 631 static int __init radeon_init(void) 632 { 633 if (vgacon_text_force() && radeon_modeset == -1) { 634 DRM_INFO("VGACON disable radeon kernel modesetting.\n"); 635 radeon_modeset = 0; 636 } 637 /* set to modesetting by default if not nomodeset */ 638 if (radeon_modeset == -1) 639 radeon_modeset = 1; 640 641 if (radeon_modeset == 1) { 642 DRM_INFO("radeon kernel modesetting enabled.\n"); 643 driver = &kms_driver; 644 pdriver = &radeon_kms_pci_driver; 645 driver->driver_features |= DRIVER_MODESET; 646 driver->num_ioctls = radeon_max_kms_ioctl; 647 radeon_register_atpx_handler(); 648 649 } else { 650 DRM_ERROR("No UMS support in radeon module!\n"); 651 return -EINVAL; 652 } 653 654 return pci_register_driver(pdriver); 655 } 656 657 static void __exit radeon_exit(void) 658 { 659 pci_unregister_driver(pdriver); 660 radeon_unregister_atpx_handler(); 661 mmu_notifier_synchronize(); 662 } 663 664 module_init(radeon_init); 665 module_exit(radeon_exit); 666 667 MODULE_AUTHOR(DRIVER_AUTHOR); 668 MODULE_DESCRIPTION(DRIVER_DESC); 669 MODULE_LICENSE("GPL and additional rights"); 670