1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <drm/drm_atomic_state_helper.h> 7 8 #include "intel_bw.h" 9 #include "intel_display_types.h" 10 #include "intel_sideband.h" 11 12 /* Parameters for Qclk Geyserville (QGV) */ 13 struct intel_qgv_point { 14 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; 15 }; 16 17 struct intel_qgv_info { 18 struct intel_qgv_point points[I915_NUM_QGV_POINTS]; 19 u8 num_points; 20 u8 num_channels; 21 u8 t_bl; 22 enum intel_dram_type dram_type; 23 }; 24 25 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, 26 struct intel_qgv_info *qi) 27 { 28 u32 val = 0; 29 int ret; 30 31 ret = sandybridge_pcode_read(dev_priv, 32 ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 33 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, 34 &val, NULL); 35 if (ret) 36 return ret; 37 38 if (IS_GEN(dev_priv, 12)) { 39 switch (val & 0xf) { 40 case 0: 41 qi->dram_type = INTEL_DRAM_DDR4; 42 break; 43 case 3: 44 qi->dram_type = INTEL_DRAM_LPDDR4; 45 break; 46 case 4: 47 qi->dram_type = INTEL_DRAM_DDR3; 48 break; 49 case 5: 50 qi->dram_type = INTEL_DRAM_LPDDR3; 51 break; 52 default: 53 MISSING_CASE(val & 0xf); 54 break; 55 } 56 } else if (IS_GEN(dev_priv, 11)) { 57 switch (val & 0xf) { 58 case 0: 59 qi->dram_type = INTEL_DRAM_DDR4; 60 break; 61 case 1: 62 qi->dram_type = INTEL_DRAM_DDR3; 63 break; 64 case 2: 65 qi->dram_type = INTEL_DRAM_LPDDR3; 66 break; 67 case 3: 68 qi->dram_type = INTEL_DRAM_LPDDR4; 69 break; 70 default: 71 MISSING_CASE(val & 0xf); 72 break; 73 } 74 } else { 75 MISSING_CASE(INTEL_GEN(dev_priv)); 76 qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */ 77 } 78 79 qi->num_channels = (val & 0xf0) >> 4; 80 qi->num_points = (val & 0xf00) >> 8; 81 82 if (IS_GEN(dev_priv, 12)) 83 qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16; 84 else if (IS_GEN(dev_priv, 11)) 85 qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8; 86 87 return 0; 88 } 89 90 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, 91 struct intel_qgv_point *sp, 92 int point) 93 { 94 u32 val = 0, val2 = 0; 95 int ret; 96 97 ret = sandybridge_pcode_read(dev_priv, 98 ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 99 ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point), 100 &val, &val2); 101 if (ret) 102 return ret; 103 104 sp->dclk = val & 0xffff; 105 sp->t_rp = (val & 0xff0000) >> 16; 106 sp->t_rcd = (val & 0xff000000) >> 24; 107 108 sp->t_rdpre = val2 & 0xff; 109 sp->t_ras = (val2 & 0xff00) >> 8; 110 111 sp->t_rc = sp->t_rp + sp->t_ras; 112 113 return 0; 114 } 115 116 static int icl_get_qgv_points(struct drm_i915_private *dev_priv, 117 struct intel_qgv_info *qi) 118 { 119 int i, ret; 120 121 ret = icl_pcode_read_mem_global_info(dev_priv, qi); 122 if (ret) 123 return ret; 124 125 if (drm_WARN_ON(&dev_priv->drm, 126 qi->num_points > ARRAY_SIZE(qi->points))) 127 qi->num_points = ARRAY_SIZE(qi->points); 128 129 for (i = 0; i < qi->num_points; i++) { 130 struct intel_qgv_point *sp = &qi->points[i]; 131 132 ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i); 133 if (ret) 134 return ret; 135 136 drm_dbg_kms(&dev_priv->drm, 137 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", 138 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras, 139 sp->t_rcd, sp->t_rc); 140 } 141 142 return 0; 143 } 144 145 static int icl_calc_bw(int dclk, int num, int den) 146 { 147 /* multiples of 16.666MHz (100/6) */ 148 return DIV_ROUND_CLOSEST(num * dclk * 100, den * 6); 149 } 150 151 static int icl_sagv_max_dclk(const struct intel_qgv_info *qi) 152 { 153 u16 dclk = 0; 154 int i; 155 156 for (i = 0; i < qi->num_points; i++) 157 dclk = max(dclk, qi->points[i].dclk); 158 159 return dclk; 160 } 161 162 struct intel_sa_info { 163 u16 displayrtids; 164 u8 deburst, deprogbwlimit; 165 }; 166 167 static const struct intel_sa_info icl_sa_info = { 168 .deburst = 8, 169 .deprogbwlimit = 25, /* GB/s */ 170 .displayrtids = 128, 171 }; 172 173 static const struct intel_sa_info tgl_sa_info = { 174 .deburst = 16, 175 .deprogbwlimit = 34, /* GB/s */ 176 .displayrtids = 256, 177 }; 178 179 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) 180 { 181 struct intel_qgv_info qi = {}; 182 bool is_y_tile = true; /* assume y tile may be used */ 183 int num_channels; 184 int deinterleave; 185 int ipqdepth, ipqdepthpch; 186 int dclk_max; 187 int maxdebw; 188 int i, ret; 189 190 ret = icl_get_qgv_points(dev_priv, &qi); 191 if (ret) { 192 drm_dbg_kms(&dev_priv->drm, 193 "Failed to get memory subsystem information, ignoring bandwidth limits"); 194 return ret; 195 } 196 num_channels = qi.num_channels; 197 198 deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); 199 dclk_max = icl_sagv_max_dclk(&qi); 200 201 ipqdepthpch = 16; 202 203 maxdebw = min(sa->deprogbwlimit * 1000, 204 icl_calc_bw(dclk_max, 16, 1) * 6 / 10); /* 60% */ 205 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); 206 207 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { 208 struct intel_bw_info *bi = &dev_priv->max_bw[i]; 209 int clpchgroup; 210 int j; 211 212 clpchgroup = (sa->deburst * deinterleave / num_channels) << i; 213 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; 214 215 bi->num_qgv_points = qi.num_points; 216 217 for (j = 0; j < qi.num_points; j++) { 218 const struct intel_qgv_point *sp = &qi.points[j]; 219 int ct, bw; 220 221 /* 222 * Max row cycle time 223 * 224 * FIXME what is the logic behind the 225 * assumed burst length? 226 */ 227 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + 228 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); 229 bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct); 230 231 bi->deratedbw[j] = min(maxdebw, 232 bw * 9 / 10); /* 90% */ 233 234 drm_dbg_kms(&dev_priv->drm, 235 "BW%d / QGV %d: num_planes=%d deratedbw=%u\n", 236 i, j, bi->num_planes, bi->deratedbw[j]); 237 } 238 239 if (bi->num_planes == 1) 240 break; 241 } 242 243 return 0; 244 } 245 246 static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, 247 int num_planes, int qgv_point) 248 { 249 int i; 250 251 for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { 252 const struct intel_bw_info *bi = 253 &dev_priv->max_bw[i]; 254 255 /* 256 * Pcode will not expose all QGV points when 257 * SAGV is forced to off/min/med/max. 258 */ 259 if (qgv_point >= bi->num_qgv_points) 260 return UINT_MAX; 261 262 if (num_planes >= bi->num_planes) 263 return bi->deratedbw[qgv_point]; 264 } 265 266 return 0; 267 } 268 269 void intel_bw_init_hw(struct drm_i915_private *dev_priv) 270 { 271 if (!HAS_DISPLAY(dev_priv)) 272 return; 273 274 if (IS_GEN(dev_priv, 12)) 275 icl_get_bw_info(dev_priv, &tgl_sa_info); 276 else if (IS_GEN(dev_priv, 11)) 277 icl_get_bw_info(dev_priv, &icl_sa_info); 278 } 279 280 static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, 281 int num_planes) 282 { 283 if (INTEL_GEN(dev_priv) >= 11) { 284 /* 285 * Any bw group has same amount of QGV points 286 */ 287 const struct intel_bw_info *bi = 288 &dev_priv->max_bw[0]; 289 unsigned int min_bw = UINT_MAX; 290 int i; 291 292 /* 293 * FIXME with SAGV disabled maybe we can assume 294 * point 1 will always be used? Seems to match 295 * the behaviour observed in the wild. 296 */ 297 for (i = 0; i < bi->num_qgv_points; i++) { 298 unsigned int bw = icl_max_bw(dev_priv, num_planes, i); 299 300 min_bw = min(bw, min_bw); 301 } 302 return min_bw; 303 } else { 304 return UINT_MAX; 305 } 306 } 307 308 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) 309 { 310 /* 311 * We assume cursors are small enough 312 * to not not cause bandwidth problems. 313 */ 314 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); 315 } 316 317 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state) 318 { 319 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 320 unsigned int data_rate = 0; 321 enum plane_id plane_id; 322 323 for_each_plane_id_on_crtc(crtc, plane_id) { 324 /* 325 * We assume cursors are small enough 326 * to not not cause bandwidth problems. 327 */ 328 if (plane_id == PLANE_CURSOR) 329 continue; 330 331 data_rate += crtc_state->data_rate[plane_id]; 332 } 333 334 return data_rate; 335 } 336 337 void intel_bw_crtc_update(struct intel_bw_state *bw_state, 338 const struct intel_crtc_state *crtc_state) 339 { 340 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 341 342 bw_state->data_rate[crtc->pipe] = 343 intel_bw_crtc_data_rate(crtc_state); 344 bw_state->num_active_planes[crtc->pipe] = 345 intel_bw_crtc_num_active_planes(crtc_state); 346 347 DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n", 348 pipe_name(crtc->pipe), 349 bw_state->data_rate[crtc->pipe], 350 bw_state->num_active_planes[crtc->pipe]); 351 } 352 353 static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv, 354 const struct intel_bw_state *bw_state) 355 { 356 unsigned int num_active_planes = 0; 357 enum pipe pipe; 358 359 for_each_pipe(dev_priv, pipe) 360 num_active_planes += bw_state->num_active_planes[pipe]; 361 362 return num_active_planes; 363 } 364 365 static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, 366 const struct intel_bw_state *bw_state) 367 { 368 unsigned int data_rate = 0; 369 enum pipe pipe; 370 371 for_each_pipe(dev_priv, pipe) 372 data_rate += bw_state->data_rate[pipe]; 373 374 return data_rate; 375 } 376 377 static struct intel_bw_state * 378 intel_atomic_get_bw_state(struct intel_atomic_state *state) 379 { 380 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 381 struct intel_global_state *bw_state; 382 383 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj); 384 if (IS_ERR(bw_state)) 385 return ERR_CAST(bw_state); 386 387 return to_intel_bw_state(bw_state); 388 } 389 390 int intel_bw_atomic_check(struct intel_atomic_state *state) 391 { 392 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 393 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 394 struct intel_bw_state *bw_state = NULL; 395 unsigned int data_rate, max_data_rate; 396 unsigned int num_active_planes; 397 struct intel_crtc *crtc; 398 int i, ret; 399 400 /* FIXME earlier gens need some checks too */ 401 if (INTEL_GEN(dev_priv) < 11) 402 return 0; 403 404 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 405 new_crtc_state, i) { 406 unsigned int old_data_rate = 407 intel_bw_crtc_data_rate(old_crtc_state); 408 unsigned int new_data_rate = 409 intel_bw_crtc_data_rate(new_crtc_state); 410 unsigned int old_active_planes = 411 intel_bw_crtc_num_active_planes(old_crtc_state); 412 unsigned int new_active_planes = 413 intel_bw_crtc_num_active_planes(new_crtc_state); 414 415 /* 416 * Avoid locking the bw state when 417 * nothing significant has changed. 418 */ 419 if (old_data_rate == new_data_rate && 420 old_active_planes == new_active_planes) 421 continue; 422 423 bw_state = intel_atomic_get_bw_state(state); 424 if (IS_ERR(bw_state)) 425 return PTR_ERR(bw_state); 426 427 bw_state->data_rate[crtc->pipe] = new_data_rate; 428 bw_state->num_active_planes[crtc->pipe] = new_active_planes; 429 430 drm_dbg_kms(&dev_priv->drm, 431 "pipe %c data rate %u num active planes %u\n", 432 pipe_name(crtc->pipe), 433 bw_state->data_rate[crtc->pipe], 434 bw_state->num_active_planes[crtc->pipe]); 435 } 436 437 if (!bw_state) 438 return 0; 439 440 ret = intel_atomic_lock_global_state(&bw_state->base); 441 if (ret) 442 return ret; 443 444 data_rate = intel_bw_data_rate(dev_priv, bw_state); 445 num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); 446 447 max_data_rate = intel_max_data_rate(dev_priv, num_active_planes); 448 449 data_rate = DIV_ROUND_UP(data_rate, 1000); 450 451 if (data_rate > max_data_rate) { 452 drm_dbg_kms(&dev_priv->drm, 453 "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n", 454 data_rate, max_data_rate, num_active_planes); 455 return -EINVAL; 456 } 457 458 return 0; 459 } 460 461 static struct intel_global_state * 462 intel_bw_duplicate_state(struct intel_global_obj *obj) 463 { 464 struct intel_bw_state *state; 465 466 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 467 if (!state) 468 return NULL; 469 470 return &state->base; 471 } 472 473 static void intel_bw_destroy_state(struct intel_global_obj *obj, 474 struct intel_global_state *state) 475 { 476 kfree(state); 477 } 478 479 static const struct intel_global_state_funcs intel_bw_funcs = { 480 .atomic_duplicate_state = intel_bw_duplicate_state, 481 .atomic_destroy_state = intel_bw_destroy_state, 482 }; 483 484 int intel_bw_init(struct drm_i915_private *dev_priv) 485 { 486 struct intel_bw_state *state; 487 488 state = kzalloc(sizeof(*state), GFP_KERNEL); 489 if (!state) 490 return -ENOMEM; 491 492 intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj, 493 &state->base, &intel_bw_funcs); 494 495 return 0; 496 } 497