1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/acpi.h> 30 #include <linux/pci.h> 31 #include <linux/slab.h> 32 33 #include <drm/drm_device.h> 34 35 #include "atom.h" 36 #include "radeon.h" 37 #include "radeon_reg.h" 38 39 /* 40 * BIOS. 41 */ 42 43 /* If you boot an IGP board with a discrete card as the primary, 44 * the IGP rom is not accessible via the rom bar as the IGP rom is 45 * part of the system bios. On boot, the system bios puts a 46 * copy of the igp rom at the start of vram if a discrete card is 47 * present. 48 */ 49 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 50 { 51 uint8_t __iomem *bios; 52 resource_size_t vram_base; 53 resource_size_t size = 256 * 1024; /* ??? */ 54 55 if (!(rdev->flags & RADEON_IS_IGP)) 56 if (!radeon_card_posted(rdev)) 57 return false; 58 59 rdev->bios = NULL; 60 vram_base = pci_resource_start(rdev->pdev, 0); 61 bios = ioremap(vram_base, size); 62 if (!bios) { 63 return false; 64 } 65 66 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 67 iounmap(bios); 68 return false; 69 } 70 rdev->bios = kmalloc(size, GFP_KERNEL); 71 if (rdev->bios == NULL) { 72 iounmap(bios); 73 return false; 74 } 75 memcpy_fromio(rdev->bios, bios, size); 76 iounmap(bios); 77 return true; 78 } 79 80 static bool radeon_read_bios(struct radeon_device *rdev) 81 { 82 uint8_t __iomem *bios, val1, val2; 83 size_t size; 84 85 rdev->bios = NULL; 86 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 87 bios = pci_map_rom(rdev->pdev, &size); 88 if (!bios) { 89 return false; 90 } 91 92 val1 = readb(&bios[0]); 93 val2 = readb(&bios[1]); 94 95 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 96 pci_unmap_rom(rdev->pdev, bios); 97 return false; 98 } 99 rdev->bios = kzalloc(size, GFP_KERNEL); 100 if (rdev->bios == NULL) { 101 pci_unmap_rom(rdev->pdev, bios); 102 return false; 103 } 104 memcpy_fromio(rdev->bios, bios, size); 105 pci_unmap_rom(rdev->pdev, bios); 106 return true; 107 } 108 109 static bool radeon_read_platform_bios(struct radeon_device *rdev) 110 { 111 uint8_t __iomem *bios; 112 size_t size; 113 114 rdev->bios = NULL; 115 116 bios = pci_platform_rom(rdev->pdev, &size); 117 if (!bios) { 118 return false; 119 } 120 121 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 122 return false; 123 } 124 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 125 if (rdev->bios == NULL) { 126 return false; 127 } 128 129 return true; 130 } 131 132 #ifdef CONFIG_ACPI 133 /* ATRM is used to get the BIOS on the discrete cards in 134 * dual-gpu systems. 135 */ 136 /* retrieve the ROM in 4k blocks */ 137 #define ATRM_BIOS_PAGE 4096 138 /** 139 * radeon_atrm_call - fetch a chunk of the vbios 140 * 141 * @atrm_handle: acpi ATRM handle 142 * @bios: vbios image pointer 143 * @offset: offset of vbios image data to fetch 144 * @len: length of vbios image data to fetch 145 * 146 * Executes ATRM to fetch a chunk of the discrete 147 * vbios image on PX systems (all asics). 148 * Returns the length of the buffer fetched. 149 */ 150 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 151 int offset, int len) 152 { 153 acpi_status status; 154 union acpi_object atrm_arg_elements[2], *obj; 155 struct acpi_object_list atrm_arg; 156 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 157 158 atrm_arg.count = 2; 159 atrm_arg.pointer = &atrm_arg_elements[0]; 160 161 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 162 atrm_arg_elements[0].integer.value = offset; 163 164 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 165 atrm_arg_elements[1].integer.value = len; 166 167 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 168 if (ACPI_FAILURE(status)) { 169 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 170 return -ENODEV; 171 } 172 173 obj = (union acpi_object *)buffer.pointer; 174 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 175 len = obj->buffer.length; 176 kfree(buffer.pointer); 177 return len; 178 } 179 180 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 181 { 182 int ret; 183 int size = 256 * 1024; 184 int i; 185 struct pci_dev *pdev = NULL; 186 acpi_handle dhandle, atrm_handle; 187 acpi_status status; 188 bool found = false; 189 190 /* ATRM is for the discrete card only */ 191 if (rdev->flags & RADEON_IS_IGP) 192 return false; 193 194 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 195 dhandle = ACPI_HANDLE(&pdev->dev); 196 if (!dhandle) 197 continue; 198 199 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 200 if (!ACPI_FAILURE(status)) { 201 found = true; 202 break; 203 } 204 } 205 206 if (!found) { 207 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 208 dhandle = ACPI_HANDLE(&pdev->dev); 209 if (!dhandle) 210 continue; 211 212 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 213 if (!ACPI_FAILURE(status)) { 214 found = true; 215 break; 216 } 217 } 218 } 219 220 if (!found) 221 return false; 222 223 rdev->bios = kmalloc(size, GFP_KERNEL); 224 if (!rdev->bios) { 225 DRM_ERROR("Unable to allocate bios\n"); 226 return false; 227 } 228 229 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 230 ret = radeon_atrm_call(atrm_handle, 231 rdev->bios, 232 (i * ATRM_BIOS_PAGE), 233 ATRM_BIOS_PAGE); 234 if (ret < ATRM_BIOS_PAGE) 235 break; 236 } 237 238 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 239 kfree(rdev->bios); 240 return false; 241 } 242 return true; 243 } 244 #else 245 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 246 { 247 return false; 248 } 249 #endif 250 251 static bool ni_read_disabled_bios(struct radeon_device *rdev) 252 { 253 u32 bus_cntl; 254 u32 d1vga_control; 255 u32 d2vga_control; 256 u32 vga_render_control; 257 u32 rom_cntl; 258 bool r; 259 260 bus_cntl = RREG32(R600_BUS_CNTL); 261 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 262 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 263 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 264 rom_cntl = RREG32(R600_ROM_CNTL); 265 266 /* enable the rom */ 267 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 268 if (!ASIC_IS_NODCE(rdev)) { 269 /* Disable VGA mode */ 270 WREG32(AVIVO_D1VGA_CONTROL, 271 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 272 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 273 WREG32(AVIVO_D2VGA_CONTROL, 274 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 275 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 276 WREG32(AVIVO_VGA_RENDER_CONTROL, 277 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 278 } 279 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 280 281 r = radeon_read_bios(rdev); 282 283 /* restore regs */ 284 WREG32(R600_BUS_CNTL, bus_cntl); 285 if (!ASIC_IS_NODCE(rdev)) { 286 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 287 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 288 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 289 } 290 WREG32(R600_ROM_CNTL, rom_cntl); 291 return r; 292 } 293 294 static bool r700_read_disabled_bios(struct radeon_device *rdev) 295 { 296 uint32_t viph_control; 297 uint32_t bus_cntl; 298 uint32_t d1vga_control; 299 uint32_t d2vga_control; 300 uint32_t vga_render_control; 301 uint32_t rom_cntl; 302 uint32_t cg_spll_func_cntl = 0; 303 uint32_t cg_spll_status; 304 bool r; 305 306 viph_control = RREG32(RADEON_VIPH_CONTROL); 307 bus_cntl = RREG32(R600_BUS_CNTL); 308 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 309 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 310 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 311 rom_cntl = RREG32(R600_ROM_CNTL); 312 313 /* disable VIP */ 314 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 315 /* enable the rom */ 316 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 317 /* Disable VGA mode */ 318 WREG32(AVIVO_D1VGA_CONTROL, 319 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 320 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 321 WREG32(AVIVO_D2VGA_CONTROL, 322 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 323 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 324 WREG32(AVIVO_VGA_RENDER_CONTROL, 325 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 326 327 if (rdev->family == CHIP_RV730) { 328 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 329 330 /* enable bypass mode */ 331 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 332 R600_SPLL_BYPASS_EN)); 333 334 /* wait for SPLL_CHG_STATUS to change to 1 */ 335 cg_spll_status = 0; 336 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 337 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 338 339 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 340 } else 341 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 342 343 r = radeon_read_bios(rdev); 344 345 /* restore regs */ 346 if (rdev->family == CHIP_RV730) { 347 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 348 349 /* wait for SPLL_CHG_STATUS to change to 1 */ 350 cg_spll_status = 0; 351 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 352 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 353 } 354 WREG32(RADEON_VIPH_CONTROL, viph_control); 355 WREG32(R600_BUS_CNTL, bus_cntl); 356 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 357 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 358 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 359 WREG32(R600_ROM_CNTL, rom_cntl); 360 return r; 361 } 362 363 static bool r600_read_disabled_bios(struct radeon_device *rdev) 364 { 365 uint32_t viph_control; 366 uint32_t bus_cntl; 367 uint32_t d1vga_control; 368 uint32_t d2vga_control; 369 uint32_t vga_render_control; 370 uint32_t rom_cntl; 371 uint32_t general_pwrmgt; 372 uint32_t low_vid_lower_gpio_cntl; 373 uint32_t medium_vid_lower_gpio_cntl; 374 uint32_t high_vid_lower_gpio_cntl; 375 uint32_t ctxsw_vid_lower_gpio_cntl; 376 uint32_t lower_gpio_enable; 377 bool r; 378 379 viph_control = RREG32(RADEON_VIPH_CONTROL); 380 bus_cntl = RREG32(R600_BUS_CNTL); 381 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 382 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 383 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 384 rom_cntl = RREG32(R600_ROM_CNTL); 385 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 386 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 387 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 388 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 389 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 390 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 391 392 /* disable VIP */ 393 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 394 /* enable the rom */ 395 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 396 /* Disable VGA mode */ 397 WREG32(AVIVO_D1VGA_CONTROL, 398 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 399 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 400 WREG32(AVIVO_D2VGA_CONTROL, 401 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 402 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 403 WREG32(AVIVO_VGA_RENDER_CONTROL, 404 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 405 406 WREG32(R600_ROM_CNTL, 407 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 408 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 409 R600_SCK_OVERWRITE)); 410 411 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 412 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 413 (low_vid_lower_gpio_cntl & ~0x400)); 414 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 415 (medium_vid_lower_gpio_cntl & ~0x400)); 416 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 417 (high_vid_lower_gpio_cntl & ~0x400)); 418 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 419 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 420 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 421 422 r = radeon_read_bios(rdev); 423 424 /* restore regs */ 425 WREG32(RADEON_VIPH_CONTROL, viph_control); 426 WREG32(R600_BUS_CNTL, bus_cntl); 427 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 428 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 429 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 430 WREG32(R600_ROM_CNTL, rom_cntl); 431 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 432 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 433 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 434 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 435 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 436 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 437 return r; 438 } 439 440 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 441 { 442 uint32_t seprom_cntl1; 443 uint32_t viph_control; 444 uint32_t bus_cntl; 445 uint32_t d1vga_control; 446 uint32_t d2vga_control; 447 uint32_t vga_render_control; 448 uint32_t gpiopad_a; 449 uint32_t gpiopad_en; 450 uint32_t gpiopad_mask; 451 bool r; 452 453 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 454 viph_control = RREG32(RADEON_VIPH_CONTROL); 455 bus_cntl = RREG32(RV370_BUS_CNTL); 456 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 457 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 458 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 459 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 460 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 461 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 462 463 WREG32(RADEON_SEPROM_CNTL1, 464 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 465 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 466 WREG32(RADEON_GPIOPAD_A, 0); 467 WREG32(RADEON_GPIOPAD_EN, 0); 468 WREG32(RADEON_GPIOPAD_MASK, 0); 469 470 /* disable VIP */ 471 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 472 473 /* enable the rom */ 474 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 475 476 /* Disable VGA mode */ 477 WREG32(AVIVO_D1VGA_CONTROL, 478 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 479 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 480 WREG32(AVIVO_D2VGA_CONTROL, 481 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 482 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 483 WREG32(AVIVO_VGA_RENDER_CONTROL, 484 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 485 486 r = radeon_read_bios(rdev); 487 488 /* restore regs */ 489 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 490 WREG32(RADEON_VIPH_CONTROL, viph_control); 491 WREG32(RV370_BUS_CNTL, bus_cntl); 492 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 493 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 494 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 495 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 496 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 497 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 498 return r; 499 } 500 501 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 502 { 503 uint32_t seprom_cntl1; 504 uint32_t viph_control; 505 uint32_t bus_cntl; 506 uint32_t crtc_gen_cntl; 507 uint32_t crtc2_gen_cntl; 508 uint32_t crtc_ext_cntl; 509 uint32_t fp2_gen_cntl; 510 bool r; 511 512 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 513 viph_control = RREG32(RADEON_VIPH_CONTROL); 514 if (rdev->flags & RADEON_IS_PCIE) 515 bus_cntl = RREG32(RV370_BUS_CNTL); 516 else 517 bus_cntl = RREG32(RADEON_BUS_CNTL); 518 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 519 crtc2_gen_cntl = 0; 520 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 521 fp2_gen_cntl = 0; 522 523 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 524 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 525 } 526 527 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 528 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 529 } 530 531 WREG32(RADEON_SEPROM_CNTL1, 532 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 533 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 534 535 /* disable VIP */ 536 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 537 538 /* enable the rom */ 539 if (rdev->flags & RADEON_IS_PCIE) 540 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 541 else 542 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 543 544 /* Turn off mem requests and CRTC for both controllers */ 545 WREG32(RADEON_CRTC_GEN_CNTL, 546 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 547 (RADEON_CRTC_DISP_REQ_EN_B | 548 RADEON_CRTC_EXT_DISP_EN))); 549 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 550 WREG32(RADEON_CRTC2_GEN_CNTL, 551 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 552 RADEON_CRTC2_DISP_REQ_EN_B)); 553 } 554 /* Turn off CRTC */ 555 WREG32(RADEON_CRTC_EXT_CNTL, 556 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 557 (RADEON_CRTC_SYNC_TRISTAT | 558 RADEON_CRTC_DISPLAY_DIS))); 559 560 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 561 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 562 } 563 564 r = radeon_read_bios(rdev); 565 566 /* restore regs */ 567 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 568 WREG32(RADEON_VIPH_CONTROL, viph_control); 569 if (rdev->flags & RADEON_IS_PCIE) 570 WREG32(RV370_BUS_CNTL, bus_cntl); 571 else 572 WREG32(RADEON_BUS_CNTL, bus_cntl); 573 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 574 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 575 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 576 } 577 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 578 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 579 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 580 } 581 return r; 582 } 583 584 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 585 { 586 if (rdev->flags & RADEON_IS_IGP) 587 return igp_read_bios_from_vram(rdev); 588 else if (rdev->family >= CHIP_BARTS) 589 return ni_read_disabled_bios(rdev); 590 else if (rdev->family >= CHIP_RV770) 591 return r700_read_disabled_bios(rdev); 592 else if (rdev->family >= CHIP_R600) 593 return r600_read_disabled_bios(rdev); 594 else if (rdev->family >= CHIP_RS600) 595 return avivo_read_disabled_bios(rdev); 596 else 597 return legacy_read_disabled_bios(rdev); 598 } 599 600 #ifdef CONFIG_ACPI 601 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 602 { 603 struct acpi_table_header *hdr; 604 acpi_size tbl_size; 605 UEFI_ACPI_VFCT *vfct; 606 unsigned offset; 607 608 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 609 return false; 610 tbl_size = hdr->length; 611 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 612 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 613 return false; 614 } 615 616 vfct = (UEFI_ACPI_VFCT *)hdr; 617 offset = vfct->VBIOSImageOffset; 618 619 while (offset < tbl_size) { 620 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 621 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 622 623 offset += sizeof(VFCT_IMAGE_HEADER); 624 if (offset > tbl_size) { 625 DRM_ERROR("ACPI VFCT image header truncated\n"); 626 return false; 627 } 628 629 offset += vhdr->ImageLength; 630 if (offset > tbl_size) { 631 DRM_ERROR("ACPI VFCT image truncated\n"); 632 return false; 633 } 634 635 if (vhdr->ImageLength && 636 vhdr->PCIBus == rdev->pdev->bus->number && 637 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 638 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 639 vhdr->VendorID == rdev->pdev->vendor && 640 vhdr->DeviceID == rdev->pdev->device) { 641 rdev->bios = kmemdup(&vbios->VbiosContent, 642 vhdr->ImageLength, 643 GFP_KERNEL); 644 645 if (!rdev->bios) 646 return false; 647 return true; 648 } 649 } 650 651 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 652 return false; 653 } 654 #else 655 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 656 { 657 return false; 658 } 659 #endif 660 661 bool radeon_get_bios(struct radeon_device *rdev) 662 { 663 bool r; 664 uint16_t tmp; 665 666 r = radeon_atrm_get_bios(rdev); 667 if (!r) 668 r = radeon_acpi_vfct_bios(rdev); 669 if (!r) 670 r = igp_read_bios_from_vram(rdev); 671 if (!r) 672 r = radeon_read_bios(rdev); 673 if (!r) 674 r = radeon_read_disabled_bios(rdev); 675 if (!r) 676 r = radeon_read_platform_bios(rdev); 677 if (!r || rdev->bios == NULL) { 678 DRM_ERROR("Unable to locate a BIOS ROM\n"); 679 rdev->bios = NULL; 680 return false; 681 } 682 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 683 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 684 goto free_bios; 685 } 686 687 tmp = RBIOS16(0x18); 688 if (RBIOS8(tmp + 0x14) != 0x0) { 689 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 690 goto free_bios; 691 } 692 693 rdev->bios_header_start = RBIOS16(0x48); 694 if (!rdev->bios_header_start) { 695 goto free_bios; 696 } 697 tmp = rdev->bios_header_start + 4; 698 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 699 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 700 rdev->is_atom_bios = true; 701 } else { 702 rdev->is_atom_bios = false; 703 } 704 705 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 706 return true; 707 free_bios: 708 kfree(rdev->bios); 709 rdev->bios = NULL; 710 return false; 711 } 712