1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: QCA AR71XX MAC
8
9allOf:
10  - $ref: ethernet-controller.yaml#
11
12maintainers:
13  - Oleksij Rempel <o.rempel@pengutronix.de>
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qca,ar7100-eth   # Atheros AR7100
21              - qca,ar7240-eth   # Atheros AR7240
22              - qca,ar7241-eth   # Atheros AR7241
23              - qca,ar7242-eth   # Atheros AR7242
24              - qca,ar9130-eth   # Atheros AR9130
25              - qca,ar9330-eth   # Atheros AR9330
26              - qca,ar9340-eth   # Atheros AR9340
27              - qca,qca9530-eth  # Qualcomm Atheros QCA9530
28              - qca,qca9550-eth  # Qualcomm Atheros QCA9550
29              - qca,qca9560-eth  # Qualcomm Atheros QCA9560
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  '#address-cells':
38    description: number of address cells for the MDIO bus
39    const: 1
40
41  '#size-cells':
42    description: number of size cells on the MDIO bus
43    const: 0
44
45  clocks:
46    items:
47      - description: MAC main clock
48      - description: MDIO clock
49
50  clock-names:
51    items:
52      - const: eth
53      - const: mdio
54
55  resets:
56    items:
57      - description: MAC reset
58      - description: MDIO reset
59
60  reset-names:
61    items:
62      - const: mac
63      - const: mdio
64
65required:
66  - compatible
67  - reg
68  - interrupts
69  - phy-mode
70  - clocks
71  - clock-names
72  - resets
73  - reset-names
74
75examples:
76  # Lager board
77  - |
78    eth0: ethernet@19000000 {
79        compatible = "qca,ar9330-eth";
80        reg = <0x19000000 0x200>;
81        interrupts = <4>;
82        resets = <&rst 9>, <&rst 22>;
83        reset-names = "mac", "mdio";
84        clocks = <&pll 1>, <&pll 2>;
85        clock-names = "eth", "mdio";
86        qca,ethcfg = <&ethcfg>;
87        phy-mode = "mii";
88        phy-handle = <&phy_port4>;
89    };
90
91    eth1: ethernet@1a000000 {
92        compatible = "qca,ar9330-eth";
93        reg = <0x1a000000 0x200>;
94        interrupts = <5>;
95        resets = <&rst 13>, <&rst 23>;
96        reset-names = "mac", "mdio";
97        clocks = <&pll 1>, <&pll 2>;
98        clock-names = "eth", "mdio";
99
100        phy-mode = "gmii";
101
102        status = "disabled";
103
104        fixed-link {
105            speed = <1000>;
106            full-duplex;
107        };
108
109        mdio {
110            #address-cells = <1>;
111            #size-cells = <0>;
112
113            switch10: switch@10 {
114                #address-cells = <1>;
115                #size-cells = <0>;
116
117                compatible = "qca,ar9331-switch";
118                reg = <0x10>;
119                resets = <&rst 8>;
120                reset-names = "switch";
121
122                interrupt-parent = <&miscintc>;
123                interrupts = <12>;
124
125                interrupt-controller;
126                #interrupt-cells = <1>;
127
128                ports {
129                    #address-cells = <1>;
130                    #size-cells = <0>;
131
132                    switch_port0: port@0 {
133                        reg = <0x0>;
134                        label = "cpu";
135                        ethernet = <&eth1>;
136
137                        phy-mode = "gmii";
138
139                        fixed-link {
140                            speed = <1000>;
141                            full-duplex;
142                        };
143                    };
144
145                    switch_port1: port@1 {
146                        reg = <0x1>;
147                        phy-handle = <&phy_port0>;
148                        phy-mode = "internal";
149
150                        status = "disabled";
151                    };
152
153                    switch_port2: port@2 {
154                        reg = <0x2>;
155                        phy-handle = <&phy_port1>;
156                        phy-mode = "internal";
157
158                        status = "disabled";
159                    };
160
161                    switch_port3: port@3 {
162                        reg = <0x3>;
163                        phy-handle = <&phy_port2>;
164                        phy-mode = "internal";
165
166                        status = "disabled";
167                    };
168
169                    switch_port4: port@4 {
170                        reg = <0x4>;
171                        phy-handle = <&phy_port3>;
172                        phy-mode = "internal";
173
174                        status = "disabled";
175                    };
176                };
177
178                mdio {
179                    #address-cells = <1>;
180                    #size-cells = <0>;
181
182                    interrupt-parent = <&switch10>;
183
184                    phy_port0: phy@0 {
185                        reg = <0x0>;
186                        interrupts = <0>;
187                        status = "disabled";
188                    };
189
190                    phy_port1: phy@1 {
191                        reg = <0x1>;
192                        interrupts = <0>;
193                        status = "disabled";
194                    };
195
196                    phy_port2: phy@2 {
197                        reg = <0x2>;
198                        interrupts = <0>;
199                        status = "disabled";
200                    };
201
202                    phy_port3: phy@3 {
203                        reg = <0x3>;
204                        interrupts = <0>;
205                        status = "disabled";
206                    };
207
208                    phy_port4: phy@4 {
209                        reg = <0x4>;
210                        interrupts = <0>;
211                        status = "disabled";
212                    };
213                };
214            };
215        };
216    };
217