1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car D3 (R8A77995) SoC 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Glider bvba 7 */ 8 9#include <dt-bindings/clock/r8a77995-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a77995-sysc.h> 12 13/ { 14 compatible = "renesas,r8a77995"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* External CAN clock - to be overridden by boards that provide it */ 19 can_clk: can { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <0>; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 a53_0: cpu@0 { 30 compatible = "arm,cortex-a53"; 31 reg = <0x0>; 32 device_type = "cpu"; 33 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 34 next-level-cache = <&L2_CA53>; 35 enable-method = "psci"; 36 }; 37 38 L2_CA53: cache-controller-1 { 39 compatible = "cache"; 40 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 41 cache-unified; 42 cache-level = <2>; 43 }; 44 }; 45 46 extal_clk: extal { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 /* This value must be overridden by the board */ 50 clock-frequency = <0>; 51 }; 52 53 pmu_a53 { 54 compatible = "arm,cortex-a53-pmu"; 55 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 56 }; 57 58 psci { 59 compatible = "arm,psci-1.0", "arm,psci-0.2"; 60 method = "smc"; 61 }; 62 63 scif_clk: scif { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 soc { 70 compatible = "simple-bus"; 71 interrupt-parent = <&gic>; 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 rwdt: watchdog@e6020000 { 77 compatible = "renesas,r8a77995-wdt", 78 "renesas,rcar-gen3-wdt"; 79 reg = <0 0xe6020000 0 0x0c>; 80 clocks = <&cpg CPG_MOD 402>; 81 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 82 resets = <&cpg 402>; 83 status = "disabled"; 84 }; 85 86 gpio0: gpio@e6050000 { 87 compatible = "renesas,gpio-r8a77995", 88 "renesas,rcar-gen3-gpio"; 89 reg = <0 0xe6050000 0 0x50>; 90 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 91 #gpio-cells = <2>; 92 gpio-controller; 93 gpio-ranges = <&pfc 0 0 9>; 94 #interrupt-cells = <2>; 95 interrupt-controller; 96 clocks = <&cpg CPG_MOD 912>; 97 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 98 resets = <&cpg 912>; 99 }; 100 101 gpio1: gpio@e6051000 { 102 compatible = "renesas,gpio-r8a77995", 103 "renesas,rcar-gen3-gpio"; 104 reg = <0 0xe6051000 0 0x50>; 105 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 106 #gpio-cells = <2>; 107 gpio-controller; 108 gpio-ranges = <&pfc 0 32 32>; 109 #interrupt-cells = <2>; 110 interrupt-controller; 111 clocks = <&cpg CPG_MOD 911>; 112 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 113 resets = <&cpg 911>; 114 }; 115 116 gpio2: gpio@e6052000 { 117 compatible = "renesas,gpio-r8a77995", 118 "renesas,rcar-gen3-gpio"; 119 reg = <0 0xe6052000 0 0x50>; 120 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 121 #gpio-cells = <2>; 122 gpio-controller; 123 gpio-ranges = <&pfc 0 64 32>; 124 #interrupt-cells = <2>; 125 interrupt-controller; 126 clocks = <&cpg CPG_MOD 910>; 127 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 128 resets = <&cpg 910>; 129 }; 130 131 gpio3: gpio@e6053000 { 132 compatible = "renesas,gpio-r8a77995", 133 "renesas,rcar-gen3-gpio"; 134 reg = <0 0xe6053000 0 0x50>; 135 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 136 #gpio-cells = <2>; 137 gpio-controller; 138 gpio-ranges = <&pfc 0 96 10>; 139 #interrupt-cells = <2>; 140 interrupt-controller; 141 clocks = <&cpg CPG_MOD 909>; 142 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 143 resets = <&cpg 909>; 144 }; 145 146 gpio4: gpio@e6054000 { 147 compatible = "renesas,gpio-r8a77995", 148 "renesas,rcar-gen3-gpio"; 149 reg = <0 0xe6054000 0 0x50>; 150 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 151 #gpio-cells = <2>; 152 gpio-controller; 153 gpio-ranges = <&pfc 0 128 32>; 154 #interrupt-cells = <2>; 155 interrupt-controller; 156 clocks = <&cpg CPG_MOD 908>; 157 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 158 resets = <&cpg 908>; 159 }; 160 161 gpio5: gpio@e6055000 { 162 compatible = "renesas,gpio-r8a77995", 163 "renesas,rcar-gen3-gpio"; 164 reg = <0 0xe6055000 0 0x50>; 165 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 166 #gpio-cells = <2>; 167 gpio-controller; 168 gpio-ranges = <&pfc 0 160 21>; 169 #interrupt-cells = <2>; 170 interrupt-controller; 171 clocks = <&cpg CPG_MOD 907>; 172 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 173 resets = <&cpg 907>; 174 }; 175 176 gpio6: gpio@e6055400 { 177 compatible = "renesas,gpio-r8a77995", 178 "renesas,rcar-gen3-gpio"; 179 reg = <0 0xe6055400 0 0x50>; 180 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 181 #gpio-cells = <2>; 182 gpio-controller; 183 gpio-ranges = <&pfc 0 192 14>; 184 #interrupt-cells = <2>; 185 interrupt-controller; 186 clocks = <&cpg CPG_MOD 906>; 187 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 188 resets = <&cpg 906>; 189 }; 190 191 pfc: pin-controller@e6060000 { 192 compatible = "renesas,pfc-r8a77995"; 193 reg = <0 0xe6060000 0 0x508>; 194 }; 195 196 cpg: clock-controller@e6150000 { 197 compatible = "renesas,r8a77995-cpg-mssr"; 198 reg = <0 0xe6150000 0 0x1000>; 199 clocks = <&extal_clk>; 200 clock-names = "extal"; 201 #clock-cells = <2>; 202 #power-domain-cells = <0>; 203 #reset-cells = <1>; 204 }; 205 206 rst: reset-controller@e6160000 { 207 compatible = "renesas,r8a77995-rst"; 208 reg = <0 0xe6160000 0 0x0200>; 209 }; 210 211 sysc: system-controller@e6180000 { 212 compatible = "renesas,r8a77995-sysc"; 213 reg = <0 0xe6180000 0 0x0400>; 214 #power-domain-cells = <1>; 215 }; 216 217 thermal: thermal@e6190000 { 218 compatible = "renesas,thermal-r8a77995"; 219 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 220 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&cpg CPG_MOD 522>; 224 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 225 resets = <&cpg 522>; 226 #thermal-sensor-cells = <0>; 227 }; 228 229 intc_ex: interrupt-controller@e61c0000 { 230 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 231 #interrupt-cells = <2>; 232 interrupt-controller; 233 reg = <0 0xe61c0000 0 0x200>; 234 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cpg CPG_MOD 407>; 241 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 242 resets = <&cpg 407>; 243 }; 244 245 i2c0: i2c@e6500000 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "renesas,i2c-r8a77995", 249 "renesas,rcar-gen3-i2c"; 250 reg = <0 0xe6500000 0 0x40>; 251 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&cpg CPG_MOD 931>; 253 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 254 resets = <&cpg 931>; 255 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 256 <&dmac2 0x91>, <&dmac2 0x90>; 257 dma-names = "tx", "rx", "tx", "rx"; 258 i2c-scl-internal-delay-ns = <6>; 259 status = "disabled"; 260 }; 261 262 i2c1: i2c@e6508000 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "renesas,i2c-r8a77995", 266 "renesas,rcar-gen3-i2c"; 267 reg = <0 0xe6508000 0 0x40>; 268 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&cpg CPG_MOD 930>; 270 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 271 resets = <&cpg 930>; 272 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 273 <&dmac2 0x93>, <&dmac2 0x92>; 274 dma-names = "tx", "rx", "tx", "rx"; 275 i2c-scl-internal-delay-ns = <6>; 276 status = "disabled"; 277 }; 278 279 i2c2: i2c@e6510000 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 compatible = "renesas,i2c-r8a77995", 283 "renesas,rcar-gen3-i2c"; 284 reg = <0 0xe6510000 0 0x40>; 285 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cpg CPG_MOD 929>; 287 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 288 resets = <&cpg 929>; 289 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 290 <&dmac2 0x95>, <&dmac2 0x94>; 291 dma-names = "tx", "rx", "tx", "rx"; 292 i2c-scl-internal-delay-ns = <6>; 293 status = "disabled"; 294 }; 295 296 i2c3: i2c@e66d0000 { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 compatible = "renesas,i2c-r8a77995", 300 "renesas,rcar-gen3-i2c"; 301 reg = <0 0xe66d0000 0 0x40>; 302 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&cpg CPG_MOD 928>; 304 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 305 resets = <&cpg 928>; 306 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 307 dma-names = "tx", "rx"; 308 i2c-scl-internal-delay-ns = <6>; 309 status = "disabled"; 310 }; 311 312 hscif0: serial@e6540000 { 313 compatible = "renesas,hscif-r8a77995", 314 "renesas,rcar-gen3-hscif", 315 "renesas,hscif"; 316 reg = <0 0xe6540000 0 0x60>; 317 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&cpg CPG_MOD 520>, 319 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 320 <&scif_clk>; 321 clock-names = "fck", "brg_int", "scif_clk"; 322 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 323 <&dmac2 0x31>, <&dmac2 0x30>; 324 dma-names = "tx", "rx", "tx", "rx"; 325 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 326 resets = <&cpg 520>; 327 status = "disabled"; 328 }; 329 330 hscif3: serial@e66a0000 { 331 compatible = "renesas,hscif-r8a77995", 332 "renesas,rcar-gen3-hscif", 333 "renesas,hscif"; 334 reg = <0 0xe66a0000 0 0x60>; 335 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cpg CPG_MOD 517>, 337 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 338 <&scif_clk>; 339 clock-names = "fck", "brg_int", "scif_clk"; 340 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 341 dma-names = "tx", "rx"; 342 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 343 resets = <&cpg 517>; 344 status = "disabled"; 345 }; 346 347 hsusb: usb@e6590000 { 348 compatible = "renesas,usbhs-r8a77995", 349 "renesas,rcar-gen3-usbhs"; 350 reg = <0 0xe6590000 0 0x200>; 351 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 353 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 354 <&usb_dmac1 0>, <&usb_dmac1 1>; 355 dma-names = "ch0", "ch1", "ch2", "ch3"; 356 renesas,buswait = <11>; 357 phys = <&usb2_phy0 3>; 358 phy-names = "usb"; 359 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 360 resets = <&cpg 704>, <&cpg 703>; 361 status = "disabled"; 362 }; 363 364 usb_dmac0: dma-controller@e65a0000 { 365 compatible = "renesas,r8a77995-usb-dmac", 366 "renesas,usb-dmac"; 367 reg = <0 0xe65a0000 0 0x100>; 368 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-names = "ch0", "ch1"; 371 clocks = <&cpg CPG_MOD 330>; 372 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 373 resets = <&cpg 330>; 374 #dma-cells = <1>; 375 dma-channels = <2>; 376 }; 377 378 usb_dmac1: dma-controller@e65b0000 { 379 compatible = "renesas,r8a77995-usb-dmac", 380 "renesas,usb-dmac"; 381 reg = <0 0xe65b0000 0 0x100>; 382 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 384 interrupt-names = "ch0", "ch1"; 385 clocks = <&cpg CPG_MOD 331>; 386 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 387 resets = <&cpg 331>; 388 #dma-cells = <1>; 389 dma-channels = <2>; 390 }; 391 392 arm_cc630p: crypto@e6601000 { 393 compatible = "arm,cryptocell-630p-ree"; 394 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 395 reg = <0x0 0xe6601000 0 0x1000>; 396 clocks = <&cpg CPG_MOD 229>; 397 resets = <&cpg 229>; 398 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 399 }; 400 401 canfd: can@e66c0000 { 402 compatible = "renesas,r8a77995-canfd", 403 "renesas,rcar-gen3-canfd"; 404 reg = <0 0xe66c0000 0 0x8000>; 405 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&cpg CPG_MOD 914>, 408 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 409 <&can_clk>; 410 clock-names = "fck", "canfd", "can_clk"; 411 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 412 assigned-clock-rates = <40000000>; 413 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 414 resets = <&cpg 914>; 415 status = "disabled"; 416 417 channel0 { 418 status = "disabled"; 419 }; 420 421 channel1 { 422 status = "disabled"; 423 }; 424 }; 425 426 dmac0: dma-controller@e6700000 { 427 compatible = "renesas,dmac-r8a77995", 428 "renesas,rcar-dmac"; 429 reg = <0 0xe6700000 0 0x10000>; 430 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 439 interrupt-names = "error", 440 "ch0", "ch1", "ch2", "ch3", 441 "ch4", "ch5", "ch6", "ch7"; 442 clocks = <&cpg CPG_MOD 219>; 443 clock-names = "fck"; 444 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 445 resets = <&cpg 219>; 446 #dma-cells = <1>; 447 dma-channels = <8>; 448 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 449 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 450 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 451 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; 452 }; 453 454 dmac1: dma-controller@e7300000 { 455 compatible = "renesas,dmac-r8a77995", 456 "renesas,rcar-dmac"; 457 reg = <0 0xe7300000 0 0x10000>; 458 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-names = "error", 468 "ch0", "ch1", "ch2", "ch3", 469 "ch4", "ch5", "ch6", "ch7"; 470 clocks = <&cpg CPG_MOD 218>; 471 clock-names = "fck"; 472 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 473 resets = <&cpg 218>; 474 #dma-cells = <1>; 475 dma-channels = <8>; 476 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 477 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 478 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 479 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 480 }; 481 482 dmac2: dma-controller@e7310000 { 483 compatible = "renesas,dmac-r8a77995", 484 "renesas,rcar-dmac"; 485 reg = <0 0xe7310000 0 0x10000>; 486 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "error", 496 "ch0", "ch1", "ch2", "ch3", 497 "ch4", "ch5", "ch6", "ch7"; 498 clocks = <&cpg CPG_MOD 217>; 499 clock-names = "fck"; 500 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 501 resets = <&cpg 217>; 502 #dma-cells = <1>; 503 dma-channels = <8>; 504 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 505 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 506 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 507 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 508 }; 509 510 ipmmu_ds0: iommu@e6740000 { 511 compatible = "renesas,ipmmu-r8a77995"; 512 reg = <0 0xe6740000 0 0x1000>; 513 renesas,ipmmu-main = <&ipmmu_mm 0>; 514 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 515 #iommu-cells = <1>; 516 }; 517 518 ipmmu_ds1: iommu@e7740000 { 519 compatible = "renesas,ipmmu-r8a77995"; 520 reg = <0 0xe7740000 0 0x1000>; 521 renesas,ipmmu-main = <&ipmmu_mm 1>; 522 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 523 #iommu-cells = <1>; 524 }; 525 526 ipmmu_hc: iommu@e6570000 { 527 compatible = "renesas,ipmmu-r8a77995"; 528 reg = <0 0xe6570000 0 0x1000>; 529 renesas,ipmmu-main = <&ipmmu_mm 2>; 530 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 531 #iommu-cells = <1>; 532 }; 533 534 ipmmu_mm: iommu@e67b0000 { 535 compatible = "renesas,ipmmu-r8a77995"; 536 reg = <0 0xe67b0000 0 0x1000>; 537 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 539 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 540 #iommu-cells = <1>; 541 }; 542 543 ipmmu_mp: iommu@ec670000 { 544 compatible = "renesas,ipmmu-r8a77995"; 545 reg = <0 0xec670000 0 0x1000>; 546 renesas,ipmmu-main = <&ipmmu_mm 4>; 547 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 548 #iommu-cells = <1>; 549 }; 550 551 ipmmu_pv0: iommu@fd800000 { 552 compatible = "renesas,ipmmu-r8a77995"; 553 reg = <0 0xfd800000 0 0x1000>; 554 renesas,ipmmu-main = <&ipmmu_mm 6>; 555 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 556 #iommu-cells = <1>; 557 }; 558 559 ipmmu_rt: iommu@ffc80000 { 560 compatible = "renesas,ipmmu-r8a77995"; 561 reg = <0 0xffc80000 0 0x1000>; 562 renesas,ipmmu-main = <&ipmmu_mm 10>; 563 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 564 #iommu-cells = <1>; 565 }; 566 567 ipmmu_vc0: iommu@fe6b0000 { 568 compatible = "renesas,ipmmu-r8a77995"; 569 reg = <0 0xfe6b0000 0 0x1000>; 570 renesas,ipmmu-main = <&ipmmu_mm 12>; 571 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 572 #iommu-cells = <1>; 573 }; 574 575 ipmmu_vi0: iommu@febd0000 { 576 compatible = "renesas,ipmmu-r8a77995"; 577 reg = <0 0xfebd0000 0 0x1000>; 578 renesas,ipmmu-main = <&ipmmu_mm 14>; 579 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 580 #iommu-cells = <1>; 581 }; 582 583 ipmmu_vp0: iommu@fe990000 { 584 compatible = "renesas,ipmmu-r8a77995"; 585 reg = <0 0xfe990000 0 0x1000>; 586 renesas,ipmmu-main = <&ipmmu_mm 16>; 587 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 588 #iommu-cells = <1>; 589 }; 590 591 avb: ethernet@e6800000 { 592 compatible = "renesas,etheravb-r8a77995", 593 "renesas,etheravb-rcar-gen3"; 594 reg = <0 0xe6800000 0 0x800>; 595 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 620 interrupt-names = "ch0", "ch1", "ch2", "ch3", 621 "ch4", "ch5", "ch6", "ch7", 622 "ch8", "ch9", "ch10", "ch11", 623 "ch12", "ch13", "ch14", "ch15", 624 "ch16", "ch17", "ch18", "ch19", 625 "ch20", "ch21", "ch22", "ch23", 626 "ch24"; 627 clocks = <&cpg CPG_MOD 812>; 628 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 629 resets = <&cpg 812>; 630 phy-mode = "rgmii"; 631 iommus = <&ipmmu_ds0 16>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 status = "disabled"; 635 }; 636 637 can0: can@e6c30000 { 638 compatible = "renesas,can-r8a77995", 639 "renesas,rcar-gen3-can"; 640 reg = <0 0xe6c30000 0 0x1000>; 641 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cpg CPG_MOD 916>, 643 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 644 <&can_clk>; 645 clock-names = "clkp1", "clkp2", "can_clk"; 646 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 647 assigned-clock-rates = <40000000>; 648 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 649 resets = <&cpg 916>; 650 status = "disabled"; 651 }; 652 653 can1: can@e6c38000 { 654 compatible = "renesas,can-r8a77995", 655 "renesas,rcar-gen3-can"; 656 reg = <0 0xe6c38000 0 0x1000>; 657 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cpg CPG_MOD 915>, 659 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 660 <&can_clk>; 661 clock-names = "clkp1", "clkp2", "can_clk"; 662 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 663 assigned-clock-rates = <40000000>; 664 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 665 resets = <&cpg 915>; 666 status = "disabled"; 667 }; 668 669 pwm0: pwm@e6e30000 { 670 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 671 reg = <0 0xe6e30000 0 0x8>; 672 #pwm-cells = <2>; 673 clocks = <&cpg CPG_MOD 523>; 674 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 675 resets = <&cpg 523>; 676 status = "disabled"; 677 }; 678 679 pwm1: pwm@e6e31000 { 680 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 681 reg = <0 0xe6e31000 0 0x8>; 682 #pwm-cells = <2>; 683 clocks = <&cpg CPG_MOD 523>; 684 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 685 resets = <&cpg 523>; 686 status = "disabled"; 687 }; 688 689 pwm2: pwm@e6e32000 { 690 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 691 reg = <0 0xe6e32000 0 0x8>; 692 #pwm-cells = <2>; 693 clocks = <&cpg CPG_MOD 523>; 694 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 695 resets = <&cpg 523>; 696 status = "disabled"; 697 }; 698 699 pwm3: pwm@e6e33000 { 700 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 701 reg = <0 0xe6e33000 0 0x8>; 702 #pwm-cells = <2>; 703 clocks = <&cpg CPG_MOD 523>; 704 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 705 resets = <&cpg 523>; 706 status = "disabled"; 707 }; 708 709 scif0: serial@e6e60000 { 710 compatible = "renesas,scif-r8a77995", 711 "renesas,rcar-gen3-scif", "renesas,scif"; 712 reg = <0 0xe6e60000 0 64>; 713 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cpg CPG_MOD 207>, 715 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 716 <&scif_clk>; 717 clock-names = "fck", "brg_int", "scif_clk"; 718 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 719 <&dmac2 0x51>, <&dmac2 0x50>; 720 dma-names = "tx", "rx", "tx", "rx"; 721 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 722 resets = <&cpg 207>; 723 status = "disabled"; 724 }; 725 726 scif1: serial@e6e68000 { 727 compatible = "renesas,scif-r8a77995", 728 "renesas,rcar-gen3-scif", "renesas,scif"; 729 reg = <0 0xe6e68000 0 64>; 730 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cpg CPG_MOD 206>, 732 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 733 <&scif_clk>; 734 clock-names = "fck", "brg_int", "scif_clk"; 735 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 736 <&dmac2 0x53>, <&dmac2 0x52>; 737 dma-names = "tx", "rx", "tx", "rx"; 738 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 739 resets = <&cpg 206>; 740 status = "disabled"; 741 }; 742 743 scif2: serial@e6e88000 { 744 compatible = "renesas,scif-r8a77995", 745 "renesas,rcar-gen3-scif", "renesas,scif"; 746 reg = <0 0xe6e88000 0 64>; 747 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cpg CPG_MOD 310>, 749 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 750 <&scif_clk>; 751 clock-names = "fck", "brg_int", "scif_clk"; 752 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 753 <&dmac2 0x13>, <&dmac2 0x12>; 754 dma-names = "tx", "rx", "tx", "rx"; 755 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 756 resets = <&cpg 310>; 757 status = "disabled"; 758 }; 759 760 scif3: serial@e6c50000 { 761 compatible = "renesas,scif-r8a77995", 762 "renesas,rcar-gen3-scif", "renesas,scif"; 763 reg = <0 0xe6c50000 0 64>; 764 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&cpg CPG_MOD 204>, 766 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 767 <&scif_clk>; 768 clock-names = "fck", "brg_int", "scif_clk"; 769 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 770 dma-names = "tx", "rx"; 771 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 772 resets = <&cpg 204>; 773 status = "disabled"; 774 }; 775 776 scif4: serial@e6c40000 { 777 compatible = "renesas,scif-r8a77995", 778 "renesas,rcar-gen3-scif", "renesas,scif"; 779 reg = <0 0xe6c40000 0 64>; 780 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD 203>, 782 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 783 <&scif_clk>; 784 clock-names = "fck", "brg_int", "scif_clk"; 785 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 786 dma-names = "tx", "rx"; 787 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 788 resets = <&cpg 203>; 789 status = "disabled"; 790 }; 791 792 scif5: serial@e6f30000 { 793 compatible = "renesas,scif-r8a77995", 794 "renesas,rcar-gen3-scif", "renesas,scif"; 795 reg = <0 0xe6f30000 0 64>; 796 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD 202>, 798 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 799 <&scif_clk>; 800 clock-names = "fck", "brg_int", "scif_clk"; 801 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 802 <&dmac2 0x5b>, <&dmac2 0x5a>; 803 dma-names = "tx", "rx", "tx", "rx"; 804 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 805 resets = <&cpg 202>; 806 status = "disabled"; 807 }; 808 809 msiof0: spi@e6e90000 { 810 compatible = "renesas,msiof-r8a77995", 811 "renesas,rcar-gen3-msiof"; 812 reg = <0 0xe6e90000 0 0x64>; 813 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&cpg CPG_MOD 211>; 815 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 816 <&dmac2 0x41>, <&dmac2 0x40>; 817 dma-names = "tx", "rx", "tx", "rx"; 818 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 819 resets = <&cpg 211>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 msiof1: spi@e6ea0000 { 826 compatible = "renesas,msiof-r8a77995", 827 "renesas,rcar-gen3-msiof"; 828 reg = <0 0xe6ea0000 0 0x64>; 829 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&cpg CPG_MOD 210>; 831 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 832 <&dmac2 0x43>, <&dmac2 0x42>; 833 dma-names = "tx", "rx", "tx", "rx"; 834 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 835 resets = <&cpg 210>; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 msiof2: spi@e6c00000 { 842 compatible = "renesas,msiof-r8a77995", 843 "renesas,rcar-gen3-msiof"; 844 reg = <0 0xe6c00000 0 0x64>; 845 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&cpg CPG_MOD 209>; 847 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 848 dma-names = "tx", "rx"; 849 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 850 resets = <&cpg 209>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 status = "disabled"; 854 }; 855 856 msiof3: spi@e6c10000 { 857 compatible = "renesas,msiof-r8a77995", 858 "renesas,rcar-gen3-msiof"; 859 reg = <0 0xe6c10000 0 0x64>; 860 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cpg CPG_MOD 208>; 862 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 863 dma-names = "tx", "rx"; 864 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 865 resets = <&cpg 208>; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 status = "disabled"; 869 }; 870 871 vin4: video@e6ef4000 { 872 compatible = "renesas,vin-r8a77995"; 873 reg = <0 0xe6ef4000 0 0x1000>; 874 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&cpg CPG_MOD 807>; 876 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 877 resets = <&cpg 807>; 878 renesas,id = <4>; 879 status = "disabled"; 880 }; 881 882 ohci0: usb@ee080000 { 883 compatible = "generic-ohci"; 884 reg = <0 0xee080000 0 0x100>; 885 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 887 phys = <&usb2_phy0 1>; 888 phy-names = "usb"; 889 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 890 resets = <&cpg 703>, <&cpg 704>; 891 status = "disabled"; 892 }; 893 894 ehci0: usb@ee080100 { 895 compatible = "generic-ehci"; 896 reg = <0 0xee080100 0 0x100>; 897 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 899 phys = <&usb2_phy0 2>; 900 phy-names = "usb"; 901 companion = <&ohci0>; 902 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 903 resets = <&cpg 703>, <&cpg 704>; 904 status = "disabled"; 905 }; 906 907 usb2_phy0: usb-phy@ee080200 { 908 compatible = "renesas,usb2-phy-r8a77995", 909 "renesas,rcar-gen3-usb2-phy"; 910 reg = <0 0xee080200 0 0x700>; 911 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 913 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 914 resets = <&cpg 703>, <&cpg 704>; 915 #phy-cells = <1>; 916 status = "disabled"; 917 }; 918 919 sdhi2: mmc@ee140000 { 920 compatible = "renesas,sdhi-r8a77995", 921 "renesas,rcar-gen3-sdhi"; 922 reg = <0 0xee140000 0 0x2000>; 923 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&cpg CPG_MOD 312>; 925 max-frequency = <200000000>; 926 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 927 resets = <&cpg 312>; 928 iommus = <&ipmmu_ds1 34>; 929 status = "disabled"; 930 }; 931 932 gic: interrupt-controller@f1010000 { 933 compatible = "arm,gic-400"; 934 #interrupt-cells = <3>; 935 #address-cells = <0>; 936 interrupt-controller; 937 reg = <0x0 0xf1010000 0 0x1000>, 938 <0x0 0xf1020000 0 0x20000>, 939 <0x0 0xf1040000 0 0x20000>, 940 <0x0 0xf1060000 0 0x20000>; 941 interrupts = <GIC_PPI 9 942 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 943 clocks = <&cpg CPG_MOD 408>; 944 clock-names = "clk"; 945 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 946 resets = <&cpg 408>; 947 }; 948 949 vspbs: vsp@fe960000 { 950 compatible = "renesas,vsp2"; 951 reg = <0 0xfe960000 0 0x8000>; 952 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&cpg CPG_MOD 627>; 954 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 955 resets = <&cpg 627>; 956 renesas,fcp = <&fcpvb0>; 957 }; 958 959 vspd0: vsp@fea20000 { 960 compatible = "renesas,vsp2"; 961 reg = <0 0xfea20000 0 0x5000>; 962 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&cpg CPG_MOD 623>; 964 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 965 resets = <&cpg 623>; 966 renesas,fcp = <&fcpvd0>; 967 }; 968 969 vspd1: vsp@fea28000 { 970 compatible = "renesas,vsp2"; 971 reg = <0 0xfea28000 0 0x5000>; 972 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cpg CPG_MOD 622>; 974 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 975 resets = <&cpg 622>; 976 renesas,fcp = <&fcpvd1>; 977 }; 978 979 fcpvb0: fcp@fe96f000 { 980 compatible = "renesas,fcpv"; 981 reg = <0 0xfe96f000 0 0x200>; 982 clocks = <&cpg CPG_MOD 607>; 983 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 984 resets = <&cpg 607>; 985 iommus = <&ipmmu_vp0 5>; 986 }; 987 988 fcpvd0: fcp@fea27000 { 989 compatible = "renesas,fcpv"; 990 reg = <0 0xfea27000 0 0x200>; 991 clocks = <&cpg CPG_MOD 603>; 992 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 993 resets = <&cpg 603>; 994 iommus = <&ipmmu_vi0 8>; 995 }; 996 997 fcpvd1: fcp@fea2f000 { 998 compatible = "renesas,fcpv"; 999 reg = <0 0xfea2f000 0 0x200>; 1000 clocks = <&cpg CPG_MOD 602>; 1001 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1002 resets = <&cpg 602>; 1003 iommus = <&ipmmu_vi0 9>; 1004 }; 1005 1006 cmm0: cmm@fea40000 { 1007 compatible = "renesas,r8a77995-cmm", 1008 "renesas,rcar-gen3-cmm"; 1009 reg = <0 0xfea40000 0 0x1000>; 1010 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1011 clocks = <&cpg CPG_MOD 711>; 1012 resets = <&cpg 711>; 1013 }; 1014 1015 cmm1: cmm@fea50000 { 1016 compatible = "renesas,r8a77995-cmm", 1017 "renesas,rcar-gen3-cmm"; 1018 reg = <0 0xfea50000 0 0x1000>; 1019 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1020 clocks = <&cpg CPG_MOD 710>; 1021 resets = <&cpg 710>; 1022 }; 1023 1024 du: display@feb00000 { 1025 compatible = "renesas,du-r8a77995"; 1026 reg = <0 0xfeb00000 0 0x40000>; 1027 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1030 clock-names = "du.0", "du.1"; 1031 resets = <&cpg 724>; 1032 reset-names = "du.0"; 1033 1034 renesas,cmms = <&cmm0>, <&cmm1>; 1035 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1036 1037 status = "disabled"; 1038 1039 ports { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 port@0 { 1044 reg = <0>; 1045 du_out_rgb: endpoint { 1046 }; 1047 }; 1048 1049 port@1 { 1050 reg = <1>; 1051 du_out_lvds0: endpoint { 1052 remote-endpoint = <&lvds0_in>; 1053 }; 1054 }; 1055 1056 port@2 { 1057 reg = <2>; 1058 du_out_lvds1: endpoint { 1059 remote-endpoint = <&lvds1_in>; 1060 }; 1061 }; 1062 }; 1063 }; 1064 1065 lvds0: lvds-encoder@feb90000 { 1066 compatible = "renesas,r8a77995-lvds"; 1067 reg = <0 0xfeb90000 0 0x20>; 1068 clocks = <&cpg CPG_MOD 727>; 1069 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1070 resets = <&cpg 727>; 1071 status = "disabled"; 1072 1073 renesas,companion = <&lvds1>; 1074 1075 ports { 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 1079 port@0 { 1080 reg = <0>; 1081 lvds0_in: endpoint { 1082 remote-endpoint = <&du_out_lvds0>; 1083 }; 1084 }; 1085 1086 port@1 { 1087 reg = <1>; 1088 lvds0_out: endpoint { 1089 }; 1090 }; 1091 }; 1092 }; 1093 1094 lvds1: lvds-encoder@feb90100 { 1095 compatible = "renesas,r8a77995-lvds"; 1096 reg = <0 0xfeb90100 0 0x20>; 1097 clocks = <&cpg CPG_MOD 727>; 1098 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1099 resets = <&cpg 726>; 1100 status = "disabled"; 1101 1102 ports { 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 1106 port@0 { 1107 reg = <0>; 1108 lvds1_in: endpoint { 1109 remote-endpoint = <&du_out_lvds1>; 1110 }; 1111 }; 1112 1113 port@1 { 1114 reg = <1>; 1115 lvds1_out: endpoint { 1116 }; 1117 }; 1118 }; 1119 }; 1120 1121 prr: chipid@fff00044 { 1122 compatible = "renesas,prr"; 1123 reg = <0 0xfff00044 0 4>; 1124 }; 1125 }; 1126 1127 thermal-zones { 1128 cpu_thermal: cpu-thermal { 1129 polling-delay-passive = <250>; 1130 polling-delay = <1000>; 1131 thermal-sensors = <&thermal>; 1132 1133 cooling-maps { 1134 }; 1135 1136 trips { 1137 cpu-crit { 1138 temperature = <120000>; 1139 hysteresis = <2000>; 1140 type = "critical"; 1141 }; 1142 }; 1143 }; 1144 }; 1145 1146 timer { 1147 compatible = "arm,armv8-timer"; 1148 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1149 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1150 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1151 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 1152 }; 1153}; 1154