1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/x1000-cgu.h> 3#include <dt-bindings/dma/x1000-dma.h> 4 5/ { 6 #address-cells = <1>; 7 #size-cells = <1>; 8 compatible = "ingenic,x1000", "ingenic,x1000e"; 9 10 cpuintc: interrupt-controller { 11 #address-cells = <0>; 12 #interrupt-cells = <1>; 13 interrupt-controller; 14 compatible = "mti,cpu-interrupt-controller"; 15 }; 16 17 intc: interrupt-controller@10001000 { 18 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc"; 19 reg = <0x10001000 0x50>; 20 21 interrupt-controller; 22 #interrupt-cells = <1>; 23 24 interrupt-parent = <&cpuintc>; 25 interrupts = <2>; 26 }; 27 28 exclk: ext { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 rtclk: rtc { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32768>; 37 }; 38 39 cgu: x1000-cgu@10000000 { 40 compatible = "ingenic,x1000-cgu"; 41 reg = <0x10000000 0x100>; 42 43 #clock-cells = <1>; 44 45 clocks = <&exclk>, <&rtclk>; 46 clock-names = "ext", "rtc"; 47 }; 48 49 tcu: timer@10002000 { 50 compatible = "ingenic,x1000-tcu", 51 "ingenic,jz4770-tcu", 52 "simple-mfd"; 53 reg = <0x10002000 0x1000>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges = <0x0 0x10002000 0x1000>; 57 58 #clock-cells = <1>; 59 60 clocks = <&cgu X1000_CLK_RTCLK 61 &cgu X1000_CLK_EXCLK 62 &cgu X1000_CLK_PCLK>; 63 clock-names = "rtc", "ext", "pclk"; 64 65 interrupt-controller; 66 #interrupt-cells = <1>; 67 68 interrupt-parent = <&intc>; 69 interrupts = <27 26 25>; 70 71 wdt: watchdog@0 { 72 compatible = "ingenic,x1000-watchdog", "ingenic,jz4780-watchdog"; 73 reg = <0x0 0x10>; 74 75 clocks = <&cgu X1000_CLK_RTCLK>; 76 clock-names = "wdt"; 77 }; 78 }; 79 80 rtc: rtc@10003000 { 81 compatible = "ingenic,x1000-rtc", "ingenic,jz4780-rtc"; 82 reg = <0x10003000 0x4c>; 83 84 interrupt-parent = <&intc>; 85 interrupts = <32>; 86 87 clocks = <&cgu X1000_CLK_RTCLK>; 88 clock-names = "rtc"; 89 }; 90 91 pinctrl: pin-controller@10010000 { 92 compatible = "ingenic,x1000-pinctrl"; 93 reg = <0x10010000 0x800>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 gpa: gpio@0 { 98 compatible = "ingenic,x1000-gpio"; 99 reg = <0>; 100 101 gpio-controller; 102 gpio-ranges = <&pinctrl 0 0 32>; 103 #gpio-cells = <2>; 104 105 interrupt-controller; 106 #interrupt-cells = <2>; 107 108 interrupt-parent = <&intc>; 109 interrupts = <17>; 110 }; 111 112 gpb: gpio@1 { 113 compatible = "ingenic,x1000-gpio"; 114 reg = <1>; 115 116 gpio-controller; 117 gpio-ranges = <&pinctrl 0 32 32>; 118 #gpio-cells = <2>; 119 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 123 interrupt-parent = <&intc>; 124 interrupts = <16>; 125 }; 126 127 gpc: gpio@2 { 128 compatible = "ingenic,x1000-gpio"; 129 reg = <2>; 130 131 gpio-controller; 132 gpio-ranges = <&pinctrl 0 64 32>; 133 #gpio-cells = <2>; 134 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 138 interrupt-parent = <&intc>; 139 interrupts = <15>; 140 }; 141 142 gpd: gpio@3 { 143 compatible = "ingenic,x1000-gpio"; 144 reg = <3>; 145 146 gpio-controller; 147 gpio-ranges = <&pinctrl 0 96 32>; 148 #gpio-cells = <2>; 149 150 interrupt-controller; 151 #interrupt-cells = <2>; 152 153 interrupt-parent = <&intc>; 154 interrupts = <14>; 155 }; 156 }; 157 158 i2c0: i2c-controller@10050000 { 159 compatible = "ingenic,x1000-i2c"; 160 reg = <0x10050000 0x1000>; 161 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 interrupt-parent = <&intc>; 166 interrupts = <60>; 167 168 clocks = <&cgu X1000_CLK_I2C0>; 169 170 status = "disabled"; 171 }; 172 173 i2c1: i2c-controller@10051000 { 174 compatible = "ingenic,x1000-i2c"; 175 reg = <0x10051000 0x1000>; 176 177 #address-cells = <1>; 178 #size-cells = <0>; 179 180 interrupt-parent = <&intc>; 181 interrupts = <59>; 182 183 clocks = <&cgu X1000_CLK_I2C1>; 184 185 status = "disabled"; 186 }; 187 188 i2c2: i2c-controller@10052000 { 189 compatible = "ingenic,x1000-i2c"; 190 reg = <0x10052000 0x1000>; 191 192 #address-cells = <1>; 193 #size-cells = <0>; 194 195 interrupt-parent = <&intc>; 196 interrupts = <58>; 197 198 clocks = <&cgu X1000_CLK_I2C2>; 199 200 status = "disabled"; 201 }; 202 203 uart0: serial@10030000 { 204 compatible = "ingenic,x1000-uart"; 205 reg = <0x10030000 0x100>; 206 207 interrupt-parent = <&intc>; 208 interrupts = <51>; 209 210 clocks = <&exclk>, <&cgu X1000_CLK_UART0>; 211 clock-names = "baud", "module"; 212 213 status = "disabled"; 214 }; 215 216 uart1: serial@10031000 { 217 compatible = "ingenic,x1000-uart"; 218 reg = <0x10031000 0x100>; 219 220 interrupt-parent = <&intc>; 221 interrupts = <50>; 222 223 clocks = <&exclk>, <&cgu X1000_CLK_UART1>; 224 clock-names = "baud", "module"; 225 226 status = "disabled"; 227 }; 228 229 uart2: serial@10032000 { 230 compatible = "ingenic,x1000-uart"; 231 reg = <0x10032000 0x100>; 232 233 interrupt-parent = <&intc>; 234 interrupts = <49>; 235 236 clocks = <&exclk>, <&cgu X1000_CLK_UART2>; 237 clock-names = "baud", "module"; 238 239 status = "disabled"; 240 }; 241 242 pdma: dma-controller@13420000 { 243 compatible = "ingenic,x1000-dma"; 244 reg = <0x13420000 0x400 245 0x13421000 0x40>; 246 #dma-cells = <2>; 247 248 interrupt-parent = <&intc>; 249 interrupts = <10>; 250 251 clocks = <&cgu X1000_CLK_PDMA>; 252 }; 253 254 mac: ethernet@134b0000 { 255 compatible = "ingenic,x1000-mac", "snps,dwmac"; 256 reg = <0x134b0000 0x2000>; 257 258 interrupt-parent = <&intc>; 259 interrupts = <55>; 260 interrupt-names = "macirq"; 261 262 clocks = <&cgu X1000_CLK_MAC>; 263 clock-names = "stmmaceth"; 264 265 status = "disabled"; 266 267 mdio: mdio { 268 compatible = "snps,dwmac-mdio"; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 272 status = "disabled"; 273 }; 274 }; 275 276 msc0: mmc@13450000 { 277 compatible = "ingenic,x1000-mmc"; 278 reg = <0x13450000 0x1000>; 279 280 interrupt-parent = <&intc>; 281 interrupts = <37>; 282 283 clocks = <&cgu X1000_CLK_MSC0>; 284 clock-names = "mmc"; 285 286 cap-sd-highspeed; 287 cap-mmc-highspeed; 288 cap-sdio-irq; 289 290 dmas = <&pdma X1000_DMA_MSC0_RX 0xffffffff>, 291 <&pdma X1000_DMA_MSC0_TX 0xffffffff>; 292 dma-names = "rx", "tx"; 293 294 status = "disabled"; 295 }; 296 297 msc1: mmc@13460000 { 298 compatible = "ingenic,x1000-mmc"; 299 reg = <0x13460000 0x1000>; 300 301 interrupt-parent = <&intc>; 302 interrupts = <36>; 303 304 clocks = <&cgu X1000_CLK_MSC1>; 305 clock-names = "mmc"; 306 307 cap-sd-highspeed; 308 cap-mmc-highspeed; 309 cap-sdio-irq; 310 311 dmas = <&pdma X1000_DMA_MSC1_RX 0xffffffff>, 312 <&pdma X1000_DMA_MSC1_TX 0xffffffff>; 313 dma-names = "rx", "tx"; 314 315 status = "disabled"; 316 }; 317}; 318