1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3 4#include <arm/sunxi-h3-h5.dtsi> 5 6/ { 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 cpu0: cpu@0 { 12 compatible = "arm,cortex-a53"; 13 device_type = "cpu"; 14 reg = <0>; 15 enable-method = "psci"; 16 }; 17 18 cpu1: cpu@1 { 19 compatible = "arm,cortex-a53"; 20 device_type = "cpu"; 21 reg = <1>; 22 enable-method = "psci"; 23 }; 24 25 cpu2: cpu@2 { 26 compatible = "arm,cortex-a53"; 27 device_type = "cpu"; 28 reg = <2>; 29 enable-method = "psci"; 30 }; 31 32 cpu3: cpu@3 { 33 compatible = "arm,cortex-a53"; 34 device_type = "cpu"; 35 reg = <3>; 36 enable-method = "psci"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a53-pmu"; 42 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 46 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 47 }; 48 49 psci { 50 compatible = "arm,psci-0.2"; 51 method = "smc"; 52 }; 53 54 timer { 55 compatible = "arm,armv8-timer"; 56 interrupts = <GIC_PPI 13 57 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 58 <GIC_PPI 14 59 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 60 <GIC_PPI 11 61 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62 <GIC_PPI 10 63 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 64 }; 65 66 soc { 67 syscon: system-control@1c00000 { 68 compatible = "allwinner,sun50i-h5-system-control"; 69 reg = <0x01c00000 0x1000>; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges; 73 74 sram_c1: sram@18000 { 75 compatible = "mmio-sram"; 76 reg = <0x00018000 0x1c000>; 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges = <0 0x00018000 0x1c000>; 80 81 ve_sram: sram-section@0 { 82 compatible = "allwinner,sun50i-h5-sram-c1", 83 "allwinner,sun4i-a10-sram-c1"; 84 reg = <0x000000 0x1c000>; 85 }; 86 }; 87 }; 88 89 video-codec@1c0e000 { 90 compatible = "allwinner,sun50i-h5-video-engine"; 91 reg = <0x01c0e000 0x1000>; 92 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 93 <&ccu CLK_DRAM_VE>; 94 clock-names = "ahb", "mod", "ram"; 95 resets = <&ccu RST_BUS_VE>; 96 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 97 allwinner,sram = <&ve_sram 1>; 98 }; 99 100 crypto: crypto@1c15000 { 101 compatible = "allwinner,sun50i-h5-crypto"; 102 reg = <0x01c15000 0x1000>; 103 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 105 clock-names = "bus", "mod"; 106 resets = <&ccu RST_BUS_CE>; 107 }; 108 109 mali: gpu@1e80000 { 110 compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; 111 reg = <0x01e80000 0x30000>; 112 /* 113 * While the datasheet lists an interrupt for the 114 * PMU, the actual silicon does not have the PMU 115 * block. Reads all return zero, and writes are 116 * ignored. 117 */ 118 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 130 interrupt-names = "gp", 131 "gpmmu", 132 "pp", 133 "pp0", 134 "ppmmu0", 135 "pp1", 136 "ppmmu1", 137 "pp2", 138 "ppmmu2", 139 "pp3", 140 "ppmmu3", 141 "pmu"; 142 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 143 clock-names = "bus", "core"; 144 resets = <&ccu RST_BUS_GPU>; 145 146 assigned-clocks = <&ccu CLK_GPU>; 147 assigned-clock-rates = <384000000>; 148 }; 149 150 ths: thermal-sensor@1c25000 { 151 compatible = "allwinner,sun50i-h5-ths"; 152 reg = <0x01c25000 0x400>; 153 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 154 resets = <&ccu RST_BUS_THS>; 155 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 156 clock-names = "bus", "mod"; 157 nvmem-cells = <&ths_calibration>; 158 nvmem-cell-names = "calibration"; 159 #thermal-sensor-cells = <1>; 160 }; 161 }; 162 163 thermal-zones { 164 cpu_thermal: cpu-thermal { 165 polling-delay-passive = <0>; 166 polling-delay = <0>; 167 thermal-sensors = <&ths 0>; 168 }; 169 170 gpu_thermal { 171 polling-delay-passive = <0>; 172 polling-delay = <0>; 173 thermal-sensors = <&ths 1>; 174 }; 175 }; 176}; 177 178&ccu { 179 compatible = "allwinner,sun50i-h5-ccu"; 180}; 181 182&display_clocks { 183 compatible = "allwinner,sun50i-h5-de2-clk"; 184}; 185 186&mmc0 { 187 compatible = "allwinner,sun50i-h5-mmc", 188 "allwinner,sun50i-a64-mmc"; 189 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 190 clock-names = "ahb", "mmc"; 191}; 192 193&mmc1 { 194 compatible = "allwinner,sun50i-h5-mmc", 195 "allwinner,sun50i-a64-mmc"; 196 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 197 clock-names = "ahb", "mmc"; 198}; 199 200&mmc2 { 201 compatible = "allwinner,sun50i-h5-emmc", 202 "allwinner,sun50i-a64-emmc"; 203 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 204 clock-names = "ahb", "mmc"; 205}; 206 207&pio { 208 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 211 compatible = "allwinner,sun50i-h5-pinctrl"; 212}; 213 214&rtc { 215 compatible = "allwinner,sun50i-h5-rtc"; 216}; 217 218&sid { 219 compatible = "allwinner,sun50i-h5-sid"; 220}; 221