1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos7 SoC device tree source 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com 7 */ 8 9#include <dt-bindings/clock/exynos7-clk.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 compatible = "samsung,exynos7"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 pinctrl0 = &pinctrl_alive; 20 pinctrl1 = &pinctrl_bus0; 21 pinctrl2 = &pinctrl_nfc; 22 pinctrl3 = &pinctrl_touch; 23 pinctrl4 = &pinctrl_ff; 24 pinctrl5 = &pinctrl_ese; 25 pinctrl6 = &pinctrl_fsys0; 26 pinctrl7 = &pinctrl_fsys1; 27 pinctrl8 = &pinctrl_bus1; 28 tmuctrl0 = &tmuctrl_0; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a57-pmu"; 33 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 37 interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>, 38 <&cpu_atlas2>, <&cpu_atlas3>; 39 }; 40 41 fin_pll: clock { 42 /* XXTI */ 43 compatible = "fixed-clock"; 44 clock-output-names = "fin_pll"; 45 #clock-cells = <0>; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu_atlas0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a57"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 }; 58 59 cpu_atlas1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a57"; 62 reg = <0x1>; 63 enable-method = "psci"; 64 }; 65 66 cpu_atlas2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a57"; 69 reg = <0x2>; 70 enable-method = "psci"; 71 }; 72 73 cpu_atlas3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a57"; 76 reg = <0x3>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 psci { 82 compatible = "arm,psci-0.2"; 83 method = "smc"; 84 }; 85 86 soc: soc@0 { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges = <0 0 0 0x18000000>; 91 92 chipid@10000000 { 93 compatible = "samsung,exynos4210-chipid"; 94 reg = <0x10000000 0x100>; 95 }; 96 97 gic: interrupt-controller@11001000 { 98 compatible = "arm,gic-400"; 99 #interrupt-cells = <3>; 100 #address-cells = <0>; 101 interrupt-controller; 102 reg = <0x11001000 0x1000>, 103 <0x11002000 0x1000>, 104 <0x11004000 0x2000>, 105 <0x11006000 0x2000>; 106 }; 107 108 pdma0: pdma@10e10000 { 109 compatible = "arm,pl330", "arm,primecell"; 110 reg = <0x10E10000 0x1000>; 111 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 112 clocks = <&clock_fsys0 ACLK_PDMA0>; 113 clock-names = "apb_pclk"; 114 #dma-cells = <1>; 115 #dma-channels = <8>; 116 #dma-requests = <32>; 117 }; 118 119 pdma1: pdma@10eb0000 { 120 compatible = "arm,pl330", "arm,primecell"; 121 reg = <0x10EB0000 0x1000>; 122 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&clock_fsys0 ACLK_PDMA1>; 124 clock-names = "apb_pclk"; 125 #dma-cells = <1>; 126 #dma-channels = <8>; 127 #dma-requests = <32>; 128 }; 129 130 clock_topc: clock-controller@10570000 { 131 compatible = "samsung,exynos7-clock-topc"; 132 reg = <0x10570000 0x10000>; 133 #clock-cells = <1>; 134 }; 135 136 clock_top0: clock-controller@105d0000 { 137 compatible = "samsung,exynos7-clock-top0"; 138 reg = <0x105d0000 0xb000>; 139 #clock-cells = <1>; 140 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 141 <&clock_topc DOUT_SCLK_BUS1_PLL>, 142 <&clock_topc DOUT_SCLK_CC_PLL>, 143 <&clock_topc DOUT_SCLK_MFC_PLL>; 144 clock-names = "fin_pll", "dout_sclk_bus0_pll", 145 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 146 "dout_sclk_mfc_pll"; 147 }; 148 149 clock_top1: clock-controller@105e0000 { 150 compatible = "samsung,exynos7-clock-top1"; 151 reg = <0x105e0000 0xb000>; 152 #clock-cells = <1>; 153 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 154 <&clock_topc DOUT_SCLK_BUS1_PLL>, 155 <&clock_topc DOUT_SCLK_CC_PLL>, 156 <&clock_topc DOUT_SCLK_MFC_PLL>; 157 clock-names = "fin_pll", "dout_sclk_bus0_pll", 158 "dout_sclk_bus1_pll", "dout_sclk_cc_pll", 159 "dout_sclk_mfc_pll"; 160 }; 161 162 clock_ccore: clock-controller@105b0000 { 163 compatible = "samsung,exynos7-clock-ccore"; 164 reg = <0x105b0000 0xd00>; 165 #clock-cells = <1>; 166 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>; 167 clock-names = "fin_pll", "dout_aclk_ccore_133"; 168 }; 169 170 clock_peric0: clock-controller@13610000 { 171 compatible = "samsung,exynos7-clock-peric0"; 172 reg = <0x13610000 0xd00>; 173 #clock-cells = <1>; 174 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>, 175 <&clock_top0 CLK_SCLK_UART0>; 176 clock-names = "fin_pll", "dout_aclk_peric0_66", 177 "sclk_uart0"; 178 }; 179 180 clock_peric1: clock-controller@14c80000 { 181 compatible = "samsung,exynos7-clock-peric1"; 182 reg = <0x14c80000 0xd00>; 183 #clock-cells = <1>; 184 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, 185 <&clock_top0 CLK_SCLK_UART1>, 186 <&clock_top0 CLK_SCLK_UART2>, 187 <&clock_top0 CLK_SCLK_UART3>; 188 clock-names = "fin_pll", "dout_aclk_peric1_66", 189 "sclk_uart1", "sclk_uart2", "sclk_uart3"; 190 }; 191 192 clock_peris: clock-controller@10040000 { 193 compatible = "samsung,exynos7-clock-peris"; 194 reg = <0x10040000 0xd00>; 195 #clock-cells = <1>; 196 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>; 197 clock-names = "fin_pll", "dout_aclk_peris_66"; 198 }; 199 200 clock_fsys0: clock-controller@10e90000 { 201 compatible = "samsung,exynos7-clock-fsys0"; 202 reg = <0x10e90000 0xd00>; 203 #clock-cells = <1>; 204 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>, 205 <&clock_top1 DOUT_SCLK_MMC2>; 206 clock-names = "fin_pll", "dout_aclk_fsys0_200", 207 "dout_sclk_mmc2"; 208 }; 209 210 clock_fsys1: clock-controller@156e0000 { 211 compatible = "samsung,exynos7-clock-fsys1"; 212 reg = <0x156e0000 0xd00>; 213 #clock-cells = <1>; 214 clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>, 215 <&clock_top1 DOUT_SCLK_MMC0>, 216 <&clock_top1 DOUT_SCLK_MMC1>, 217 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>, 218 <&clock_top1 DOUT_SCLK_PHY_FSYS1>, 219 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>; 220 clock-names = "fin_pll", "dout_aclk_fsys1_200", 221 "dout_sclk_mmc0", "dout_sclk_mmc1", 222 "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1", 223 "dout_sclk_phy_fsys1_26m"; 224 }; 225 226 serial_0: serial@13630000 { 227 compatible = "samsung,exynos4210-uart"; 228 reg = <0x13630000 0x100>; 229 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&clock_peric0 PCLK_UART0>, 231 <&clock_peric0 SCLK_UART0>; 232 clock-names = "uart", "clk_uart_baud0"; 233 status = "disabled"; 234 }; 235 236 serial_1: serial@14c20000 { 237 compatible = "samsung,exynos4210-uart"; 238 reg = <0x14c20000 0x100>; 239 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clock_peric1 PCLK_UART1>, 241 <&clock_peric1 SCLK_UART1>; 242 clock-names = "uart", "clk_uart_baud0"; 243 status = "disabled"; 244 }; 245 246 serial_2: serial@14c30000 { 247 compatible = "samsung,exynos4210-uart"; 248 reg = <0x14c30000 0x100>; 249 interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clock_peric1 PCLK_UART2>, 251 <&clock_peric1 SCLK_UART2>; 252 clock-names = "uart", "clk_uart_baud0"; 253 status = "disabled"; 254 }; 255 256 serial_3: serial@14c40000 { 257 compatible = "samsung,exynos4210-uart"; 258 reg = <0x14c40000 0x100>; 259 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clock_peric1 PCLK_UART3>, 261 <&clock_peric1 SCLK_UART3>; 262 clock-names = "uart", "clk_uart_baud0"; 263 status = "disabled"; 264 }; 265 266 pinctrl_alive: pinctrl@10580000 { 267 compatible = "samsung,exynos7-pinctrl"; 268 reg = <0x10580000 0x1000>; 269 270 wakeup-interrupt-controller { 271 compatible = "samsung,exynos7-wakeup-eint"; 272 interrupt-parent = <&gic>; 273 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 274 }; 275 }; 276 277 pinctrl_bus0: pinctrl@13470000 { 278 compatible = "samsung,exynos7-pinctrl"; 279 reg = <0x13470000 0x1000>; 280 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 281 }; 282 283 pinctrl_nfc: pinctrl@14cd0000 { 284 compatible = "samsung,exynos7-pinctrl"; 285 reg = <0x14cd0000 0x1000>; 286 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 287 }; 288 289 pinctrl_touch: pinctrl@14ce0000 { 290 compatible = "samsung,exynos7-pinctrl"; 291 reg = <0x14ce0000 0x1000>; 292 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 293 }; 294 295 pinctrl_ff: pinctrl@14c90000 { 296 compatible = "samsung,exynos7-pinctrl"; 297 reg = <0x14c90000 0x1000>; 298 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 299 }; 300 301 pinctrl_ese: pinctrl@14ca0000 { 302 compatible = "samsung,exynos7-pinctrl"; 303 reg = <0x14ca0000 0x1000>; 304 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 305 }; 306 307 pinctrl_fsys0: pinctrl@10e60000 { 308 compatible = "samsung,exynos7-pinctrl"; 309 reg = <0x10e60000 0x1000>; 310 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 311 }; 312 313 pinctrl_fsys1: pinctrl@15690000 { 314 compatible = "samsung,exynos7-pinctrl"; 315 reg = <0x15690000 0x1000>; 316 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 317 }; 318 319 pinctrl_bus1: pinctrl@14870000 { 320 compatible = "samsung,exynos7-pinctrl"; 321 reg = <0x14870000 0x1000>; 322 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 323 }; 324 325 hsi2c_0: hsi2c@13640000 { 326 compatible = "samsung,exynos7-hsi2c"; 327 reg = <0x13640000 0x1000>; 328 interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&hs_i2c0_bus>; 333 clocks = <&clock_peric0 PCLK_HSI2C0>; 334 clock-names = "hsi2c"; 335 status = "disabled"; 336 }; 337 338 hsi2c_1: hsi2c@13650000 { 339 compatible = "samsung,exynos7-hsi2c"; 340 reg = <0x13650000 0x1000>; 341 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&hs_i2c1_bus>; 346 clocks = <&clock_peric0 PCLK_HSI2C1>; 347 clock-names = "hsi2c"; 348 status = "disabled"; 349 }; 350 351 hsi2c_2: hsi2c@14e60000 { 352 compatible = "samsung,exynos7-hsi2c"; 353 reg = <0x14e60000 0x1000>; 354 interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&hs_i2c2_bus>; 359 clocks = <&clock_peric1 PCLK_HSI2C2>; 360 clock-names = "hsi2c"; 361 status = "disabled"; 362 }; 363 364 hsi2c_3: hsi2c@14e70000 { 365 compatible = "samsung,exynos7-hsi2c"; 366 reg = <0x14e70000 0x1000>; 367 interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&hs_i2c3_bus>; 372 clocks = <&clock_peric1 PCLK_HSI2C3>; 373 clock-names = "hsi2c"; 374 status = "disabled"; 375 }; 376 377 hsi2c_4: hsi2c@13660000 { 378 compatible = "samsung,exynos7-hsi2c"; 379 reg = <0x13660000 0x1000>; 380 interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&hs_i2c4_bus>; 385 clocks = <&clock_peric0 PCLK_HSI2C4>; 386 clock-names = "hsi2c"; 387 status = "disabled"; 388 }; 389 390 hsi2c_5: hsi2c@13670000 { 391 compatible = "samsung,exynos7-hsi2c"; 392 reg = <0x13670000 0x1000>; 393 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&hs_i2c5_bus>; 398 clocks = <&clock_peric0 PCLK_HSI2C5>; 399 clock-names = "hsi2c"; 400 status = "disabled"; 401 }; 402 403 hsi2c_6: hsi2c@14e00000 { 404 compatible = "samsung,exynos7-hsi2c"; 405 reg = <0x14e00000 0x1000>; 406 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&hs_i2c6_bus>; 411 clocks = <&clock_peric1 PCLK_HSI2C6>; 412 clock-names = "hsi2c"; 413 status = "disabled"; 414 }; 415 416 hsi2c_7: hsi2c@13e10000 { 417 compatible = "samsung,exynos7-hsi2c"; 418 reg = <0x13e10000 0x1000>; 419 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&hs_i2c7_bus>; 424 clocks = <&clock_peric1 PCLK_HSI2C7>; 425 clock-names = "hsi2c"; 426 status = "disabled"; 427 }; 428 429 hsi2c_8: hsi2c@14e20000 { 430 compatible = "samsung,exynos7-hsi2c"; 431 reg = <0x14e20000 0x1000>; 432 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&hs_i2c8_bus>; 437 clocks = <&clock_peric1 PCLK_HSI2C8>; 438 clock-names = "hsi2c"; 439 status = "disabled"; 440 }; 441 442 hsi2c_9: hsi2c@13680000 { 443 compatible = "samsung,exynos7-hsi2c"; 444 reg = <0x13680000 0x1000>; 445 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&hs_i2c9_bus>; 450 clocks = <&clock_peric0 PCLK_HSI2C9>; 451 clock-names = "hsi2c"; 452 status = "disabled"; 453 }; 454 455 hsi2c_10: hsi2c@13690000 { 456 compatible = "samsung,exynos7-hsi2c"; 457 reg = <0x13690000 0x1000>; 458 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&hs_i2c10_bus>; 463 clocks = <&clock_peric0 PCLK_HSI2C10>; 464 clock-names = "hsi2c"; 465 status = "disabled"; 466 }; 467 468 hsi2c_11: hsi2c@136a0000 { 469 compatible = "samsung,exynos7-hsi2c"; 470 reg = <0x136a0000 0x1000>; 471 interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&hs_i2c11_bus>; 476 clocks = <&clock_peric0 PCLK_HSI2C11>; 477 clock-names = "hsi2c"; 478 status = "disabled"; 479 }; 480 481 pmu_system_controller: system-controller@105c0000 { 482 compatible = "samsung,exynos7-pmu", "syscon"; 483 reg = <0x105c0000 0x5000>; 484 485 reboot: syscon-reboot { 486 compatible = "syscon-reboot"; 487 regmap = <&pmu_system_controller>; 488 offset = <0x0400>; 489 mask = <0x1>; 490 }; 491 }; 492 493 rtc: rtc@10590000 { 494 compatible = "samsung,s3c6410-rtc"; 495 reg = <0x10590000 0x100>; 496 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clock_ccore PCLK_RTC>; 499 clock-names = "rtc"; 500 status = "disabled"; 501 }; 502 503 watchdog: watchdog@101d0000 { 504 compatible = "samsung,exynos7-wdt"; 505 reg = <0x101d0000 0x100>; 506 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&clock_peris PCLK_WDT>; 508 clock-names = "watchdog"; 509 samsung,syscon-phandle = <&pmu_system_controller>; 510 status = "disabled"; 511 }; 512 513 gpu: gpu@14ac0000 { 514 compatible = "samsung,exynos5433-mali", "arm,mali-t760"; 515 reg = <0x14ac0000 0x5000>; 516 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "job", "mmu", "gpu"; 520 status = "disabled"; 521 /* TODO: operating points for DVFS, cooling device */ 522 }; 523 524 mmc_0: mmc@15740000 { 525 compatible = "samsung,exynos7-dw-mshc-smu"; 526 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 reg = <0x15740000 0x2000>; 530 clocks = <&clock_fsys1 ACLK_MMC0>, 531 <&clock_top1 CLK_SCLK_MMC0>; 532 clock-names = "biu", "ciu"; 533 fifo-depth = <0x40>; 534 status = "disabled"; 535 }; 536 537 mmc_1: mmc@15750000 { 538 compatible = "samsung,exynos7-dw-mshc"; 539 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 reg = <0x15750000 0x2000>; 543 clocks = <&clock_fsys1 ACLK_MMC1>, 544 <&clock_top1 CLK_SCLK_MMC1>; 545 clock-names = "biu", "ciu"; 546 fifo-depth = <0x40>; 547 status = "disabled"; 548 }; 549 550 mmc_2: mmc@15560000 { 551 compatible = "samsung,exynos7-dw-mshc-smu"; 552 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <0x15560000 0x2000>; 556 clocks = <&clock_fsys0 ACLK_MMC2>, 557 <&clock_top1 CLK_SCLK_MMC2>; 558 clock-names = "biu", "ciu"; 559 fifo-depth = <0x40>; 560 status = "disabled"; 561 }; 562 563 adc: adc@13620000 { 564 compatible = "samsung,exynos7-adc"; 565 reg = <0x13620000 0x100>; 566 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&clock_peric0 PCLK_ADCIF>; 568 clock-names = "adc"; 569 #io-channel-cells = <1>; 570 io-channel-ranges; 571 status = "disabled"; 572 }; 573 574 pwm: pwm@136c0000 { 575 compatible = "samsung,exynos4210-pwm"; 576 reg = <0x136c0000 0x100>; 577 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 582 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 583 #pwm-cells = <3>; 584 clocks = <&clock_peric0 PCLK_PWM>; 585 clock-names = "timers"; 586 }; 587 588 tmuctrl_0: tmu@10060000 { 589 compatible = "samsung,exynos7-tmu"; 590 reg = <0x10060000 0x200>; 591 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&clock_peris PCLK_TMU>, 593 <&clock_peris SCLK_TMU>; 594 clock-names = "tmu_apbif", "tmu_sclk"; 595 #thermal-sensor-cells = <0>; 596 }; 597 598 ufs: ufs@15570000 { 599 compatible = "samsung,exynos7-ufs"; 600 reg = <0x15570000 0x100>, /* 0: HCI standard */ 601 <0x15570100 0x100>, /* 1: Vendor specificed */ 602 <0x15571000 0x200>, /* 2: UNIPRO */ 603 <0x15572000 0x300>; /* 3: UFS protector */ 604 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 605 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&clock_fsys1 ACLK_UFS20_LINK>, 607 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; 608 clock-names = "core_clk", "sclk_unipro_main"; 609 freq-table-hz = <0 0>, <0 0>; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 612 phys = <&ufs_phy>; 613 phy-names = "ufs-phy"; 614 status = "disabled"; 615 }; 616 617 ufs_phy: ufs-phy@15571800 { 618 compatible = "samsung,exynos7-ufs-phy"; 619 reg = <0x15571800 0x240>; 620 reg-names = "phy-pma"; 621 samsung,pmu-syscon = <&pmu_system_controller>; 622 #phy-cells = <0>; 623 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>, 624 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>, 625 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>, 626 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>; 627 clock-names = "ref_clk", "rx1_symbol_clk", 628 "rx0_symbol_clk", 629 "tx0_symbol_clk"; 630 }; 631 632 usbdrd_phy: phy@15500000 { 633 compatible = "samsung,exynos7-usbdrd-phy"; 634 reg = <0x15500000 0x100>; 635 clocks = <&clock_fsys0 ACLK_USBDRD300>, 636 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, 637 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, 638 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, 639 <&clock_fsys0 SCLK_USBDRD300_REFCLK>; 640 clock-names = "phy", "ref", "phy_pipe", 641 "phy_utmi", "itp"; 642 samsung,pmu-syscon = <&pmu_system_controller>; 643 #phy-cells = <1>; 644 }; 645 646 usbdrd3 { 647 compatible = "samsung,exynos7-dwusb3"; 648 clocks = <&clock_fsys0 ACLK_USBDRD300>, 649 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, 650 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; 651 clock-names = "usbdrd30", "usbdrd30_susp_clk", 652 "usbdrd30_axius_clk"; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 ranges; 656 657 dwc3@15400000 { 658 compatible = "snps,dwc3"; 659 reg = <0x15400000 0x10000>; 660 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 661 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 662 phy-names = "usb2-phy", "usb3-phy"; 663 }; 664 }; 665 }; 666 667 thermal-zones { 668 atlas_thermal: cluster0-thermal { 669 polling-delay-passive = <0>; /* milliseconds */ 670 polling-delay = <0>; /* milliseconds */ 671 thermal-sensors = <&tmuctrl_0>; 672 #include "exynos7-trip-points.dtsi" 673 }; 674 }; 675 676 timer { 677 compatible = "arm,armv8-timer"; 678 interrupts = <GIC_PPI 13 679 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 680 <GIC_PPI 14 681 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 682 <GIC_PPI 11 683 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 684 <GIC_PPI 10 685 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 686 }; 687}; 688 689#include "exynos7-pinctrl.dtsi" 690