1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver. 4 * 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 21 /* SPDIF-rx Register Map */ 22 #define STM32_SPDIFRX_CR 0x00 23 #define STM32_SPDIFRX_IMR 0x04 24 #define STM32_SPDIFRX_SR 0x08 25 #define STM32_SPDIFRX_IFCR 0x0C 26 #define STM32_SPDIFRX_DR 0x10 27 #define STM32_SPDIFRX_CSR 0x14 28 #define STM32_SPDIFRX_DIR 0x18 29 #define STM32_SPDIFRX_VERR 0x3F4 30 #define STM32_SPDIFRX_IDR 0x3F8 31 #define STM32_SPDIFRX_SIDR 0x3FC 32 33 /* Bit definition for SPDIF_CR register */ 34 #define SPDIFRX_CR_SPDIFEN_SHIFT 0 35 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT) 36 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT) 37 38 #define SPDIFRX_CR_RXDMAEN BIT(2) 39 #define SPDIFRX_CR_RXSTEO BIT(3) 40 41 #define SPDIFRX_CR_DRFMT_SHIFT 4 42 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT) 43 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT) 44 45 #define SPDIFRX_CR_PMSK BIT(6) 46 #define SPDIFRX_CR_VMSK BIT(7) 47 #define SPDIFRX_CR_CUMSK BIT(8) 48 #define SPDIFRX_CR_PTMSK BIT(9) 49 #define SPDIFRX_CR_CBDMAEN BIT(10) 50 #define SPDIFRX_CR_CHSEL_SHIFT 11 51 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT) 52 53 #define SPDIFRX_CR_NBTR_SHIFT 12 54 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT) 55 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT) 56 57 #define SPDIFRX_CR_WFA BIT(14) 58 59 #define SPDIFRX_CR_INSEL_SHIFT 16 60 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT) 61 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT) 62 63 #define SPDIFRX_CR_CKSEN_SHIFT 20 64 #define SPDIFRX_CR_CKSEN BIT(20) 65 #define SPDIFRX_CR_CKSBKPEN BIT(21) 66 67 /* Bit definition for SPDIFRX_IMR register */ 68 #define SPDIFRX_IMR_RXNEI BIT(0) 69 #define SPDIFRX_IMR_CSRNEIE BIT(1) 70 #define SPDIFRX_IMR_PERRIE BIT(2) 71 #define SPDIFRX_IMR_OVRIE BIT(3) 72 #define SPDIFRX_IMR_SBLKIE BIT(4) 73 #define SPDIFRX_IMR_SYNCDIE BIT(5) 74 #define SPDIFRX_IMR_IFEIE BIT(6) 75 76 #define SPDIFRX_XIMR_MASK GENMASK(6, 0) 77 78 /* Bit definition for SPDIFRX_SR register */ 79 #define SPDIFRX_SR_RXNE BIT(0) 80 #define SPDIFRX_SR_CSRNE BIT(1) 81 #define SPDIFRX_SR_PERR BIT(2) 82 #define SPDIFRX_SR_OVR BIT(3) 83 #define SPDIFRX_SR_SBD BIT(4) 84 #define SPDIFRX_SR_SYNCD BIT(5) 85 #define SPDIFRX_SR_FERR BIT(6) 86 #define SPDIFRX_SR_SERR BIT(7) 87 #define SPDIFRX_SR_TERR BIT(8) 88 89 #define SPDIFRX_SR_WIDTH5_SHIFT 16 90 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT) 91 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT) 92 93 /* Bit definition for SPDIFRX_IFCR register */ 94 #define SPDIFRX_IFCR_PERRCF BIT(2) 95 #define SPDIFRX_IFCR_OVRCF BIT(3) 96 #define SPDIFRX_IFCR_SBDCF BIT(4) 97 #define SPDIFRX_IFCR_SYNCDCF BIT(5) 98 99 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2) 100 101 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */ 102 #define SPDIFRX_DR0_DR_SHIFT 0 103 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT) 104 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT) 105 106 #define SPDIFRX_DR0_PE BIT(24) 107 108 #define SPDIFRX_DR0_V BIT(25) 109 #define SPDIFRX_DR0_U BIT(26) 110 #define SPDIFRX_DR0_C BIT(27) 111 112 #define SPDIFRX_DR0_PT_SHIFT 28 113 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT) 114 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT) 115 116 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */ 117 #define SPDIFRX_DR1_PE BIT(0) 118 #define SPDIFRX_DR1_V BIT(1) 119 #define SPDIFRX_DR1_U BIT(2) 120 #define SPDIFRX_DR1_C BIT(3) 121 122 #define SPDIFRX_DR1_PT_SHIFT 4 123 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT) 124 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT) 125 126 #define SPDIFRX_DR1_DR_SHIFT 8 127 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT) 128 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT) 129 130 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */ 131 #define SPDIFRX_DR1_DRNL1_SHIFT 0 132 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT) 133 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT) 134 135 #define SPDIFRX_DR1_DRNL2_SHIFT 16 136 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT) 137 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT) 138 139 /* Bit definition for SPDIFRX_CSR register */ 140 #define SPDIFRX_CSR_USR_SHIFT 0 141 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT) 142 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\ 143 >> SPDIFRX_CSR_USR_SHIFT) 144 145 #define SPDIFRX_CSR_CS_SHIFT 16 146 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT) 147 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\ 148 >> SPDIFRX_CSR_CS_SHIFT) 149 150 #define SPDIFRX_CSR_SOB BIT(24) 151 152 /* Bit definition for SPDIFRX_DIR register */ 153 #define SPDIFRX_DIR_THI_SHIFT 0 154 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT) 155 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT) 156 157 #define SPDIFRX_DIR_TLO_SHIFT 16 158 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT) 159 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT) 160 161 #define SPDIFRX_SPDIFEN_DISABLE 0x0 162 #define SPDIFRX_SPDIFEN_SYNC 0x1 163 #define SPDIFRX_SPDIFEN_ENABLE 0x3 164 165 /* Bit definition for SPDIFRX_VERR register */ 166 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0) 167 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4) 168 169 /* Bit definition for SPDIFRX_IDR register */ 170 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0) 171 172 /* Bit definition for SPDIFRX_SIDR register */ 173 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0) 174 175 #define SPDIFRX_IPIDR_NUMBER 0x00130041 176 177 #define SPDIFRX_IN1 0x1 178 #define SPDIFRX_IN2 0x2 179 #define SPDIFRX_IN3 0x3 180 #define SPDIFRX_IN4 0x4 181 #define SPDIFRX_IN5 0x5 182 #define SPDIFRX_IN6 0x6 183 #define SPDIFRX_IN7 0x7 184 #define SPDIFRX_IN8 0x8 185 186 #define SPDIFRX_NBTR_NONE 0x0 187 #define SPDIFRX_NBTR_3 0x1 188 #define SPDIFRX_NBTR_15 0x2 189 #define SPDIFRX_NBTR_63 0x3 190 191 #define SPDIFRX_DRFMT_RIGHT 0x0 192 #define SPDIFRX_DRFMT_LEFT 0x1 193 #define SPDIFRX_DRFMT_PACKED 0x2 194 195 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */ 196 #define SPDIFRX_CS_BYTES_NB 24 197 #define SPDIFRX_UB_BYTES_NB 48 198 199 /* 200 * CSR register is retrieved as a 32 bits word 201 * It contains 1 channel status byte and 2 user data bytes 202 * 2 S/PDIF frames are acquired to get all CS/UB bits 203 */ 204 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2) 205 206 /** 207 * struct stm32_spdifrx_data - private data of SPDIFRX 208 * @pdev: device data pointer 209 * @base: mmio register base virtual address 210 * @regmap: SPDIFRX register map pointer 211 * @regmap_conf: SPDIFRX register map configuration pointer 212 * @cs_completion: channel status retrieving completion 213 * @kclk: kernel clock feeding the SPDIFRX clock generator 214 * @dma_params: dma configuration data for rx channel 215 * @substream: PCM substream data pointer 216 * @dmab: dma buffer info pointer 217 * @ctrl_chan: dma channel for S/PDIF control bits 218 * @desc:dma async transaction descriptor 219 * @slave_config: dma slave channel runtime config pointer 220 * @phys_addr: SPDIFRX registers physical base address 221 * @lock: synchronization enabling lock 222 * @irq_lock: prevent race condition with IRQ on stream state 223 * @cs: channel status buffer 224 * @ub: user data buffer 225 * @irq: SPDIFRX interrupt line 226 * @refcount: keep count of opened DMA channels 227 */ 228 struct stm32_spdifrx_data { 229 struct platform_device *pdev; 230 void __iomem *base; 231 struct regmap *regmap; 232 const struct regmap_config *regmap_conf; 233 struct completion cs_completion; 234 struct clk *kclk; 235 struct snd_dmaengine_dai_dma_data dma_params; 236 struct snd_pcm_substream *substream; 237 struct snd_dma_buffer *dmab; 238 struct dma_chan *ctrl_chan; 239 struct dma_async_tx_descriptor *desc; 240 struct dma_slave_config slave_config; 241 dma_addr_t phys_addr; 242 spinlock_t lock; /* Sync enabling lock */ 243 spinlock_t irq_lock; /* Prevent race condition on stream state */ 244 unsigned char cs[SPDIFRX_CS_BYTES_NB]; 245 unsigned char ub[SPDIFRX_UB_BYTES_NB]; 246 int irq; 247 int refcount; 248 }; 249 250 static void stm32_spdifrx_dma_complete(void *data) 251 { 252 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data; 253 struct platform_device *pdev = spdifrx->pdev; 254 u32 *p_start = (u32 *)spdifrx->dmab->area; 255 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1; 256 u32 *ptr = p_start; 257 u16 *ub_ptr = (short *)spdifrx->ub; 258 int i = 0; 259 260 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 261 SPDIFRX_CR_CBDMAEN, 262 (unsigned int)~SPDIFRX_CR_CBDMAEN); 263 264 if (!spdifrx->dmab->area) 265 return; 266 267 while (ptr <= p_end) { 268 if (*ptr & SPDIFRX_CSR_SOB) 269 break; 270 ptr++; 271 } 272 273 if (ptr > p_end) { 274 dev_err(&pdev->dev, "Start of S/PDIF block not found\n"); 275 return; 276 } 277 278 while (i < SPDIFRX_CS_BYTES_NB) { 279 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr); 280 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++); 281 if (ptr > p_end) { 282 dev_err(&pdev->dev, "Failed to get channel status\n"); 283 return; 284 } 285 i++; 286 } 287 288 complete(&spdifrx->cs_completion); 289 } 290 291 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx) 292 { 293 dma_cookie_t cookie; 294 int err; 295 296 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan, 297 spdifrx->dmab->addr, 298 SPDIFRX_CSR_BUF_LENGTH, 299 DMA_DEV_TO_MEM, 300 DMA_CTRL_ACK); 301 if (!spdifrx->desc) 302 return -EINVAL; 303 304 spdifrx->desc->callback = stm32_spdifrx_dma_complete; 305 spdifrx->desc->callback_param = spdifrx; 306 cookie = dmaengine_submit(spdifrx->desc); 307 err = dma_submit_error(cookie); 308 if (err) 309 return -EINVAL; 310 311 dma_async_issue_pending(spdifrx->ctrl_chan); 312 313 return 0; 314 } 315 316 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx) 317 { 318 dmaengine_terminate_async(spdifrx->ctrl_chan); 319 } 320 321 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx) 322 { 323 int cr, cr_mask, imr, ret; 324 unsigned long flags; 325 326 /* Enable IRQs */ 327 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE; 328 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr); 329 if (ret) 330 return ret; 331 332 spin_lock_irqsave(&spdifrx->lock, flags); 333 334 spdifrx->refcount++; 335 336 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 337 338 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) { 339 /* 340 * Start sync if SPDIFRX is still in idle state. 341 * SPDIFRX reception enabled when sync done 342 */ 343 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n"); 344 345 /* 346 * SPDIFRX configuration: 347 * Wait for activity before starting sync process. This avoid 348 * to issue sync errors when spdif signal is missing on input. 349 * Preamble, CS, user, validity and parity error bits not copied 350 * to DR register. 351 */ 352 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK | 353 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO; 354 cr_mask = cr; 355 356 cr |= SPDIFRX_CR_NBTRSET(SPDIFRX_NBTR_63); 357 cr_mask |= SPDIFRX_CR_NBTR_MASK; 358 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 359 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK; 360 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 361 cr_mask, cr); 362 if (ret < 0) 363 dev_err(&spdifrx->pdev->dev, 364 "Failed to start synchronization\n"); 365 } 366 367 spin_unlock_irqrestore(&spdifrx->lock, flags); 368 369 return ret; 370 } 371 372 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx) 373 { 374 int cr, cr_mask, reg; 375 unsigned long flags; 376 377 spin_lock_irqsave(&spdifrx->lock, flags); 378 379 if (--spdifrx->refcount) { 380 spin_unlock_irqrestore(&spdifrx->lock, flags); 381 return; 382 } 383 384 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 385 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN; 386 387 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr); 388 389 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 390 SPDIFRX_XIMR_MASK, 0); 391 392 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 393 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK); 394 395 /* dummy read to clear CSRNE and RXNE in status register */ 396 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); 397 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); 398 399 spin_unlock_irqrestore(&spdifrx->lock, flags); 400 } 401 402 static int stm32_spdifrx_dma_ctrl_register(struct device *dev, 403 struct stm32_spdifrx_data *spdifrx) 404 { 405 int ret; 406 407 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl"); 408 if (IS_ERR(spdifrx->ctrl_chan)) { 409 dev_err(dev, "dma_request_slave_channel failed\n"); 410 return PTR_ERR(spdifrx->ctrl_chan); 411 } 412 413 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer), 414 GFP_KERNEL); 415 if (!spdifrx->dmab) 416 return -ENOMEM; 417 418 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM; 419 spdifrx->dmab->dev.dev = dev; 420 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev, 421 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab); 422 if (ret < 0) { 423 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret); 424 return ret; 425 } 426 427 spdifrx->slave_config.direction = DMA_DEV_TO_MEM; 428 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr + 429 STM32_SPDIFRX_CSR); 430 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr; 431 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 432 spdifrx->slave_config.src_maxburst = 1; 433 434 ret = dmaengine_slave_config(spdifrx->ctrl_chan, 435 &spdifrx->slave_config); 436 if (ret < 0) { 437 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret); 438 spdifrx->ctrl_chan = NULL; 439 } 440 441 return ret; 442 }; 443 444 static const char * const spdifrx_enum_input[] = { 445 "in0", "in1", "in2", "in3" 446 }; 447 448 /* By default CS bits are retrieved from channel A */ 449 static const char * const spdifrx_enum_cs_channel[] = { 450 "A", "B" 451 }; 452 453 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input, 454 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT, 455 spdifrx_enum_input); 456 457 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel, 458 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT, 459 spdifrx_enum_cs_channel); 460 461 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol, 462 struct snd_ctl_elem_info *uinfo) 463 { 464 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 465 uinfo->count = 1; 466 467 return 0; 468 } 469 470 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol, 471 struct snd_ctl_elem_info *uinfo) 472 { 473 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 474 uinfo->count = 1; 475 476 return 0; 477 } 478 479 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx) 480 { 481 int ret = 0; 482 483 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB); 484 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB); 485 486 ret = stm32_spdifrx_dma_ctrl_start(spdifrx); 487 if (ret < 0) 488 return ret; 489 490 ret = clk_prepare_enable(spdifrx->kclk); 491 if (ret) { 492 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 493 return ret; 494 } 495 496 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 497 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN); 498 if (ret < 0) 499 goto end; 500 501 ret = stm32_spdifrx_start_sync(spdifrx); 502 if (ret < 0) 503 goto end; 504 505 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion, 506 msecs_to_jiffies(100)) 507 <= 0) { 508 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n"); 509 ret = -EAGAIN; 510 } 511 512 stm32_spdifrx_stop(spdifrx); 513 stm32_spdifrx_dma_ctrl_stop(spdifrx); 514 515 end: 516 clk_disable_unprepare(spdifrx->kclk); 517 518 return ret; 519 } 520 521 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol, 522 struct snd_ctl_elem_value *ucontrol) 523 { 524 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 525 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 526 527 stm32_spdifrx_get_ctrl_data(spdifrx); 528 529 ucontrol->value.iec958.status[0] = spdifrx->cs[0]; 530 ucontrol->value.iec958.status[1] = spdifrx->cs[1]; 531 ucontrol->value.iec958.status[2] = spdifrx->cs[2]; 532 ucontrol->value.iec958.status[3] = spdifrx->cs[3]; 533 ucontrol->value.iec958.status[4] = spdifrx->cs[4]; 534 535 return 0; 536 } 537 538 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol, 539 struct snd_ctl_elem_value *ucontrol) 540 { 541 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 542 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 543 544 stm32_spdifrx_get_ctrl_data(spdifrx); 545 546 ucontrol->value.iec958.status[0] = spdifrx->ub[0]; 547 ucontrol->value.iec958.status[1] = spdifrx->ub[1]; 548 ucontrol->value.iec958.status[2] = spdifrx->ub[2]; 549 ucontrol->value.iec958.status[3] = spdifrx->ub[3]; 550 ucontrol->value.iec958.status[4] = spdifrx->ub[4]; 551 552 return 0; 553 } 554 555 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = { 556 /* Channel status control */ 557 { 558 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 559 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 560 .access = SNDRV_CTL_ELEM_ACCESS_READ | 561 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 562 .info = stm32_spdifrx_info, 563 .get = stm32_spdifrx_capture_get, 564 }, 565 /* User bits control */ 566 { 567 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 568 .name = "IEC958 User Bit Capture Default", 569 .access = SNDRV_CTL_ELEM_ACCESS_READ | 570 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 571 .info = stm32_spdifrx_ub_info, 572 .get = stm32_spdif_user_bits_get, 573 }, 574 }; 575 576 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = { 577 SOC_ENUM("SPDIFRX input", ctrl_enum_input), 578 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel), 579 }; 580 581 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai) 582 { 583 int ret; 584 585 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls, 586 ARRAY_SIZE(stm32_spdifrx_iec_ctrls)); 587 if (ret < 0) 588 return ret; 589 590 return snd_soc_add_component_controls(cpu_dai->component, 591 stm32_spdifrx_ctrls, 592 ARRAY_SIZE(stm32_spdifrx_ctrls)); 593 } 594 595 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai) 596 { 597 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev); 598 599 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr + 600 STM32_SPDIFRX_DR); 601 spdifrx->dma_params.maxburst = 1; 602 603 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 604 605 return stm32_spdifrx_dai_register_ctrls(cpu_dai); 606 } 607 608 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) 609 { 610 switch (reg) { 611 case STM32_SPDIFRX_CR: 612 case STM32_SPDIFRX_IMR: 613 case STM32_SPDIFRX_SR: 614 case STM32_SPDIFRX_IFCR: 615 case STM32_SPDIFRX_DR: 616 case STM32_SPDIFRX_CSR: 617 case STM32_SPDIFRX_DIR: 618 case STM32_SPDIFRX_VERR: 619 case STM32_SPDIFRX_IDR: 620 case STM32_SPDIFRX_SIDR: 621 return true; 622 default: 623 return false; 624 } 625 } 626 627 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 628 { 629 switch (reg) { 630 case STM32_SPDIFRX_DR: 631 case STM32_SPDIFRX_CSR: 632 case STM32_SPDIFRX_SR: 633 case STM32_SPDIFRX_DIR: 634 return true; 635 default: 636 return false; 637 } 638 } 639 640 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 641 { 642 switch (reg) { 643 case STM32_SPDIFRX_CR: 644 case STM32_SPDIFRX_IMR: 645 case STM32_SPDIFRX_IFCR: 646 return true; 647 default: 648 return false; 649 } 650 } 651 652 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = { 653 .reg_bits = 32, 654 .reg_stride = 4, 655 .val_bits = 32, 656 .max_register = STM32_SPDIFRX_SIDR, 657 .readable_reg = stm32_spdifrx_readable_reg, 658 .volatile_reg = stm32_spdifrx_volatile_reg, 659 .writeable_reg = stm32_spdifrx_writeable_reg, 660 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1, 661 .fast_io = true, 662 .cache_type = REGCACHE_FLAT, 663 }; 664 665 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid) 666 { 667 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid; 668 struct platform_device *pdev = spdifrx->pdev; 669 unsigned int cr, mask, sr, imr; 670 unsigned int flags, sync_state; 671 int err = 0, err_xrun = 0; 672 673 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr); 674 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr); 675 676 mask = imr & SPDIFRX_XIMR_MASK; 677 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */ 678 if (mask & SPDIFRX_IMR_IFEIE) 679 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); 680 681 flags = sr & mask; 682 if (!flags) { 683 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n", 684 sr, imr); 685 return IRQ_NONE; 686 } 687 688 /* Clear IRQs */ 689 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR, 690 SPDIFRX_XIFCR_MASK, flags); 691 692 if (flags & SPDIFRX_SR_PERR) { 693 dev_dbg(&pdev->dev, "Parity error\n"); 694 err_xrun = 1; 695 } 696 697 if (flags & SPDIFRX_SR_OVR) { 698 dev_dbg(&pdev->dev, "Overrun error\n"); 699 err_xrun = 1; 700 } 701 702 if (flags & SPDIFRX_SR_SBD) 703 dev_dbg(&pdev->dev, "Synchronization block detected\n"); 704 705 if (flags & SPDIFRX_SR_SYNCD) { 706 dev_dbg(&pdev->dev, "Synchronization done\n"); 707 708 /* Enable spdifrx */ 709 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE); 710 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 711 SPDIFRX_CR_SPDIFEN_MASK, cr); 712 } 713 714 if (flags & SPDIFRX_SR_FERR) { 715 dev_dbg(&pdev->dev, "Frame error\n"); 716 err = 1; 717 } 718 719 if (flags & SPDIFRX_SR_SERR) { 720 dev_dbg(&pdev->dev, "Synchronization error\n"); 721 err = 1; 722 } 723 724 if (flags & SPDIFRX_SR_TERR) { 725 dev_dbg(&pdev->dev, "Timeout error\n"); 726 err = 1; 727 } 728 729 if (err) { 730 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr); 731 sync_state = FIELD_GET(SPDIFRX_CR_SPDIFEN_MASK, cr) && 732 SPDIFRX_SPDIFEN_SYNC; 733 734 /* SPDIFRX is in STATE_STOP. Disable SPDIFRX to clear errors */ 735 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE); 736 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 737 SPDIFRX_CR_SPDIFEN_MASK, cr); 738 739 /* If SPDIFRX was in STATE_SYNC, retry synchro */ 740 if (sync_state) { 741 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC); 742 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 743 SPDIFRX_CR_SPDIFEN_MASK, cr); 744 return IRQ_HANDLED; 745 } 746 747 spin_lock(&spdifrx->irq_lock); 748 if (spdifrx->substream) 749 snd_pcm_stop(spdifrx->substream, 750 SNDRV_PCM_STATE_DISCONNECTED); 751 spin_unlock(&spdifrx->irq_lock); 752 753 return IRQ_HANDLED; 754 } 755 756 spin_lock(&spdifrx->irq_lock); 757 if (err_xrun && spdifrx->substream) 758 snd_pcm_stop_xrun(spdifrx->substream); 759 spin_unlock(&spdifrx->irq_lock); 760 761 return IRQ_HANDLED; 762 } 763 764 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream, 765 struct snd_soc_dai *cpu_dai) 766 { 767 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 768 unsigned long flags; 769 int ret; 770 771 spin_lock_irqsave(&spdifrx->irq_lock, flags); 772 spdifrx->substream = substream; 773 spin_unlock_irqrestore(&spdifrx->irq_lock, flags); 774 775 ret = clk_prepare_enable(spdifrx->kclk); 776 if (ret) 777 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret); 778 779 return ret; 780 } 781 782 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream, 783 struct snd_pcm_hw_params *params, 784 struct snd_soc_dai *cpu_dai) 785 { 786 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 787 int data_size = params_width(params); 788 int fmt; 789 790 switch (data_size) { 791 case 16: 792 fmt = SPDIFRX_DRFMT_PACKED; 793 break; 794 case 32: 795 fmt = SPDIFRX_DRFMT_LEFT; 796 break; 797 default: 798 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n"); 799 return -EINVAL; 800 } 801 802 /* 803 * Set buswidth to 4 bytes for all data formats. 804 * Packed format: transfer 2 x 2 bytes samples 805 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte 806 */ 807 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 808 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params); 809 810 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 811 SPDIFRX_CR_DRFMT_MASK, 812 SPDIFRX_CR_DRFMTSET(fmt)); 813 } 814 815 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 816 struct snd_soc_dai *cpu_dai) 817 { 818 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 819 int ret = 0; 820 821 switch (cmd) { 822 case SNDRV_PCM_TRIGGER_START: 823 case SNDRV_PCM_TRIGGER_RESUME: 824 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 825 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, 826 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE); 827 828 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, 829 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN); 830 831 ret = stm32_spdifrx_start_sync(spdifrx); 832 break; 833 case SNDRV_PCM_TRIGGER_SUSPEND: 834 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 835 case SNDRV_PCM_TRIGGER_STOP: 836 stm32_spdifrx_stop(spdifrx); 837 break; 838 default: 839 return -EINVAL; 840 } 841 842 return ret; 843 } 844 845 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream, 846 struct snd_soc_dai *cpu_dai) 847 { 848 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai); 849 unsigned long flags; 850 851 spin_lock_irqsave(&spdifrx->irq_lock, flags); 852 spdifrx->substream = NULL; 853 spin_unlock_irqrestore(&spdifrx->irq_lock, flags); 854 855 clk_disable_unprepare(spdifrx->kclk); 856 } 857 858 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = { 859 .startup = stm32_spdifrx_startup, 860 .hw_params = stm32_spdifrx_hw_params, 861 .trigger = stm32_spdifrx_trigger, 862 .shutdown = stm32_spdifrx_shutdown, 863 }; 864 865 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = { 866 { 867 .probe = stm32_spdifrx_dai_probe, 868 .capture = { 869 .stream_name = "CPU-Capture", 870 .channels_min = 1, 871 .channels_max = 2, 872 .rates = SNDRV_PCM_RATE_8000_192000, 873 .formats = SNDRV_PCM_FMTBIT_S32_LE | 874 SNDRV_PCM_FMTBIT_S16_LE, 875 }, 876 .ops = &stm32_spdifrx_pcm_dai_ops, 877 } 878 }; 879 880 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = { 881 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 882 .buffer_bytes_max = 8 * PAGE_SIZE, 883 .period_bytes_min = 1024, 884 .period_bytes_max = 4 * PAGE_SIZE, 885 .periods_min = 2, 886 .periods_max = 8, 887 }; 888 889 static const struct snd_soc_component_driver stm32_spdifrx_component = { 890 .name = "stm32-spdifrx", 891 }; 892 893 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = { 894 .pcm_hardware = &stm32_spdifrx_pcm_hw, 895 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 896 }; 897 898 static const struct of_device_id stm32_spdifrx_ids[] = { 899 { 900 .compatible = "st,stm32h7-spdifrx", 901 .data = &stm32_h7_spdifrx_regmap_conf 902 }, 903 {} 904 }; 905 906 static int stm32_spdifrx_parse_of(struct platform_device *pdev, 907 struct stm32_spdifrx_data *spdifrx) 908 { 909 struct device_node *np = pdev->dev.of_node; 910 const struct of_device_id *of_id; 911 struct resource *res; 912 913 if (!np) 914 return -ENODEV; 915 916 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev); 917 if (of_id) 918 spdifrx->regmap_conf = 919 (const struct regmap_config *)of_id->data; 920 else 921 return -EINVAL; 922 923 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 924 spdifrx->base = devm_ioremap_resource(&pdev->dev, res); 925 if (IS_ERR(spdifrx->base)) 926 return PTR_ERR(spdifrx->base); 927 928 spdifrx->phys_addr = res->start; 929 930 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk"); 931 if (IS_ERR(spdifrx->kclk)) { 932 dev_err(&pdev->dev, "Could not get kclk\n"); 933 return PTR_ERR(spdifrx->kclk); 934 } 935 936 spdifrx->irq = platform_get_irq(pdev, 0); 937 if (spdifrx->irq < 0) 938 return spdifrx->irq; 939 940 return 0; 941 } 942 943 static int stm32_spdifrx_probe(struct platform_device *pdev) 944 { 945 struct stm32_spdifrx_data *spdifrx; 946 struct reset_control *rst; 947 const struct snd_dmaengine_pcm_config *pcm_config = NULL; 948 u32 ver, idr; 949 int ret; 950 951 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL); 952 if (!spdifrx) 953 return -ENOMEM; 954 955 spdifrx->pdev = pdev; 956 init_completion(&spdifrx->cs_completion); 957 spin_lock_init(&spdifrx->lock); 958 spin_lock_init(&spdifrx->irq_lock); 959 960 platform_set_drvdata(pdev, spdifrx); 961 962 ret = stm32_spdifrx_parse_of(pdev, spdifrx); 963 if (ret) 964 return ret; 965 966 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk", 967 spdifrx->base, 968 spdifrx->regmap_conf); 969 if (IS_ERR(spdifrx->regmap)) { 970 dev_err(&pdev->dev, "Regmap init failed\n"); 971 return PTR_ERR(spdifrx->regmap); 972 } 973 974 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0, 975 dev_name(&pdev->dev), spdifrx); 976 if (ret) { 977 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 978 return ret; 979 } 980 981 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 982 if (!IS_ERR(rst)) { 983 reset_control_assert(rst); 984 udelay(2); 985 reset_control_deassert(rst); 986 } 987 988 ret = devm_snd_soc_register_component(&pdev->dev, 989 &stm32_spdifrx_component, 990 stm32_spdifrx_dai, 991 ARRAY_SIZE(stm32_spdifrx_dai)); 992 if (ret) 993 return ret; 994 995 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx); 996 if (ret) 997 goto error; 998 999 pcm_config = &stm32_spdifrx_pcm_config; 1000 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0); 1001 if (ret) { 1002 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret); 1003 goto error; 1004 } 1005 1006 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr); 1007 if (ret) 1008 goto error; 1009 1010 if (idr == SPDIFRX_IPIDR_NUMBER) { 1011 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver); 1012 1013 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n", 1014 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver), 1015 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver)); 1016 } 1017 1018 return ret; 1019 1020 error: 1021 if (!IS_ERR(spdifrx->ctrl_chan)) 1022 dma_release_channel(spdifrx->ctrl_chan); 1023 if (spdifrx->dmab) 1024 snd_dma_free_pages(spdifrx->dmab); 1025 1026 return ret; 1027 } 1028 1029 static int stm32_spdifrx_remove(struct platform_device *pdev) 1030 { 1031 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev); 1032 1033 if (spdifrx->ctrl_chan) 1034 dma_release_channel(spdifrx->ctrl_chan); 1035 1036 if (spdifrx->dmab) 1037 snd_dma_free_pages(spdifrx->dmab); 1038 1039 return 0; 1040 } 1041 1042 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids); 1043 1044 #ifdef CONFIG_PM_SLEEP 1045 static int stm32_spdifrx_suspend(struct device *dev) 1046 { 1047 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1048 1049 regcache_cache_only(spdifrx->regmap, true); 1050 regcache_mark_dirty(spdifrx->regmap); 1051 1052 return 0; 1053 } 1054 1055 static int stm32_spdifrx_resume(struct device *dev) 1056 { 1057 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev); 1058 1059 regcache_cache_only(spdifrx->regmap, false); 1060 1061 return regcache_sync(spdifrx->regmap); 1062 } 1063 #endif /* CONFIG_PM_SLEEP */ 1064 1065 static const struct dev_pm_ops stm32_spdifrx_pm_ops = { 1066 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume) 1067 }; 1068 1069 static struct platform_driver stm32_spdifrx_driver = { 1070 .driver = { 1071 .name = "st,stm32-spdifrx", 1072 .of_match_table = stm32_spdifrx_ids, 1073 .pm = &stm32_spdifrx_pm_ops, 1074 }, 1075 .probe = stm32_spdifrx_probe, 1076 .remove = stm32_spdifrx_remove, 1077 }; 1078 1079 module_platform_driver(stm32_spdifrx_driver); 1080 1081 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface"); 1082 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>"); 1083 MODULE_ALIAS("platform:stm32-spdifrx"); 1084 MODULE_LICENSE("GPL v2"); 1085