1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2018 Intel Corporation. All rights reserved. 7 // 8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10 // Rander Wang <rander.wang@intel.com> 11 // Keyon Jie <yang.jie@linux.intel.com> 12 // 13 14 /* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18 #include <linux/module.h> 19 #include <sound/hdaudio_ext.h> 20 #include <sound/hda_register.h> 21 #include "../ops.h" 22 #include "hda.h" 23 24 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 25 static int hda_codec_mask = -1; 26 module_param_named(codec_mask, hda_codec_mask, int, 0444); 27 MODULE_PARM_DESC(codec_mask, "SOF HDA codec mask for probing"); 28 #endif 29 30 /* 31 * HDA Operations. 32 */ 33 34 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset) 35 { 36 unsigned long timeout; 37 u32 gctl = 0; 38 u32 val; 39 40 /* 0 to enter reset and 1 to exit reset */ 41 val = reset ? 0 : SOF_HDA_GCTL_RESET; 42 43 /* enter/exit HDA controller reset */ 44 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL, 45 SOF_HDA_GCTL_RESET, val); 46 47 /* wait to enter/exit reset */ 48 timeout = jiffies + msecs_to_jiffies(HDA_DSP_CTRL_RESET_TIMEOUT); 49 while (time_before(jiffies, timeout)) { 50 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL); 51 if ((gctl & SOF_HDA_GCTL_RESET) == val) 52 return 0; 53 usleep_range(500, 1000); 54 } 55 56 /* enter/exit reset failed */ 57 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n", 58 reset ? "reset" : "ready", gctl); 59 return -EIO; 60 } 61 62 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev) 63 { 64 struct hdac_bus *bus = sof_to_bus(sdev); 65 u32 cap, offset, feature; 66 int count = 0; 67 68 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH); 69 70 do { 71 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset); 72 73 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n", 74 offset & SOF_HDA_CAP_NEXT_MASK); 75 76 feature = (cap & SOF_HDA_CAP_ID_MASK) >> SOF_HDA_CAP_ID_OFF; 77 78 switch (feature) { 79 case SOF_HDA_PP_CAP_ID: 80 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n", 81 offset); 82 bus->ppcap = bus->remap_addr + offset; 83 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap; 84 break; 85 case SOF_HDA_SPIB_CAP_ID: 86 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n", 87 offset); 88 bus->spbcap = bus->remap_addr + offset; 89 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap; 90 break; 91 case SOF_HDA_DRSM_CAP_ID: 92 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n", 93 offset); 94 bus->drsmcap = bus->remap_addr + offset; 95 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap; 96 break; 97 case SOF_HDA_GTS_CAP_ID: 98 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n", 99 offset); 100 bus->gtscap = bus->remap_addr + offset; 101 break; 102 case SOF_HDA_ML_CAP_ID: 103 dev_dbg(sdev->dev, "found ML capability at 0x%x\n", 104 offset); 105 bus->mlcap = bus->remap_addr + offset; 106 break; 107 default: 108 dev_vdbg(sdev->dev, "found capability %d at 0x%x\n", 109 feature, offset); 110 break; 111 } 112 113 offset = cap & SOF_HDA_CAP_NEXT_MASK; 114 } while (count++ <= SOF_HDA_MAX_CAPS && offset); 115 116 return 0; 117 } 118 119 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable) 120 { 121 u32 val = enable ? SOF_HDA_PPCTL_GPROCEN : 0; 122 123 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 124 SOF_HDA_PPCTL_GPROCEN, val); 125 } 126 127 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable) 128 { 129 u32 val = enable ? SOF_HDA_PPCTL_PIE : 0; 130 131 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL, 132 SOF_HDA_PPCTL_PIE, val); 133 } 134 135 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable) 136 { 137 u32 val = enable ? PCI_CGCTL_MISCBDCGE_MASK : 0; 138 139 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val); 140 } 141 142 /* 143 * enable/disable audio dsp clock gating and power gating bits. 144 * This allows the HW to opportunistically power and clock gate 145 * the audio dsp when it is idle 146 */ 147 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable) 148 { 149 u32 val; 150 151 /* enable/disable audio dsp clock gating */ 152 val = enable ? PCI_CGCTL_ADSPDCGE : 0; 153 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val); 154 155 /* enable/disable DMI Link L1 support */ 156 val = enable ? HDA_VS_INTEL_EM2_L1SEN : 0; 157 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2, 158 HDA_VS_INTEL_EM2_L1SEN, val); 159 160 /* enable/disable audio dsp power gating */ 161 val = enable ? 0 : PCI_PGCTL_ADSPPGD; 162 snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val); 163 164 return 0; 165 } 166 167 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset) 168 { 169 struct hdac_bus *bus = sof_to_bus(sdev); 170 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 171 struct hdac_ext_link *hlink; 172 #endif 173 struct hdac_stream *stream; 174 int sd_offset, ret = 0; 175 176 if (bus->chip_init) 177 return 0; 178 179 hda_dsp_ctrl_misc_clock_gating(sdev, false); 180 181 if (full_reset) { 182 /* reset HDA controller */ 183 ret = hda_dsp_ctrl_link_reset(sdev, true); 184 if (ret < 0) { 185 dev_err(sdev->dev, "error: failed to reset HDA controller\n"); 186 return ret; 187 } 188 189 usleep_range(500, 1000); 190 191 /* exit HDA controller reset */ 192 ret = hda_dsp_ctrl_link_reset(sdev, false); 193 if (ret < 0) { 194 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n"); 195 return ret; 196 } 197 198 usleep_range(1000, 1200); 199 } 200 201 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 202 /* check to see if controller is ready */ 203 if (!snd_hdac_chip_readb(bus, GCTL)) { 204 dev_dbg(bus->dev, "controller not ready!\n"); 205 return -EBUSY; 206 } 207 208 /* Accept unsolicited responses */ 209 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL); 210 211 /* detect codecs */ 212 if (!bus->codec_mask) { 213 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); 214 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); 215 } 216 217 if (hda_codec_mask != -1) { 218 bus->codec_mask &= hda_codec_mask; 219 dev_dbg(bus->dev, "filtered codec_mask = 0x%lx\n", 220 bus->codec_mask); 221 } 222 #endif 223 224 /* clear stream status */ 225 list_for_each_entry(stream, &bus->stream_list, list) { 226 sd_offset = SOF_STREAM_SD_OFFSET(stream); 227 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 228 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS, 229 SOF_HDA_CL_DMA_SD_INT_MASK); 230 } 231 232 /* clear WAKESTS */ 233 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, 234 SOF_HDA_WAKESTS_INT_MASK); 235 236 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 237 /* clear rirb status */ 238 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 239 #endif 240 241 /* clear interrupt status register */ 242 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, 243 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM); 244 245 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 246 /* initialize the codec command I/O */ 247 snd_hdac_bus_init_cmd_io(bus); 248 #endif 249 250 /* enable CIE and GIE interrupts */ 251 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 252 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 253 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN); 254 255 /* program the position buffer */ 256 if (bus->use_posbuf && bus->posbuf.addr) { 257 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE, 258 (u32)bus->posbuf.addr); 259 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE, 260 upper_32_bits(bus->posbuf.addr)); 261 } 262 263 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 264 /* Reset stream-to-link mapping */ 265 list_for_each_entry(hlink, &bus->hlink_list, list) 266 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV); 267 #endif 268 269 bus->chip_init = true; 270 271 hda_dsp_ctrl_misc_clock_gating(sdev, true); 272 273 return ret; 274 } 275 276 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev) 277 { 278 struct hdac_bus *bus = sof_to_bus(sdev); 279 struct hdac_stream *stream; 280 int sd_offset; 281 282 if (!bus->chip_init) 283 return; 284 285 /* disable interrupts in stream descriptor */ 286 list_for_each_entry(stream, &bus->stream_list, list) { 287 sd_offset = SOF_STREAM_SD_OFFSET(stream); 288 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 289 sd_offset + 290 SOF_HDA_ADSP_REG_CL_SD_CTL, 291 SOF_HDA_CL_DMA_SD_INT_MASK, 292 0); 293 } 294 295 /* disable SIE for all streams */ 296 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 297 SOF_HDA_INT_ALL_STREAM, 0); 298 299 /* disable controller CIE and GIE */ 300 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 301 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 302 0); 303 304 /* clear stream status */ 305 list_for_each_entry(stream, &bus->stream_list, list) { 306 sd_offset = SOF_STREAM_SD_OFFSET(stream); 307 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 308 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS, 309 SOF_HDA_CL_DMA_SD_INT_MASK); 310 } 311 312 /* clear WAKESTS */ 313 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS, 314 SOF_HDA_WAKESTS_INT_MASK); 315 316 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 317 /* clear rirb status */ 318 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 319 #endif 320 321 /* clear interrupt status register */ 322 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS, 323 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM); 324 325 #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 326 /* disable CORB/RIRB */ 327 snd_hdac_bus_stop_cmd_io(bus); 328 #endif 329 /* disable position buffer */ 330 if (bus->posbuf.addr) { 331 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 332 SOF_HDA_ADSP_DPLBASE, 0); 333 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, 334 SOF_HDA_ADSP_DPUBASE, 0); 335 } 336 337 bus->chip_init = false; 338 } 339